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The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture and fabrication flow, and using undoped source and drain terminals, the device allows for a fast electrical evaluation of semiconductor films on insulators (SOI) and gate stacks. This paper describes an electrical model that reproduces the peculiar transfer characteristics of a junctionless EZ-FET. The model is then simplified to develop a pragmatic parameter extraction methodology. This methodology is experimentally validated and provides the electrical properties of SOI films (mobility, threshold voltage) for both electrons and holes. [ABSTRACT FROM AUTHOR]

• The gate-induced drain leakage (GIDL) in stacked nanowire transistors for temperatures of operation between 300 K and 580 K is experimentally assessed for devices with different channel lengths and fin widths. • The temperature rise increases the current due to GIDL and its dependence on the device width. • For a fixed negative gate voltage the channel length reduction increases the GIDL current for nanowires independent of the temperature, except for devices suffering from threshold voltage roll-off due to short-channel effect. • Three-dimensional TCAD simulations showed that drain leakage is mainly composed of band-to-band tunneling rather than junction leakage, even at high temperatures. • The band-to-band generation rate intensity is larger in the bottom nanowire, with Ω-gate architecture than in the top GAA nanowire. • Band-to-band generation becomes higher as length is reduced and fin width is increased and is larger in the drain extension and gate overlap regions. • The temperature rise changes valence and conduction energy levels causing the reduction of the lateral distance between the two levels, favoring the transversal band-to-band tunneling. This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling. [ABSTRACT FROM AUTHOR]

• A crossbar array of silicon nitride resistive memories was fabricated on SOI. • Multi-Level-Cell capabilities were demonstrated through DC measurements and model. • A comprehensive analysis of the MRL gates' design and optimizations were done. In this work, the fabrication of crossbar arrays of silicon nitride resistive memories on silicon-on-insulator substrate and their utilization to realize multi-rationed logic circuits are presented. Typical electrical characterization of the memristors revealed their ability of multi-state operation by the presence of 12 well separated resistance levels. Through a dedicated modeling and fitting procedure of these levels, a reconfigurable logic based on memristor rationed logic scheme is designed and a crossbar integration methodology was proposed. Finally, several circuitry aspects were simulated in SPICE with a silicon nitride SOI crossbar array calibrated model and power optimization prospects were discussed. [ABSTRACT FROM AUTHOR]

This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affecting the ac response of pseudo-MOSFET structure for SOI wafer with thin SOI film by using simple series and parallel circuits composed of resistance and capacitance. Our measurement results show the gate bias range where the influence of the contact resistance becomes dominant in measurements with single and multiple probes. The degradation of the capacitance measured at high frequency is also analyzed by constructing an equivalent circuit, which detach the influence of the contact and channel resistances quantitatively. The necessity to carefully account for the influence of the contact resistance in pseudo-MOS method is clarified. [ABSTRACT FROM AUTHOR]

We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low I ON and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (L rt) yields a very steep slope and higher I ON compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (1021 cm−3) thin layer at the bottom for extremely small body thickness (T Si < 7 nm), increases I ON even for small gate lengths (L G < 100 nm). The implementation of an embedded tip in the source enhances the maximum electric field at the source/channel junction, but the impact on the performance is limited because the tunneling area is not increased. Therefore, this architecture provides a performance similar to a standard TFET. TCAD simulations using SiGe with different germanium concentrations (30% and 50%) and pure germanium, instead of silicon, show an increase of the interband tunneling current when using an ultrahigh dopant concentration thin boron layer for small gate lengths (L G < 50 nm). The reduction of the tunneling current using a relatively thick channel (11–7 nm) can be compensated by using a higher germanium concentration to reduce the energy bandgap. However, this will increase the density of defects causing a TAT tunneling instead of interband tunneling, jeopardizing the possibility of achieving a subthreshold swing below 60 mV/dec. [ABSTRACT FROM AUTHOR]

We propose for the first time a method based on C-V measurement to extract the bridge doping profile which governs the operation and performance of A2RAM capacitorless memory cell. Assessed with TCAD simulation and simple extraction model adapted from bulk devices, this technique is validated with experimental data. [ABSTRACT FROM AUTHOR]

Highlights • A methodology is proposed to separate mobility of each level of stacked NW structure. • Lower low filed mobility is obtained for top GAA level comparing to Ω bottom NW. • Mobility varies with VB due to holes concentration reduction and displacement. • A linear behavior between mobility and back bias has been evidenced. • Mobility dependence on temperature remarkably varies with VB for Ω-NWs. Abstract This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (I DS) varying the back gate bias (V B), aiming the extraction of carriers’ mobility of each level separately. The methodology consists of three main steps and accounts for V B influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying V B through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on V B for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of V B and up to 150 °C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels. [ABSTRACT FROM AUTHOR]

• This work presents experimental results of the series resistance variability in junctionless and inversion-mode nanowire transistors. • Due to series resistance, drain-current variability is larger than Y-function variability both in junctionless and inversion mode nanowires. • The influence of source-drain series resistance is higher on drain-current variability for junctionless than inversion mode, presenting an increase of up to 50% depending on the width and channel length. • Results suggest that series resistance variation impacts junctionless more than inversion mode nanowire transistors. This work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors. [ABSTRACT FROM AUTHOR]

Silicon-based solid state plasma antennas were characterized by its wide radiation range, good stealth characteristic, and dynamic reconfigurability, which have broad application prospects in the future. In this paper, investigations of surface PiN diodes developed for silicon-based reconfigurable holographic antennas have been demonstrated for using millimeter-wave communication systems. The SPiN diodes have been extensively discussed, and the obtained results (simulations and experiments) confirm the applicability of these devices for dynamically reconfigurable antennas. A carrier concentration of 10 18 –10 19  cm −3 has been achieved within the optimized SPiN diode. Reconfigurable holographic antennas based on SPiN diodes that were activated by the injection of dc current were demonstrated in this paper. The resonance frequencies at 60 GHz and 64.5 GHz have been easily achieved by turning on or off different sections of the reconfigurable dipole antenna, while the radiation efficiencies were 85.1% and 83.8%, respectively. A double-layer holographic structure was also investigated in this paper. The study reveals that a novel reconfigurable antenna with SPiN diodes has been formed in a single system and has numerous advantages over the traditional antenna. [ABSTRACT FROM AUTHOR]

This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature junctions obtained by Solid Phase Epitaxy Regrowth (SPER). Their electrical behavior is analyzed and compared to reference samples (regular process using High-Temperature junction formation, HT). Dual I D -V DS measurements verify that the TFET structures present Band-to-Band tunnelling (BTBT) carrier injection and not Schottky Barrier tunnelling. P-mode operating LT TFETs deliver an ON state current similar to that of the HT reference, opening the door towards optimized devices operating with very low threshold voltage V TH and low supply voltage V DD . [ABSTRACT FROM AUTHOR]

Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the body potential is probed to evidence the impact of majority carrier accumulation and drain pulse duration on the kink effect onset. [ABSTRACT FROM AUTHOR]

A systematic study to model and characterize the band-modulation Z 2 -FET device is developed bringing light to the relevance of the carrier lifetime influence. This work provides guidelines to optimize the Z 2 -FETs for sharp switching, ESD protection, and 1T-DRAM applications. Lower carrier lifetime in the Z 2 -FET helps in attaining the sharp switch. We provide new insights into the correlation between generation/recombination, diffusion, electrostatic barriers and carrier lifetime. [ABSTRACT FROM AUTHOR]

In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO 2 /Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials. [ABSTRACT FROM AUTHOR]

The aim of this paper is to present the out-of-equilibrium body potential behaviour in the Ψ-MOSFET configuration. Consistent measurements in this experimental setup succeeded in providing a substantial understanding of its characteristics in the depletion region. The final objective of this work is to envision this new measurement technique for biochemical sensor applications. Among its advantages, the most important are its simplicity, the good sensitivity, the measurement of a potential instead of a current and the low bias needed for detection compared to the conventional drain current measurements. [ABSTRACT FROM AUTHOR]

In this paper, a novel SPAD architecture implemented in a Fully-Depleted Silicon-On-Insulator (SOI) CMOS technology is presented. Thanks to its intrinsic vertical 3D structure, the proposed solution is expected to allow further scaling of the pixel size while ensuring high fill factors. Moreover the pixel and the detector electronics can benefit of the well-known advantages brought by SOI technology with respect to bulk CMOS, such as higher speed and lower power consumption. TCAD simulations based on realistic process parameters and dedicated post-processing analysis are carried out in order to optimize and validate the avalanche diode architecture for an optimal electric field distribution in the device but also to extract the main parameters of the SPAD, such as the breakdown voltage, the avalanche triggering probability, the dark count rate and the photon detection probability. A comparison between the efficiency in back-side and front-side approaches is carried out with a particular focus on time-of-flight applications. [ABSTRACT FROM AUTHOR]

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (V BR ) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (V t1 ) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior. [ABSTRACT FROM AUTHOR]

Semiconductor on Insulator (SOI) technology offers an assortment of opportunities for chip manufacturers in the Power Management market. Recent advances in the automotive and industrial markets, along with emerging features, the increasing use of sensors, and the ever-expanding “Internet of Things” (IoT) are providing for continued growth in these markets while also driving more complex solutions. The potential benefits of SOI include the ability to place both high-voltage and low-voltage devices on a single chip, saving space and cost, simplifying designs and models, and improving performance, thereby cutting development costs and improving time to market. SOI also offers novel new approaches to long-standing technologies. [ABSTRACT FROM AUTHOR]

Back-gated InGaAs-on-insulator lateral N + NN + MOSFETs are successfully fabricated by direct wafer bonding and selective epitaxial regrowth. These devices were characterized using a revisited pseudo-MOSFET configuration. Two different transport mechanisms are evidenced: volume conduction in the undepleted region of the film and surface conduction at the interface between InGaAs and buried insulator. We propose extraction techniques for the volume mobility and interface mobility. The impact of film thickness, channel width, and length is evaluated. Additional measurements reveal the variation of the transistor parameters at low temperature and under externally applied uniaxial tensile strain. [ABSTRACT FROM AUTHOR]

• Absence of asymmetry in the noise characteristics of GAA VNW pFETs on SOI substrates. • A clear impact of the nanowire p-type doping density on the noise Power Spectral Density and on the 1/f noise mechanism. • Optimal 1/f noise performance for an intermediate boron doping density around 5 × 1018 cm−3. In this work, the impact of the channel doping density on the low-frequency noise of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) pMOSFETs on Silicon-on-Insulator (SOI) substrates will be described and discussed. It is demonstrated that the dominant fluctuation mechanism of the 1/f noise in the subthreshold regime changes from number (Δn) to mobility (Δμ) fluctuations with increasing p-type doping density of the silicon nanowires. At the same time, the lowest input-referred voltage noise Power Spectral Density is observed for an intermediate boron concentration in the nanowire of 5 × 1018 cm−3. [ABSTRACT FROM AUTHOR]

Three dimensional (3-D) FinFET devices with an ultra-high Si-fin aspect ratio (Height/Width = 82.9 nm/8.6 nm) have been developed after integrating a 14 Å nitrided gate oxide upon the silicon on insulator (SOI) wafers through an advanced CMOS logic platform. The drive current (I ON ), off current (I OFF ), subthreshold swing (SS), drain-induced barrier lowering (DIBL) and transistor gate delay of 30 nm gate length (L g ) of FinFETs illustrate the promising device performance. The TCAD simulations demonstrate that both threshold voltage (V th ) and off current can be adjusted appropriately through the full silicidation (FUSI) of CoSi 2 gate engineering. Moreover, the drive currents of n- and p-channel FinFETs are able to be further enhanced once applying the raised Source/Drain (S/D) approach technology for reducing the S/D resistance drastically. [ABSTRACT FROM AUTHOR]

Low-frequency noise (LFN) measurements are largely used for interface quality characterization in MOSFETs. In this work, a detailed investigation of LFN technique applied to pseudo-MOSFETs in bare silicon-on-insulator (SOI) substrates is provided. A physical model capable to describe the experimental results is proposed and validated using different die areas and inter-probe distances. The effective silicon area contributing to the noise signal, the impact of defects induced by probes and the possibility to extract interface trap density are addressed. [ABSTRACT FROM AUTHOR]

The characterization of nanosize SOI materials and devices is challenging because multiple oxides, interfaces and channels coexist. Conventional measurement methods need to be replaced, or at least updated. We review the routine techniques that proved efficient for the evaluation of bare SOI wafers (essentially the pseudo-MOSFET) and of MOS structures (transistors and gated diodes). Informative examples are selected to illustrate the typical properties of advanced SOI wafers and MOSFETs. We will show how the ultrathin film and short-channel effects affect the interpretation of the experimental data. [ABSTRACT FROM AUTHOR]

We propose and demonstrate experimentally a band-modulation device with extremely sharp switching capability. The Z 3 -FET (Zero gate, Zero swing and Zero impact ionization) has no top gate, is processed with FDSOI CMOS technology, and makes use of two adjacent buried ground planes acting as back gates. The buried gates emulate respectively N + and P + regions in the undoped body, forming a virtual thyristor-like NPNP structure with feedback operation. Vertical output I A – V A and transfer I A – V G characteristics over more than 8 decades of current are measured with relatively low gate and drain bias (<3 V). [ABSTRACT FROM AUTHOR]

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high- k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS. [ABSTRACT FROM AUTHOR]

We report the fabrication and the characterization of tunnel FETs fabricated on SiGe-On-Insulator with a High-κ Metal Gate (HKMG) CMOS process. The beneficial impact of low band gap SiGe channel on I D ( V G ) characteristics is presented and analyzed: compressive Si 0.75 Ge 0.25 enables to increase by a factor of 25 the saturation currents, even at small gate length ( L G = 50 nm). This large gain is due to the threshold voltage shift and to enhanced intrinsic band-to-band tunneling injection (both related to the narrow band gap of SiGe channels). [ABSTRACT FROM AUTHOR]

• Silicon nitride was used as resistive switching in a MIS memristor structure on heavily doped SOI substrates. • The active electrode was Cu allowing for Top electrode. • AC impedance and current-voltage sweep measurements revealed higher series on SOI compared to bulk Si substrate. • Low-frequency noise measurements at low resistance state revealed the silicon nitride traps as main noise source. • Devices on SOI exhibited self-compliance characteristics as revealed by I - V sweeps and AC impedance measurements. Several resistive memory technologies (RRAMs) are prominent, but few are fulfilling the requirements for CMOS integration and meet the commercialization standards. In this work, the fabrication and electrical characterization of a fully compatible CMOS process on SOI substrate of 1R silicon SiN-based resistance switching (RS) MIS devices is presented. The RS characteristics are compared with the same devices previously fabricated on bulk silicon. [ABSTRACT FROM AUTHOR]

• Study performed through 3D numerical simulations validated with experimental data. • Analysis of the coupling effects in current mirrors composed by UTBB as follows: • Capacitive coupling in V TH of the input device operating alone at reduced distances. • At small S, the temperature rise due to thermal coupling leads an I D2 /I D1 increase. • Stronger effect observed in shorter device positioned at the channel width direction. This work performs an analysis of the cross-coupling effects influence on the performance of current mirrors composed by advanced UTBB SOI MOSFETs through 3D numerical simulations validated to experimental data of single devices. It is shown the presence of a capacitive coupling acting in the system, which can be demonstrated through the threshold voltage reduction at small distances between devices. Additionally, the temperature rise in the system due to the thermal coupling provokes a decrease in the input current as the devices become closer to each other. This is responsible for an increase of 3 % on I D2 /I D1 ratio when the devices are biased at the same time and when the distance between them is lowered to 100 nm. [ABSTRACT FROM AUTHOR]

The aim of this study is to analyse the excess low frequency noise from 100 K up to room temperature in p-channel triple-gate standard and strained FinFET transistors fabricated on silicon on insulator (SOI) substrates. The low frequency noise measurements as a function of temperature can be successfully used as a non-destructive device characterisation tool in order to evaluate the quality of the silicon film and to identify traps induced during the device processing. Several identified traps which can be related to boron and carbon, in particular for strained substrate devices, were observed. [ABSTRACT FROM AUTHOR]

This work aims to analyze the impact of the Ground Plane (GP) on a new generation of the dynamic threshold (DT2) operation in Ultra-thin Body and Buried Oxide (UTBB) SOI nMOSFETs. The DT2, using a short-circuit between the gate and the substrate contact, the enhanced dynamic threshold (eDT), where the substrate bias is a multiple value of the gate bias ( V B = k × V G , k = 1,2,…,5), and the inverse eDT (with V G = k × V B ) were compared to the conventional mode with grounded substrate. Although the improvement of the DT2 mode observed for devices with GP is lower, they presented lower short channel effects, mainly for shorter channel lengths. Regarding the direct and inverse eDT modes, a stronger dynamic threshold (DT) effect on devices with GP also results in better DC parameters such as lower subthreshold swing and higher maximum transconductance. [ABSTRACT FROM AUTHOR]

The scaling of MOSFET transistors makes the use of new device geometries, such as multigate FETs, a need to solve the limitations of the conventional bulk technology. In this context we introduce an analytical model for square Gate All Around (GAA) MOSFETs with rounded corners including quantum effects. The modeling of rounded corners in GAA and FinFET devices is imperative because there are no perfectly square corners in the cross-section of real devices. In this model the 2D inversion charge distribution function (ICDF) is described analytically for devices of different sizes and for different operation regimes. The model reproduces accurately simulated data obtained with a state-of-the-art simulator that solves self-consistently the Poisson and Schrödinger equations in the devices under consideration. The analytical ICDF is used to better understand the device physics and to calculate the inversion charge centroid and the gate-to-channel capacitance for different device geometries and biases for modeling purposes. [ABSTRACT FROM AUTHOR]

In this work, a compact model for short-channel effects is proposed for fully depleted silicon-on-insulator (FDSOI) MOSFETs, which takes into account the impact of body-bias and fringing fields, developed to be suitable for both thin and thick buried oxide (BOX) devices. The model is derived using the Voltage-Doping Transform, confirmed with TCAD simulations and experimental data from the literature. The impact of the BOX thickness on the subthreshold swing and the contribution of the leakiest path position to the DIBL are finally discussed. [ABSTRACT FROM AUTHOR]

The feasibility of full split C-V method in ultra-thin body and BOX (UTBB) FDSOI devices is demonstrated, emphasizing the usefulness of gate-to-bulk capacitance. The split C-V measurements carried out on both gate-to-channel and gate-to-bulk mode are shown to be consistent with TCAD simulation. This enabled us to propose an improved parameter extraction methodology for the whole vertical FDSOI stack from gate to substrate using back biasing effect. [ABSTRACT FROM AUTHOR]

Abstract: We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N2 pixels or test sites) and 8 input–output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases. [Copyright &y& Elsevier]

Abstract: A dual-gate (DG) ion sensitive field effect transistor (ISFET) using capacitance coupling effect has recently been proposed to overcome the Nernst limitation as 59mV/pH. In this study, we focus on the analysis of sensing characteristics by various oxide capacitances and channel thickness using intensive measurement on conventional fully depleted (FD) silicon-on-insulator (SOI) based DG ISFET. The enlarged oxide capacitance and reductive channel thickness enhance the capacitive coupling effect and increase sensitivity of DG ISFET. And also, the thin channel thickness reduced the leakage current in the DG operation. These will be very promising techniques for high performance biosensor application. [Copyright &y& Elsevier]

Abstract: Vertical double-gate (DG) FinFETs fabricated on SOI wafers show good gate control, reasonable threshold voltage and high carrier mobility despite the absence of the top-gate. The 3D coupling effect between the two lateral-gates and the back-gate is investigated based on experimental and simulation results. We compare DG and triple-gate FinFETs with various fin widths. Front-channel characteristics are easily tuned by applied bias at the back-gate if the fin is not too narrow. We highlight that vertical DG FinFET is more appropriate device for dynamic threshold voltage adjustment than triple-gate FinFET. An analytical model is proposed to quantify the coupling effect in DG FinFET by solving 2D Poisson equation. The body potential profile and coupling effect are modeled. A very good agreement is obtained between experiments, 3D simulations and the proposed model. [Copyright &y& Elsevier]

Abstract: 300mm ultrathin Silicon-On-Insulator (SOI) wafers with SiGe/Si stacks on top were used as pre-structures for the fabrication of 5nm thick SiGe-On-Insulator (SGOI) substrates obtained by the Ge enrichment technique. Those substrates will be used as the channel of advanced Fully Depleted (FD) p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFET). We present in the first part the successful fabrication of 5nm SGOI wafers. Various characterization techniques are used to investigate the Ge profile and the final strain in the fabricated 5nm Si0.7Ge0.3 film. Secondary Ions Mass Spectrometry (SIMS) and Scanning Transmission Electron Microscopy (STEM) clearly show that the Ge content is very homogeneous (x Ge =30±1%) in the SiGe layer. Raman spectroscopy and High Angle Annular Dark Field (HAADF) STEM both confirm that the 5nm thick SiGe film is compressively strained (−2GPa). The second part is dedicated to the sensitivity of the Ge enrichment process (based on numerical modelling). We investigate the impact of single and combined fluctuations of the pre-structure parameters (T Si, T SiGe,0, x Ge,0) on the final SiGe layer (T SiGe, x Ge). [Copyright &y& Elsevier]

Highlights: [•] RF losses and crosstalk were studied for 6H-SiC, poly-SiC and silicon substrates. [•] SiC substrates behave semi-insulating with low losses and no temperature dependence. [•] Losses, crosstalk and temperature behavior in silicon depend strongly on resistivity. [•] Poly-SiC shows complex high frequency behavior. [•] Poly-SiC can replace 6H-SiC in Si/SiC hybrid substrates without performance loss. [Copyright &y& Elsevier]

Abstract: This paper investigates the front and back gate bias influence on current sense margin and retention time in Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices used as a FBRAM (floating body random access memory) cell through simulations and experimental results. This work aims to gain insight into the mechanisms involved into FBRAM operation and optimize the front and back gate biases for achieving the best retention time and current sense margin. The writing ‘1’, through BJT effect, and writing ‘0’, by using capacitive coupling, were verified. We demonstrated that, during the holding, the operation mode of the interfaces is an important factor for the best condition for achieving both a higher current sense margin and a longer retention time, which should be with the front gate in accumulation mode and the back gate in depletion mode. It was also observed that depending on gate bias applied during the hold operation, there are two mechanisms involved in retention time. For less negative gate voltage the retention time is limited by recombination, whereas for more negative gate voltage the generation mechanisms take place. Moreover, the retention time showed more sensitivity to the back gate voltage than the current sense margin. [Copyright &y& Elsevier]

Abstract: A low-field mobility model for square GAA MOSFETs has been developed. The model is analytical and explicit, so it can be used in device simulators and, most importantly, in compact models of these Multi-gate devices for circuit simulation purposes. We have made use of a simulator that includes quantum effects to characterize the electron mobility of square GAA MOSFETs with different sizes for the usual gate voltages and operation regimes. The dependencies with the silicon core lateral size, the inversion charge and the surface roughness are included. The phonon, surface roughness and Coulomb mobility components are modeled separately by means of the Matthiessen rule. Finally, we have performed a comparison between our model and experimental results for validation purposes. We find that the experimental results are well reproduced by our model. [Copyright &y& Elsevier]

Abstract: This paper presents a systematic study of a sharp-switching device built in fully-depleted silicon-on-insulator (FD-SOI) that we have called Z2-FET, as it features zero subthreshold swing (<1mV/decade of current) and zero impact ionization. The Z2-FET is a compact device with a single front gate that experimentally demonstrates a current I ON/I OFF ratio >108 at low supply voltage, as well as gate-controlled hysteresis. The operating principle of the sharp switching involves the positive feedback between carrier flow and gate-controlled injection barriers, as confirmed by TCAD simulations. We discuss the impact of bias and device dimensions on the experimental performance and simulate the Z2-FET’s ultimate scaling capability to <50nm channel length. We present a simplified compact model of the Z2-FET. With good reliability and relative insusceptibility to temperature variation, the envisioned applications of the Z2-FET include compact, high-speed one transistor DRAM (1T-DRAM), one-transistor SRAM, fast logic and electrostatic discharge (ESD) protection circuits. [Copyright &y& Elsevier]

Highlights: [•] Impact of UTBOX with GP and local Vb on bitcells performance improvement. [•] The V T variation increases when opposite GP doping is used for NMOS and PMOS. [•] As the BOX thickness is reduced this V T variation versus Vb increases. [•] Back bias improve bitcells performance in FBB and RBB as in bulk. [•] For gated and STI diodes, hybrid technology improves TLP at the same level as bulk. [ABSTRACT FROM AUTHOR]

Highlights: [•] This paper presents a pragmatic device design methodology for bulk FinFET. [•] The pragmatic design could be controlled by isolation oxide and substrate doping levels. [•] The design methodology can be applied to low power and high speed applications within a design window. [Copyright &y& Elsevier]

Abstract: Charge pumping (ACIV) and direct current–voltage (DCIV) measurements were performed on standard floating-body n-channel FinFETs. The resulting recombination currents are monitored directly at the drain and source contacts, and are found to depend strongly on frequency, gate voltage, and FinFET geometry. The DCIV current reaches a maximum when the body potential transitions from accumulation to inversion in response to the applied gate bias and the body-to-source and body-to-drain diodes become forward biased. The ACIV current is dominated by contributions from interface traps when the surface potential is swept from accumulation to inversion during the gate pulse. It is sensitive to recombination currents at the body-to-source and body-to-drain diodes at intermediate voltage levels. At the highest applied gate voltages, band-to-band tunneling is also observed. We demonstrate that the change in ACIV current with frequency before and after electrical stress allows charge-pumping estimates of stress-induced interface trap densities in standard SOI FinFETs without body contacts. [Copyright &y& Elsevier]

Abstract: Advanced FinFETs fabricated on alternative SOI substrate with SiO2–Si3N4–SiO2 (ONO) buried insulator are investigated for flash memory applications. The Si3N4 buried layer can easily trap charges by applying high back-gate or reasonable drain bias. The shift of the drain current, flowing at front-gate interface and resulting from interface coupling, indicates the amount of trapped/detrapped charges in the buried nitride layer. The memory effect, which is defined as the difference of drain current level, is induced by trapped/detrapped charges. The trapped charges in the buried dielectric also induce a drain current hysteresis when the back-gate bias is dynamically scanned. Systematic measurements reveal that the memory effect depends on the bias conditions and geometrical parameters. [Copyright &y& Elsevier]

Abstract: In this paper, the low frequency noise was studied from 100K up to room temperature in n-channel triple-gate FinFET transistors fabricated on silicon on insulator (SOI) substrates. It was found that the noise spectra contain 1/f and Lorentzian components, which can be analyzed using the standpoint of the number fluctuation by generation–recombination of carriers due to traps that can be located either at the gate oxide/Si film interface or in the silicon depletion film. The variations of the low frequency noise versus temperature allow to evaluate the quality of the gate oxide interface, to identify traps in the silicon film and to make a correlation between the observed traps and some technological steps. Moreover, some additional process steps used to boost the device performances seem to increase the trap densities in the film with no significant impact at the gate oxide/Si film interface. [Copyright &y& Elsevier]

Abstract: This paper reports the function of the parasitic bipolar device in the 40nm PD SOI NMOS device with the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during DC and transient operations could be modelled. During the turn-on transient by imposing a step voltage from 0V to 2V on the gate, the case with the a slower rise time shows a relatively faster turn-on in the drain current due to a stronger function of the parasitic bipolar device from smaller displacement currents through the gate oxide, as reflected in the current gain, as verified by the experimentally measured result. [Copyright &y& Elsevier]

Abstract: SOI enables reduced capacitive coupling in RF power technology but the thick oxide causes thermal problems. In this paper, the authors present a new type of substrate, where the oxide insulator and the silicon substrate in SOI, are replaced by silicon carbide (SiC). SiC has higher thermal conductivity and is semi-insulating which can improve the thermal and RF performance. Here, LDMOS-transistors are processed and characterized on 150mm silicon-on-polycrystalline-silicon carbide (Si-on-poly-SiC) substrates as well as on high power and RF optimized SOI reference substrates. The electrical performance for the Si-on-poly-SiC was improved or equal compared to the SOI reference and the device self-heating was reduced. The hybrid substrate had lower RF losses and the RF measurements on transistors were not ideal due to no isolation between the devices. [Copyright &y& Elsevier]

Abstract: We demonstrate a new fully depleted (FD) double-gate (DG) MSDRAM cell, which features SONOS type storage node at the back-gate (control-gate). This single-transistor cell, based on the meta-stable dip (MSD) hysteresis effect, can also be operated in non-volatile memory (NVM) mode. The NVM functionality is achieved by Fowler–Nordheim tunneling hole injection into the nitride storage node; the injected holes induce a permanent inversion layer in silicon body. The proposed device shows a large current ratio between ‘1’ and ‘0’ states (∼103) and a wide memory window (∼3V). The effect of the NVM functionality on the MSD hysteresis was investigated and combined with the effect of the control-gate bias. The SONOS charging can be used for replacing the second gate (i.e. enabling single-gate MSDRAM) or for achieving ‘unified’ memory operation. [Copyright &y& Elsevier]

Abstract: In this work, a model is developed in order to obtain analytical expressions of the subthreshold characteristics of advanced Pi-gate FET transistors. Based on the solution of the 3D Laplace’s equation, the interface coupling in the structure is accurately described and the potential calculated. Using the ‘most leaky path’ approach, the potential is then integrated and expressed as a simplified formula for the subthreshold current of Pi-gate FET transistors. The short-channel characteristics (subthreshold current, subthreshold slope, Roll-off and DIBL) are calculated and compared to experimental data with an excellent agreement, without the need of any fitting parameters. Additionally, it is shown that the proposed analytical equation for the 3D subthreshold current can be extended to a wide range of Multiple-gate FET transistors in order to study their scalability. Finally, a pseudo-compact subthreshold slope formula is proposed in order to provide simplified scaling-oriented guidelines. [Copyright &y& Elsevier]