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• Fabrication of ISFETs. • Experimental analysis of ISFET for potassium chloride (KCl) sensing. • Sensitivity analysis for measurement methods, with one and two platinum electrodes. This work presents the fabrication and electrical characterization of the Ion Sensitive Field Effect Transistor (ISFET) exposed to potassium chloride (KCl) solutions. The focus of the study is to compare two measurements methods and verify the effects of these methods in the device threshold voltage (V TH) sensitivity to the different KCl concentrations. First, a reference electrode (a platinum needle) is placed in the sample solution over the gate area of the device, demonstrating that the threshold voltage decreases with the increase of the KCl concentration. The method shows a sensitivity of 10.44 mV/mM for the low KCl concentration range (0 to 10 mM) and 0.5 mV/mM for the higher KCl concentration range (10 to 100 mM). The second method involves inserting a second platinum electrode into the solution on the field oxide. This method proposes the KCl electrolysis to increase the selectivity for potassium ions. The result allows the next steps for potassium sensing biosensor application with selective membranes. [ABSTRACT FROM AUTHOR]

• Systematic evaluation of threshold voltage extraction methods in FD-SOI MOSFET. The threshold voltage definition and measurement in ultrathin FD-SOI MOS transistors are revisited by comparing theoretical and pragmatic extraction techniques, including novel approaches. The respective merits and limitations of methods based on the monitoring of the potential, mobile charge, gate-to-channel capacitance and drain current are emphasized. Back-gate biasing, thickness-induced quantization, potential fluctuations and surface roughness can enhance the disparity between various extraction methods. The origin of these deviations is clarified. [ABSTRACT FROM AUTHOR]

• The current of RBDT could rise increase exponentially; while the current of SiC MOSFET could be saturated. • The transient characteristics of RBDT includes a voltage-controlled inductance, while the SiC MOSFET contain a current-controlled inductance. • The equivalents inductance of Si RBDT decreases and tends to be saturated when the main voltage is higher than half of the breakdown voltage of Si RBDT. • For SiC MOSFET, the equivalent inductance increases until the drain current reaches the saturated value for a given gate voltage. With the development of pulse power supplies, solid-state semiconductor switches are required to have fast switching speeds and low losses. Both Reverse blocking diode thyristor (RBDT) and silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) have fast turn-on speed, making them suitable candidates for short pulse generator. In this paper, the transient turn-on characteristics of Si RBDT and SiC MOSFET are analyzed theoretically and validated experimentally. Si RBDT and commercial 1.2 kV/81A SiC MOSFET are comparatively investigated in switching current pulse with a rise time of several hundreds of nanoseconds. (1) The anode current of RBDT could rise exponentially because of the latch-up effect of Si RBDT, while the drain current of SiC MOSFET tends to be saturated. (2) Utilizing the current rise time (T rise) to represent the switching speed, SiC MOSFET can switch faster when the current is lower than 400A. With the increase of the current, Si RBDT presents faster turn-on speed and lower switching loss due to the regenerative action of the two coupled transistors. (3) The transient characteristics of Si RBDT include a voltage-controlled inductance, while SiC MOSFET contains a current-controlled inductance based on the current rise time, respectively. With the increasing of the main voltage, the equivalent inductance of Si RBDT decreases and tends to be saturated when the main voltage is higher than half of the breakdown voltage of Si RBDT. For SiC MOSFET, the equivalent inductance increases until the drain current remains stable for a given gate voltage. This paper confirms the advantages of Si RBDT and SiC MOSFET in different situations. [ABSTRACT FROM AUTHOR]

The junctionless EZ-FET is a simple FDSOI-like device that requires only two lithography levels and standard processing steps. With its simplified architecture and fabrication flow, and using undoped source and drain terminals, the device allows for a fast electrical evaluation of semiconductor films on insulators (SOI) and gate stacks. This paper describes an electrical model that reproduces the peculiar transfer characteristics of a junctionless EZ-FET. The model is then simplified to develop a pragmatic parameter extraction methodology. This methodology is experimentally validated and provides the electrical properties of SOI films (mobility, threshold voltage) for both electrons and holes. [ABSTRACT FROM AUTHOR]

• A novel method to determine bias-dependent source and drain parasitic series resistances in AlGaN/GaN high electron mobility transistors has been proposed. • The physical mechanism that causes R s and R d to vary with bias voltage is studied. • The bias voltage can affect the magnitude of R s and R d by affecting the optical phonon temperature and the intensity of the inverse piezoelectric effect. The AlGaN/GaN high electron mobility transistors (HEMTs) with T-gate that suitable for high frequency applications were fabricated. A novel method to extract the bias-dependent source and drain parasitic series resistances (R s and R d) of AlGaN/GaN HEMTs is proposed. By analyzing the distributed capacitance and current generator network in the velocity saturated regions of the AlGaN/GaN HEMTs, a new restriction relationship between small-signal equivalent circuit elements is found. The R s and R d can be determined under active bias through wideband S-parameter measurements, which can better reflect the physical mechanism of AlGaN/GaN HEMTs under normal operation. The S-parameters and extrinsic transconductance calculated based the small-signal equivalent circuit element values extracted by the method proposed in this paper are very consistent with the experimental values, which reflects the accuracy of this element extraction method. In this paper, the physical mechanism that causes R s and R d to vary with bias voltage is also studied. This study has a deeper insight into the bias-dependence of R s and R d , which modifies the understanding for physical mechanisms of AlGaN/GaN HEMTs. The research results provide new ideas for establishing small-signal equivalent circuit models containing more physical effects and is of great significance to GaN-based integrated circuit design. [ABSTRACT FROM AUTHOR]

• Normally-off GaN MOSFET is successfully demonstrated by using the selective regrowth of AlGaN layer on source/drain (S/D) regions. • Wide regrown AlGaN layer is applied to GaN MOSFET to accommodate the poor structural quality of narrow regrown AlGaN on the S/D regions. • The proposed device with wide regrown AlGaN S/D has the potential to serve as a robust and uniform normally-off GaN MOSFET. A normally-off GaN MOSFET is successfully fabricated by using the selective regrowth technique (SRT) with regrown AlGaN layer on source/drain (S/D) region. The GaN MOSFET with regrown AlGaN layer and L g of 10 μm shows enhanced electrical performance such as maximum drain current (I D,max) of 57 mA/mm, maximum transconductance (g m,max) of 11 mS/mm, and field-effect mobility (μ FE) of 59 cm2/V·s, respectively, compared to the GaN MOSFET with n+-GaN selective regrowth in S/D region. This is because of the high 2DEG density formed by AlGaN/GaN heterojunction in S/D region. Moreover, to accommodate the poor structural quality of the narrow region regrowth of AlGaN layer on the S/D region, wide regrown AlGaN layer is applied to the GaN MOSFET. Especially, the off-state breakdown voltage improves from 25 V to 192 V with the improved structural quality of wide regrown AlGaN layer and optimized structure and the application of the 70-nm thick SiO 2 passivation. These result shows that GaN MOSFET with wide regrown AlGaN layer on S/D region is beneficial to achieving high-quality and uniform normally-off GaN MOSFETs with excellent electrical performance. [ABSTRACT FROM AUTHOR]

• The device is most susceptible to degradation in the semi-on state. • Voltage is the main driving factor for device degradation. • The electrical pulse stress causes more severe device degradation than DC stress. • Channel high-energy hot electron injection, exacerbating device degradation. The large numbers of high-energy carriers that occur in semiconductor devices under semi-on state conditions can cause significant device degradation. The effects of different stresses on the electrical and trapping characteristics of GaN-based high-electron-mobility transistors (HEMTs) are investigated. Test results for GaN HEMTs under semi-on state conditions show that the electrical characteristics of these devices degrade to a certain extent after they are subjected to electrical pulse stress cycles with different drain voltage, frequencies, and duty cycles; a degree of degradation also occurs in the electrical characteristics of the devices when they are subjected to direct current electrical stresses. After electrical stress is applied, the absolute amplitude of the traps in the device increases, thus indicating an increase in the trap density. The results show that voltage is the main driver for device damage, with the current playing an accelerating role through its effects on device temperature or by supplying hot electrons; therefore, the drain voltage has the most significant effect on device degradation, which is mainly due to channel high-energy hot electron injection. [ABSTRACT FROM AUTHOR]

• Establishment of a precise physical foundation for the negative capacitance effect, unveiling its direct connection with the free energy profile of HZO. • Demonstration of the origin of negative capacitance effect in multidomain M/HZO/M gate stack, attributing it to varying switching rates between free charge and polarization, primarily influenced by the negative capacitance region within HZO's free energy profile. • Prediction of the HZO's intrinsic switching speed for various experimentally extracted damping factorsof the HZO material, offering versatile control over device performance. • Investigation into the direct causes of the negative drain-induced barrier lowering effect and the negative differential resistance effect in Landau NCFETs. • Engineered Leaky-HZO to fix the leakage problem in NCFET design. • Development of a circuit-compatible hybrid compact model for leakage-aware negative capacitance circuit simulations, facilitating practical integration into negative capacitance electronics. This paper addresses the lack of understanding of the origin of negative capacitance (NC) effect in the hafnium zirconium oxide (HZO) ferroelectric (FE) gate stack and proposes a new circuit-compatible hybrid compact model for NC field-effect transistors (NCFETs). The model supports Landau and Preisach FE models, encompassing multiple FE domains, FE leakage, and FE damping. The proposed model is experimentally validated, and the intrinsic switching speed of HZO is predicted. It is revealed that the NC effect in HZO stems from a mismatch in free charge and polarization switching rates. Performance evaluation of the model reveals that HZO-NCFET achieves ∼1.18x and ∼9.17x higher amplification at low and high frequencies compared to its PZT-NCFET counterpart. Our study demonstrates the superior ON-current (2.74 mA/µm) of the Engineered Leaky-HZO NCFET, surpassing FinFET and Germanium-source L-shaped TFET by ∼7.89x and ∼4.81x, respectively. This study briefly examines the direct causes of the negative drain-induced barrier lowering effect and negative differential resistance effect in Landau NCFETs. Furthermore, we emphasize the crucial role of FE thickness in determining the magnitude of the NC effect, offering valuable insights for the design and optimization of NC-based devices and circuits. Analysis of the Miller effect in NCFET-based inverters demonstrates significant improvements owing to high ON-current and voltage amplification, making them suitable for high-speed NCFET-based circuitry. Landau and Preisach NCFET-based inverters exhibit (50.70%, 51.34%) lower overshoots and (28.45%, 28.61%) reduced propagation delay compared to the NC nanowire FET-based inverter. Moreover, NCFET-based 2:1 fork circuits significantly reduce (46.69%, 51.37%) critical clock skew compared to CMOS FET-based circuits, showcasing the potential of NCFET technology in addressing timing violations in random logic paths. Furthermore, the Landau and Preisach NCFET-based ring oscillators (ROs) achieve (39.97%, 49.38%) and (52.65%, 62.92%) higher oscillation frequencies (f OSC) compared to state-of-the-art graphene FET-RO and CMOS-RO, respectively. The 15-stage Leaky-HZO and Engineered Leaky-HZO NCFET-ROs outperform the double gate-FET-RO by ∼2.19x and ∼16.69x in terms of f OSC , highlighting their superior performance in frequency-domain metrics. These findings demonstrate the potential of NCFET-based digital and mixed-signal circuits for high-performance integrated circuit designs. [ABSTRACT FROM AUTHOR]

• Study examines field plate configurations' impact on GaN MIS-HEMT breakdown voltage. • The study stresses composite field plates(e.g. gate with source and drain) to maximize breakdown voltage. • The device performance is further enhanced by using a stacked field plate configuration. • Study explores high-k dielectric passivation effects with field plate configuration on device breakdown voltage. The effects of different field plate designs on the breakdown voltage of GaN Metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) were examined in this study. The study's primary goal was to determine the dependence of breakdown voltage with respective to composite field plate designs using TCAD simulation. For devices featuring only G-FP, with a fixed gate to drain distance of 15 μm and a fixed G-FP to drain distance of 15 μm, the maximum breakdown voltage was achieved 1 μm G-FP. Breakdown voltage trends were also determined for composite field plate configurations, such as adding a source field plate (S-FP) or a drain field plate (D-FP) with a fixed 1 μm G-FP length. A further enhancement in device breakdown performance was demonstrated by employing a novel D-FP structure. A single D-FP improves the breakdown voltage from 1.4 kV (conventional breakdown voltage with 1um G-FP) to 1.6 kV when combined with 1 μm G-FP, while the novel two-step D-FP achieves a breakdown voltage of about 1.7 kV when combined with 1 μm G-FP. We also investigated the influence of high-k dielectric passivation layers on the breakdown voltage. The breakdown voltage of the devices with optimized G-FP can be further improved by using high-k dielectric material as a passivation layer. The thorough investigations contribute to a better understanding of GaN MIS-HEMT breakdown characteristics and prospective pathways for improving their performance via unique field plate designs and superior dielectric materials. [ABSTRACT FROM AUTHOR]

• Bias scheme for FeFET based AND array was secured by using a single FeFET. • Experiments verified that single FeFET based bias scheme is valid for an array. • Experimentally showed that writing can be inhibited by adjusting only bias in BL. In this study, we experimentally demonstrated a simplified write inhibition bias scheme for a ferroelectric field-effect transistor (FeFET) based AND array, which is the promising energy- and area-efficient memory. The write inhibition scheme that only employs the bit line (BL) voltages was optimized through the single cell FeFET measurements. The program and erase operations were confirmed to be apparently inhibited with the BL/source line (SL) voltages of 3.5 V/0 V, respectively. The suggested inhibition bias scheme was then applied to the 16 × 16 FeFET AND array for demonstrating its validity. It was clearly verified that selective program/erase operations were possible without modulating the SL voltages, suggesting its benefits in terms of area-efficiency. [ABSTRACT FROM AUTHOR]

• A single neural network parameter extractor for BSIM-CMG IV and CV model is developed. • A global I-V and C-V parameter extraction for a large range of gate length is achieved. • A high fitting accuracy is demonstrated on TCAD simulated data calibrated to 10 nm node. A global I-V and C-V BSIM-CMG parameter extraction methodology based on deep learning is proposed. 100 k training datasets were generated through Monte Carlo simulation varying 28 IV and CV model parameters in the industry-standard BSIM-CMG FinFET model. For each of the 100 k Monte Carlo-selected BSIM-CMG parameter dataset, the I D -V G and C GG -V G characteristics of seven Monte Carlo-selected gate lengths ranging from 14 nm to 110 nm were generated as the input to train the parameter extraction neural network. The neural network outputs for training are the 28 model parameters' values. The neural network's capability to extract BSIM-CMG model parameters that accurately fit TCAD-generated I D -V G and C GG -V G data over a range of gate lengths was demonstrated. This marks the first time a deep learning compact model parameter extraction flow, employing a single neural network for both I-V and C-V parameters and for a range of gate length, is presented. [ABSTRACT FROM AUTHOR]

• β-Ga 2 O 3 FinFET. • Low-Frequency Noise. • Spatial Distribution of Trap States. • Positive-Bias Stress. The reliability of a β -Ga 2 O 3 thin-film field-effect transistor is investigated under positive-bias stress (PBS). The transistor has a tri-gate structure with a gate dielectric of Al 2 O 3. By characterizing low-frequency noise (LFN), the spatial distribution of trap in the gate dielectric was quantitatively extracted. The measured power spectral density (PSD) followed a 1/f-shape due to trapping and de-trapping of the channel carriers to and from the gate dielectric. Notably, the vertical distribution of the traps perpendicular to the interface of β -Ga 2 O 3 and Al 2 O 3 was mapped [ABSTRACT FROM AUTHOR]

• The mechanism of negative bias instability in commercial silicon carbide Metal-Oxide-Semiconductor Field-Effect Transistors has been explained through the analysis of transient gate currents. • Experimental results demonstrate that near-interface traps with energy levels aligned to the valence band trap holes from the valence band by tunneling. • The transients in the gate current correspond to the trapping of holes by the near-interface traps. • The study demonstrates the impact of the aluminum implantation process on the p-type region, highlighting its role in hole trapping. This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results reveal that near-interface traps (NITs) with energy levels aligned to the valence band trap holes from the valence band by tunneling, which is different from published results about NITs with energy levels aligned to the energy gap. The impact of the aluminium implantation process of the p-type region on hole trapping is also demonstrated. The presented analysis also reveals that the hole trapping by NITs is limited to the p-type region, indicating that the aluminium implantation process is responsible for the detected NITs. [ABSTRACT FROM AUTHOR]

• Effects of gate-source/drain overlap on FeFETs are investigated. • Threshold voltage and polarization under various overlap conditions are analyzed. • MFMIS FeFET features superior memory performance with gate-source/drain overlap compared to the MFIS FeFET. The influences of gate-source/drain overlap on ferroelectric field-effect transistors (FeFETs) are investigated with various gate-source/drain overlap lengths (L ov 's) and doping concentrations of the gate-source/drain overlap region (D ov 's). In contrast to conventional metal-ferroelectric-insulator-semiconductor (MFIS) FeFETs, a metal layer between a ferroelectric and an insulator layer allows overlap capacitance to affect the entire ferroelectric layer in metal-ferroelectric-metal–insulator-semiconductor (MFMIS) FeFETs. As L ov and D ov increase, the effective channel length of both FeFETs decreases. In the case of MFMIS FeFETs, the gate-to-source/drain overlap capacitance (C ov,gate-S/D) increases, leading to a larger voltage drop across the ferroelectric layer. According to the simulation results, MFMIS FeFETs show a wider memory window (MW) and larger sensing margin than MFIS FeFETs. [ABSTRACT FROM AUTHOR]

• The forming gas (FG) annealing results in a significantly reduction of surface native oxide whereby the amount of Ga–O bonds is decreased demonstrated by the X-ray photoelectron spectra. Hydrogen atoms in H 2 can react with oxygen atoms in the native oxide layer and remove the oxygen to form a surface with oxygen vacancies. Nitrogen molecules in FG can provide nitrogen atoms to fill up these vacancies. Consequently, the removed native oxide layer during FG annealing leads to the formation of a new nitridation layer on the surface. • Compared with N 2 annealing, an on-resistance of 1.68 Ω·mm, a subthreshold swing of 118 mV/dec, a transconductance peak of 513 mS/mm, a gate diode breakdown voltage of surpassing 42 V, and a high current/power gain cutoff frequency (f T / f max) of 165/165 GHz are achieved by the 50-nm InAlN/GaN HEMT annealing by FG H 2 /N 2 on Si substrate. The surface electronic states and defects of gallium nitride based high-electron-mobility transistors (HEMTs) play a critical role affecting channel electron density, electron mobility, leakage current, radio frequency (RF) power output and power added efficiency of devices. This article demonstrates the improved surface properties of InAlN/GaN HEMTs through forming gas (FG) annealing, resulting in a significantly improved electrical properties. The X-ray photoelectron spectra reveals a reduction of surface native oxide after FG H 2 /N 2 annealing whereby the amount of Ga–O bonds is decreased. Compared with N 2 annealing, an on-resistance of 1.68 Ω·mm, a subthreshold swing of 118 mV/dec, a transconductance peak of 513 mS/mm, a gate diode breakdown voltage of surpassing 42 V, and a high current/power gain cutoff frequency (f T / f max) of 165/165 GHz are achieved by the 50-nm InAlN/GaN HEMT on Si substrate. [ABSTRACT FROM AUTHOR]

This paper presents a new core compact model of double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs for circuit simulations. The current and the terminal charges are continuous with high computation efficiency and accuracy. Despite its accuracy, it retains the same simplicity of the industry standard transistors models. The drain current is worked out without invoking the charge-sheet approximation exploiting a quadratic symmetric polynomial interpolation of the charge in the channel. Apart this clear approximation, no other simplification is used to work out the drain current, the terminal charges, the potential, and electric field in the channel. The accuracy of the model is shown by comparison with the exact numerical solution and experimental data of the literature. [ABSTRACT FROM AUTHOR]

• The mechanism of current modulation in the open region of split-gate AlGaN/GaN HFETs can be explained by the fringe electric field (FEF) effect and polarization Coulomb field (PCF) scattering effect for the applied biased split-gate. • Experimental results and TCAD simulation reveal the role of the PCF scattering in split-gate AlGaN/GaN HFETs. • The PCF scattering modulates the current by affecting the mobility of the two-dimensional electron gas (2DEG) and is closely related to the additional polarization charges generated by the inverse piezoelectric effect. • This study further promotes the research and application of split-gate AlGaN/GaN HFETs. In this study, we fabricated two similar split-gate AlGaN/GaN heterostructure field-effect transistors (SG AlGaN/GaN HFETs). However, minor variations in structural design resulted in substantial differences in the current–voltage characteristics. The mechanism of current modulation in the open region of the HFET can be explained by the fringe electric field (FEF) effect and the polarization Coulomb field (PCF) scattering for the applied biased split-gate. In particular, the effects of FEF and PCF scattering on the two-dimensional electron gas in the open region were analyzed separately when only the open region was on. Experimental results and TCAD simulation reveal the role of PCF scattering in SG AlGaN/GaN HFETs and provide evidence for the universality of PCF scattering in electronic devices with the AlGaN/GaN heterostructure. This study is meaningful for the structural optimization and electrical performance enhancement of SG AlGaN/GaN HFETs. [ABSTRACT FROM AUTHOR]

This paper presents a compact model for the DC current of Schottky barrier field-effect transistors at deep cryogenic temperatures, close to absolute zero kelvin. The proposed model is physics based and calculates the injection current over a device's Schottky barriers, by considering physical effects at these temperatures (e.g. quantum oscillations, band tail effect, phonon-assisted tunneling, etc.). For model verification, it is compared to measurements performed on nanowire Schottky barrier transistors at a temperature of 5.5 K. [ABSTRACT FROM AUTHOR]

• A glucose biosensor was developed, fabricated and simulated using the BESOI MOSFET reconfigurable device structure; • The charges produced by the glucose oxidation reaction resulted in an increase in the drain current; • The maximum drain current increase as a function of the glucose concentration was obtained for the lowest programming gate voltage; • An optimal channel thickness of 10 nm was found to achieve higher sensitivity; • The flexibility of operation of reconfigurable transistors can be explored to obtain more sensitive sensors; • The BESOI MOSFET showed to be a promising structure for an integrated biosensor. A reconfigurable transistor glucose biosensor was fabricated using the BESOI MOSFET structure. Glucose oxidase enzyme was immobilized on the sensitive regions of the device to specifically detect glucose. The experimental measurements showed a positive linear relationship between the sensitivity and the glucose solution concentration, in the measured range (0–200 mM). The maximum value of 0.52 was obtained for programming gate voltage V GB = 15 V. Next, numerical simulations based on the previous experimental results enabled the study of the channel thickness influence on the sensitivity. An optimal channel thickness value of 10 nm was obtained, in which the generated charges due to the glucose oxidation reaction most impact the drain current level of this device. [ABSTRACT FROM AUTHOR]

[Display omitted] • HEMTs are very attractive candidates for 5G applications. • Low frequency noise were performed on AlGaN/GaN HEMTs with different channel orientation. • LF noise is an important tool for studying reliability of GaN-based HEMTs. • Flicker noise is due to trapping in the AlGaN barrier of High-Electron-Mobility Transistors. • Noise Power Spectral Density of AlGaN/GaN High-Electron-Mobility Transistors. The performance of AlGaN/GaN High-Electron Mobility Transistors (HEMTs) fabricated on 〈1 1 1〉 silicon substrates has been experimentally investigated, aiming to verify the effect of different channel orientations on the main electrical parameters, such as drain current (I D), threshold voltage, transconductance (g m), and Drain-Induced Barrier Lowering (DIBL). Moreover, the noise Power Spectral Density (PSD) with different channel orientations has also been characterized in linear operation. No noticeable differences on the electrical and noise PSD characteristics have been observed between the GaN channel orientations (0°, 90° and 45°). [ABSTRACT FROM AUTHOR]

• The proposed sensor can detect bioanalytics such as protein, APTES, Choline Oxidase and Uricase. • The impact of device design parameters like epitaxial layer doping and cavity length as well as gate oxide length is comprehensively investigated on the performance of proposed biosensor. • To consider hybridization the steric hindrance effect on the performance of the proposed sensor is also presented in this work. • The completely filled cavity provides the highest sensitivity in detecting various biomolecules, followed by increasing, concave, convex, and decreasing step profiles. • The optimum device design improves the sensitivity of ION ∼×103 and Vth ∼×2 times. • We believe the results presented in this manuscript will be immensely useful for developing future analytical models for designing the biosensor using dielectrically modulated area-scaled tunnel FET. This paper explores Si/SiGe hetero-junction dielectrically modulated area-scaled tunnel FET (DM-ASTFET) for label-free bio-sensing applications. The proposed sensor can detect bioanalytics such as protein, APTES, Choline Oxidase and Uricase. We have also investigated the influence of quantum confinement on the proposed device, and the onset voltage shifted by 0.1–0.3 V, as reported, without affecting the sensitivity mechanism. Sensitivity improvement is observed when the gate oxide length is 20 nm and the cavity length is 50 nm for a given bio-molecule due to the increased cross-section area for tunneling. The impact of epitaxial engineering on the biosensor's performance is also investigated in this work. A physics-based in-depth explanation of steric hindrance on the performance of the proposed sensor is also presented in this work. Finally, the optimum device design improves the sensitivity of I ON ∼×103 and V th ∼×2 times. [ABSTRACT FROM AUTHOR]

• Hf 0.5 Zr 0.5 O 2 (HZO)-stacked negative capacitance field-effect transistor (NCFET) for possible beyond-CMOS technology. • Impact of ferroelectric domain numbers on the performance of MFM stack and HZO-NCFET device-circuit co-design. • HZO-NCFET offers significant voltage amplification compared to conventional PZT-NCFET and P(VDF-TrFE)-NCFET. • This study predicts that HZO has a switching time approximately 20 times faster than traditional ferroelectric Pb(Nb 0.04 Zr 0.28 Ti 0.68)O 3. • The HZO-NCFET-RO outperforms standard CMOS-RO, showcasing its potential for advancing beyond-CMOS technologies and guiding NCFET design optimization. This paper explores the performance of Hf 0.5 Zr 0.5 O 2 (HZO)-stacked negative capacitance field-effect transistor (NCFET) for possible beyond complementary metal–oxide–semiconductor (CMOS) technology. For the first time, we investigate the impact of ferroelectric (FE) domain numbers on the negative capacitance (NC) effect, energy dissipation, NC effect voltage window, polarization ramping rate, voltage amplification (A NC), and oscillation frequency of a 5-stage HZO-NCFET inverter-based ring oscillator (HZO-NCFET-RO). The results show that HZO-NCFET is suitable for low-voltage and high-speed applications, providing a significant increase in A NC concerning the conventional PZT-NCFET and P(VDF-TrFE)-NCFET. Our study suggests that the HZO intrinsic NC effect time scale is tiny and limited by the FE switching. We show that the switching time of HZO is ∼20 times faster than the traditional FE [Pb(Nb 0.04 Zr 0.28 Ti 0.68)O 3 ]. Finally, the proposed 5-stage HZO-NCFET-RO offers superior performance with a 26% higher oscillation frequency and a 94.42% reduction in power dissipation compared to standard 5-stage CMOS inverter-based RO. These findings highlight the potential of HZO-stacked NCFET as an alternative device for the future beyond-CMOS technology. [ABSTRACT FROM AUTHOR]

• Atomistic quantum transport simulations of phosphorene nanoribbon FETs. • Impact of bias and quantum confinement effects on ballistic performance. • Electron injection velocity equals 2.1 × 10^7 cm/s in PNRs down to 1.5 nm width. • Bias enhancement of injection velocity up to 33% is achievable in PNRs wider than 2 nm. • Cut-off frequency of 3.2 THz obtained for PNR FETs with 2.5 nm wide channel. Atomistic quantum transport simulations are employed to study the electron injection velocity (v inj) and ballistic performance of phosphorene nanoribbon (PNR) field-effect transistors (FETs). We show that PNR bandstructure is immune to quantum confinement effects, which is seen in a rather constant v inj ≈ 2.1 × 107 cm/s down to the PNR width of 1.5 nm. Moreover, we demonstrate that the modulation of v inj by gate bias is available only for PNRs wider than 2.1 nm, with the maximum enhancement being 33%. Finally, it is reported that PNR FETs combine high cut-off frequencies above 526 GHz with acceptable bandgap that ranges from 0.7 eV to 1.6 eV in the examined PNR width range, which proves the plausibility of PNRs as channel material for future ultra-scaled high-speed FETs. [ABSTRACT FROM AUTHOR]

A new deep-learning-based parameter extraction for a global (multiple gate lengths) BSIM-CMG drain-current model is presented in this paper. The approach starts with generating 300K training dataset, consisting of 778 million data points to train the deep learning engine. Training data is generated by Monte Carlo simulation. The I-V data and the device geometry information from multiple devices serve to train a deep-learning (DL) model to predict BSIM-CMG parameters. The performance of DL-based extraction is verified by using the trained DL model to extract parameters of 10 nm FinFET technology simulated with TCAD. The DL-extracted BSIM-CMG model shows a good accuracy for eight different gate-lengths. The created BSIM-CMG global model was also able to reproduce the scalability in key electrical performance parameters such as off current I o f f , saturation current I s a t , linear current I l i n and the threshold voltage in linear V t h , l i n and saturation V t h , s a t conditions. The developed solution significantly reduces the model extraction time for a global BSIM-CMG model. This new technique can expedite the development of process design kits (PDK). • Automatic parameter extraction of BSIM-CMG I-V global parameters. • Tested on TCAD simulated data calibrated to Intel 10 nm node with gate lengths from 16 nm to 100 nm. • Created global model captures the trends in I-V data and key electrical parameters accurately. [ABSTRACT FROM AUTHOR]

• Systematic evaluation of threshold voltage extraction methods in FD-SOI MOSFET. The threshold voltage in ultrathin FD-SOI MOSFETs is revisited from theoretical definitions to pragmatic extraction techniques, including novel ones. Their respective merits and limitations are underlined. [ABSTRACT FROM AUTHOR]

• Non-GCA model into velocity saturation region is developed for ground-plane MOSFETs. • It starts with GCA model by analytically solving 1-D Poisson's equation. • Non-GCA model is then derived with the effect of lateral-field driven mobile charge. • It has I ds - V ds similar to the published data by adding source and drain resistance. A non-GCA (Gradual Channel Approximation) model continuous into the velocity saturation region is developed for ground-plane bulk MOSFETs. The I ds -V ds characteristics generated by both the n = 1 and the n = 2 models are consistent with 2-D simulations. By incorporating source and drain series resistance into the model, it is shown that the model can reproduce the I ds -V ds data of 20 nm bulk MOSFETs published in the literature. [ABSTRACT FROM AUTHOR]

• Aknee has been observed in the mesa isolated SOI pMOSFETs transfer characteristic. • The mesa isolation induces a presence of a parasitic transistor at the SOI pMOSFETs edges, which conducts earlier than the main transistor. • A methodology was presented to decompose edge and center contributions in mesa-isolated SOI pMOSFETs around threshold. • We revealed that the subthreshold regime is always driven by the edges. This work proposes a methodology to decompose the center and edge current contributions around threshold in mesa-isolated SOI MOSFETs using 3D TCAD simulations. Applied to pMOS measurements, it reveals that the subthreshold regime is driven by the active edge, whatever the device width. It also explains why the threshold voltage modulation by the back-gate bias depends on the device width, as well as why these effects are worse for high channel doping values. [ABSTRACT FROM AUTHOR]

• Low access resistance and low mobility are observed for p-channel vertical gate-all-around nanowire FETs. • The extracted access resistance revels that the access resistance in the drain side R D represents ∼20% of the total access resistance, while the access resistance in the source side is R D ∼80%. • The 1 / f behavior of the asymmetric GAA VNW FETs may be explained in the framework of the correlated carrier number and mobility fluctuation mechanism. • In strong inversion the access resistances noise contribution dominates the 1/f noise for both operation mode (forward/reverse). In this work, DC and low frequency noise measurements are performed in p-channel gate-all-around (GAA) silicon vertical nanowire (Si VNW) MOSFETs. The DC measurements highlight asymmetry in the drain current and transconductance transfer characteristic even in linear operation, at an applied drain voltage of −50 mV. A novel Y-function based strategy for parameter extraction in S/D asymmetric devices is proposed. This novel strategy allows the estimation of the value of each access resistance, from source and from drain sides, respectively, and allows overcoming the device asymmetry to provide an accurate extraction of the main DC parameters. The low-frequency noise studies on forward and reverse operation mode, demonstrate that the 1/f noise in both modes can be explained by the correlated carrier number (Δn) and mobility fluctuation (Δμ) mechanisms, with additional contribution of the access resistance noise in strong inversion. [ABSTRACT FROM AUTHOR]

• The impact of various ion implantation schemes on the subthreshold behavior of cryogenic FD SOI MOSFETs is investigated. • The density of localized states was decreased by the optimized ion implantation into silicide process. • The effects of ion implantation angle and activation temperature were systematically studied. Band tailing is a critical issue for cryogenic CMOS, which significantly degrades the performance of conventional MOSFETs at cryogenic temperature. The band tail arises primarily due to Gaussian-distributed localized states, which can be induced by ion implantation during source/drain formation. In this study, we investigate the impact of various ion implantation schemes on the subthreshold behavior of cryogenic fully depleted (FD) SOI MOSFETs. By optimizing the ion implantation into silicide (IIS) process, we were able to reduce the density of localized states and achieve a steep switching performance at 5 K. We systematically examine the effects of ion implantation angle and activation temperature of IIS on the device performance at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

• Experimental evaluation of analog parameters of GAA nanosheet transistors, in a temperature range from 473 Kto 173 K. • TheNSt transistors present a good behavior when decreasing the temperature, especially due to the improvement of the carrier mobility. • Besides being designed mainly for digital applications, the NS transistors present a promising analog characteristics, with a great gm/ID and a high Av. • The evaluated analog parameters represent key transistors characteristics for analog circuit design, being possible to determine which dimension are most appropriate for a given situation, including the temperature dependence. This work presents an experimental evaluation of n-type, gate-all-around (GAA), vertically stacked nanosheet field effect transistors (NSFETs) operating in a temperature (T) range from 473 K down to 173 K and focusing on their use for analog applications. Devices with gate lengths (L gate) of 28 nm to 200 nm were analyzed. Besides exhibiting a slight short channel effect, the shorter transistors show a good performance in terms of analog application, presenting at 173 K an intrinsic voltage gain (A V) of 30 dB and unit gain frequency (f T) of 185 GHz. This is also seen in two figures of merit that characterize the transistor performance for analog circuit design: the transistor efficiency (gm/I DS) and the gain frequency product (A V *f T). The optimum region of operation was demonstrated to be at strong inversion by the trade-off between gm/I DS and f T , where in this region L gate = 28 nm presents a gain frequency product of ∼ 5,5THz at T = 173 K. At lower temperature, as expected, it is confirmed that the carrier mobility and the subthreshold swing (SS) improve while the threshold voltage (V T) increases. [ABSTRACT FROM AUTHOR]

• TCAD simulation of liquid-gate graphene field effect transistor. • Tuned user-defined materials to include the electrolyte and monolayer graphene effect. • Anchored antibodies in the surface of the sensor modeled as charged boxes. • Antibody-Antigen binding event modifies the charge trapped at the surface of the sensor. • Response of the sensor measured as the drift of the minimum current point of the current–voltage characteristic. We used a commercial TCAD simulator for the study of liquid-gate Graphene FETs as antibody-based sensors. To model the graphene layer, a zero-bandgap semiconductor with a linear density of states relationship in both the conduction and valence bands near the edge of the bands was adopted. The electrolyte which forms the liquid gate was also modeled as a semiconductor with tuned parameters to reproduce the behavior of a dilute PhosphateBuffer Saline (PBS) solution with pH = 7.4. Antibodies are anchored to the graphene surface and their effect is simulated with a charged cube box with a size similar to the one of the IgG antibody and a charge concentration similar to the charge usually carried by an anibody. The binding of the antibody with the antigen protein (Ab-Pr) complex is also represented in the simulator with a charged box carrying a different charge. We have calculated the I D -V FG curves for different numbers of antibodies anchored to the surface of the graphene and analyzed the behavior of the sensor as a function of the number of antibody-protein complexes. [ABSTRACT FROM AUTHOR]

• Experimental analysis of a MISHEMT analog behaviour. • Transconductance and output conductance gate length dependence. • Study of the device's behavior under temperature variation from 450 K down to 200 K. • The effect of multiple conductions mechanisms in MISHEMT. This work presents an experimental analysis of Metal-Insulator-Semiconductor High Electron Mobility transistor (MISHEMT) operating in a temperature range from 450 K down to 200 K, focusing on analog applications. The drain current and consequently the saturation transconductance (gm sat) showed to be slightly dependent on gate length. The output conductance (g D) presents a higher dependence with gate length than gm sat for the whole temperature range due to the influence of MOS conduction that is strongly affected by short channel effect. There is also a kink in the behavior of these parameters at 350 K, most likely due to the competition of temperature effects on different conduction mechanisms. The transistors showed a good performance in terms of analog application, where the intrinsic voltage gain (A V) increases from 38 dB (at 200 K) to 43 dB (at 450 K) for 800 nm gate length while the unity gain frequency (f T) decreases from 1.8 GHz (at 200 K) to 800 MHz (at 450 K) for a gate length of 400 nm, which makes MISHEMT a good candidate for analog applications. [ABSTRACT FROM AUTHOR]

• Nitride-based hot electron transistor (HET) with current density above 1 MA/cm2. • Temperature-independent characteristics indicate the dominant role of LO-phonon emission in scattering of hot electrons. • Proposed structure for demonstration of nitride-based coherent transistor. Previously we demonstrated high-current, high-gain III-nitride hot electron transistors (HETs) with collimated electron injection into an undoped base region, reaching collector current density of ∼0.44 MA/cm2 and Gummel gain β ∼ 2 at 300 K. Here, we compare the behavior of these devices from 300 to 77 and 4.2 K to elucidate the role of hot electron scattering in limiting the performance. Under cryogenic operation and Gummel biasing, we obtain a maximum current gain of 3.5 at a collector current density of 1.35 MA/cm2, limited by the onset of intervalley electron transfer, and common-emitter current gain β > 20. Our results point to the promise of nitride HETs for realizing the long-proposed coherent transistor. [ABSTRACT FROM AUTHOR]

• This work presents experimental results of the series resistance variability in junctionless and inversion-mode nanowire transistors. • Due to series resistance, drain-current variability is larger than Y-function variability both in junctionless and inversion mode nanowires. • The influence of source-drain series resistance is higher on drain-current variability for junctionless than inversion mode, presenting an increase of up to 50% depending on the width and channel length. • Results suggest that series resistance variation impacts junctionless more than inversion mode nanowire transistors. This work analyzes the influence of source-drain series resistance variability over the drain current in junctionless and inversion mode nanowire transistors. A comparison between drain current and Y-function variability is presented using experimental data of nanowires with different widths and channel lengths. The source-drain series resistance variability is also presented. The results indicates that source-drain series resistance influence is higher on drain current variability for junctionless than inversion mode nanowire transistors. [ABSTRACT FROM AUTHOR]

• An EZFET is a simple and reliable characterization device for substrates and gate stacks. • Junctionless EZFET removes the temperature limitation of junctions activation for low temperature integration applications. • A complete model reproduces the peculiar device behavior. • A simplified parameters extraction methodology provides reliable substrate and gate stack evaluation. • The junctionless EZFET can be used for two-dimensional that cannot be doped. The junctionless EZ-FET is a device with simplified architecture and processing. With only two lithography levels and using regular process steps, it enables fast electrical characterization of semiconductor films on insulators (SOI) with undoped source and drain. An electrical model reproducing the peculiar transfer characteristics of a junctionless EZ-FET is presented in this work. Based on this model, a simplified parameter extraction methodology is proposed and used to access the electrical properties of SOI structures (i.e. threshold voltage, mobility). [ABSTRACT FROM AUTHOR]

This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affecting the ac response of pseudo-MOSFET structure for SOI wafer with thin SOI film by using simple series and parallel circuits composed of resistance and capacitance. Our measurement results show the gate bias range where the influence of the contact resistance becomes dominant in measurements with single and multiple probes. The degradation of the capacitance measured at high frequency is also analyzed by constructing an equivalent circuit, which detach the influence of the contact and channel resistances quantitatively. The necessity to carefully account for the influence of the contact resistance in pseudo-MOS method is clarified. [ABSTRACT FROM AUTHOR]

Methods for characterization of MOSFET gate overlap capacitances are briefly discussed. Considerations of their shortcomings due to the neglected shortening and/or narrowing of the MOSFET channel in relation to its drawn size have led to development of a new method for a simultaneous extraction of the gate overlap capacitances and of the channel width and length variations. The approach is presented and illustrated using experimental data obtained by C-V measurements of the MOSFETs in a CMOS test structure. The characterization results are compared with the parameters obtained via I-V measurements of the corresponding devices. [ABSTRACT FROM AUTHOR]

This paper reports an improved method for estimating the thermal resistance of a MOSFET device using the inverse of the transistor efficiency as a function of the power applied to the transistor's channel. This method was deduced considering that the main effect of the self-heating is on the carriers' mobility, where the temperature dependency, vertical/lateral field degradation and saturation velocity were taken into account. After performing the analytical considerations, the method was validated through numerical simulations to verify if its results were compatible with other traditional pulsed-like method for the thermal resistance extraction. This improved method was applied experimentally to attest its robustness. The advantages of this method are the use of DC measurements only and differences smaller than 10 K in the estimation of the absolute channel temperature due to the self-heating effect compared to a traditional pulsed-like method for the UTBB SOI studied in this work. [ABSTRACT FROM AUTHOR]

In this paper, a charge-based analytical model for intrinsic capacitances in tunnel field-effect transistors (TFETs) is presented. The model is derived for a Si Double-Gate (DG) n-TFET whose flexibility is applicable to single-gate or p-type TFETs as well. The model is verified comparing with the TCAD simulations as well as measurements data. Considering the capacitances of fabricated Si planar p-TFETs on Ultrathin Body, some deviations between TCAD simulations, compact model and measurements are observed. Here the effect of Schottky barriers at NiSi 2 contacts are analyzed and a theory for the reason associated deviations and the unexpected behavior of intrinsic capacitances is evolved. Furthermore, a technique to include this effect in the aforementioned model is also presented. [ABSTRACT FROM AUTHOR]

The built-in bipolar junction transistor (BJT) of a BIMOS fabricated in 28 nm ultra-thin body and BOX (UTBB) fully-depleted silicon-on-insulator (FD-SOI) high-k metal gate technology is investigated in common-emitter mode and in built-in metal-oxide-semi-conductor field effect transistor (MOSFET) off-state. In the weak V BE regime, field-effects dominate, generating a negative base current and making the current gain β 0 meaningless. For V BE high enough, the BJT works normally but with a very low gain below 1. [ABSTRACT FROM AUTHOR]

This paper investigates the digital circuit-level performance of an inverter realised with n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/ Al 0.05 Ga 0.95 Sb tech nology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different I OFF values, namely 100 nA/ μ m and 10 pA/μm to target both high-performance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for I OFF = 10 pA/μm. [ABSTRACT FROM AUTHOR]

Quantum drift diffusion corrections, models for the one- and two-dimensional density of states, a non-local model for source-to-drain tunneling, and a simple ballistic mobility model are jointly used to simulate I D V GS -characteristics of scaled III-V-channel nFETs. The sub-threshold swing of double-gate ultra-thin-body and gate-all-around nanowire geometries are extracted for different gate lengths, and the semi-classical results are compared with those from the quantum transport simulator QTx. The low-dimensional density of states in combination with the ballistic mobility yields an overall good agreement with the QTx transfer curves after the onset of inversion and decreases I ON by two orders of magnitude in comparison to the simulation with a large diffusive mobility. It is shown that source-to-drain tunneling sets a limit to scaling at a gate length of about 10 nm due to the degradation of the sub-threshold swing. Simulating this effect with a low-dimensional density of states reveals inconsistencies. They are attributed to the tunneling model, which had been derived for a three-dimensional electron gas. [ABSTRACT FROM AUTHOR]

Variability is one of the major roadblocks for III-V semiconductors in nanoscale devices, according to the recent International Roadmap for Devices and Systems (IRDS). A particular concern is the detrimental effect of variability of threshold voltage due to channel compositional variations. In this paper, we investigate the impact of this variability source and the effects of scaling on the performance of Dual-Gate-Ultra-Thin-Body (DG-UTB) In 0.53 Ga 0.47 As MOSFETs. We model mole fraction variations in terms of the Indium content by taking into account the spatial inhomogeneity of the channel and the corresponding bandgap variations, analyzing the effects on threshold voltage variability. We thus define a variability source, i.e., Band Gap Fluctuation (BGF), and we compare the associated variability with the ones from other important sources, namely, Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (B-LER and G-LER). We then define three corner cases for mole fraction variations to determine worst-case variability. Finally, the impact of scaling on variability is assessed by comparing results for two technology nodes on the linear and saturation threshold voltage, V T,lin , V T,sat , on-current, I ON , leakage current, I OFF , and linear and saturation sub-threshold slope, SS. We find that although scaling has no impact on BGF-induced V T variability, it increases the total V T,lin variability as well as that for I ON and I OFF. [ABSTRACT FROM AUTHOR]

This work evaluates the operation of p-type Si 0.7 Ge 0.3 -On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow Ω-gate to quasi-planar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20 nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor. [ABSTRACT FROM AUTHOR]

We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low I ON and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (L rt) yields a very steep slope and higher I ON compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (1021 cm−3) thin layer at the bottom for extremely small body thickness (T Si < 7 nm), increases I ON even for small gate lengths (L G < 100 nm). The implementation of an embedded tip in the source enhances the maximum electric field at the source/channel junction, but the impact on the performance is limited because the tunneling area is not increased. Therefore, this architecture provides a performance similar to a standard TFET. TCAD simulations using SiGe with different germanium concentrations (30% and 50%) and pure germanium, instead of silicon, show an increase of the interband tunneling current when using an ultrahigh dopant concentration thin boron layer for small gate lengths (L G < 50 nm). The reduction of the tunneling current using a relatively thick channel (11–7 nm) can be compensated by using a higher germanium concentration to reduce the energy bandgap. However, this will increase the density of defects causing a TAT tunneling instead of interband tunneling, jeopardizing the possibility of achieving a subthreshold swing below 60 mV/dec. [ABSTRACT FROM AUTHOR]

We thoroughly compare the DC electrical behavior of n-MOS transistors based on Si nanowires with 〈 1 0 0 〉 and 〈 1 1 0 〉 channel orientations by means of Multi-Subband Ensemble Monte Carlo simulations. We find that the drain current depends on the nanowire diameter and it is slightly, but consistently, larger for 〈 1 0 0 〉 than for 〈 1 1 0 〉 nanowires. The observed differences in mobility, velocity and spatial charge distribution are interpreted in terms of the effective masses and populations of the different Si conduction band valleys, whose sixfold degeneracy is lifted by quantum confinement in narrow nanowires. Finally, we study the scaling behavior for channel lengths down to 8 nm, concluding that the differences observed between orientations are minimal. [ABSTRACT FROM AUTHOR]

Steep slope negative capacitance MOSFETs with HfYO x ferroelectric on FDSOI were experimentally demonstrated. An average SS of 30 mV/dec was achieved over 3 decades of drain current. The negative capacitance is believed to be a transient phenomenon because a strong polarization switching is needed for the steep slope. We found that the sub-thermal SS degrades with the cycling measurements, which is assumed to be caused by the trap charging in the ferroelectric oxide layer. The tradeoff between polarization and charge trapping is responsible for the subthreshold behavior of the device. [ABSTRACT FROM AUTHOR]

• SOI and SOS pseudo-MOSFETs with 20 nm hafnia interlayers show normal gate-drain characteristics after annealing ≥ 1000 °C with the carrier mobility as in bulk silicon. • Highly stable ferroelectric hysteresis was observed in the case of SOS pseudo-MOSFETs. • Formation of a HfO 2 film, having the ferroelectric phase OII (Pmn2 1) is stabilized by a compressive stress in the case of SOS pseudo-MOSFETs. The formation of a multi-crystalline HfO 2 film, containing the ferroelectric phase OII (Pmn2 1) after a high-temperature annealing at 1100 °C, was experimentally observed by HREM for the first time in silicon-on-sapphire (SOS) structures obtained by direct bonding and a hydrogen transfer of silicon layer on Si or C-sapphire substrates, respectively. PEALD HfO 2 interlayers with the thickness of 20 nm were deposited on silicon before bonding to reduce the defects and magnitude of their charge at the SOS and silicon-on-insulator (SOI) interfaces. SOS pseudo-MOS transistors demonstrate standard drain-gate characteristics with the same charge carrier mobility as in bulk silicon and a small positive fixed charge (≤1.2 × 1012 cm−2). Moreover, a stable ferroelectric hysteresis with ΔV G ∼700 V observed only in SOS FETs is promising for the embedded memory formation and it extends the functionality of logic circuits. It was concluded that the OII phase is stabilized mainly by a high compressive stress and it can be responsible for the hysteresis in the case of SOS pseudo-MOSFETs opposite to the SOI-structure. [ABSTRACT FROM AUTHOR]

This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures. [ABSTRACT FROM AUTHOR]

• This paper presents a benchmarking comparison between InAs FinFET and gate-all-around (GAA) MOSFET. • A 2-D TCAD simulation is then performed to understand the operation of the InAs nanowire transistors. • The normalized on-current of GAA MOSFET is lower than FinFET in addition to the more complexity during fabrication. • Significant boost in transistor DC/RF performances is possible with these devices with optimizations in materials and device geometry. This paper presents a benchmarking comparison between InAs FinFET and gate-all-around (GAA) MOSFET by a 3-D TCAD simulation. The complete FinFET fabrication process is demonstrated followed by a TCAD simulation platform based on the experimental data. Both DC and RF simulation results are shown here. Further optimizations are explored for InAs FinFET/GAA MOSFET through TCAD simulations. It is found that with optimizations in materials, device geometry and fabrication, significant enhancement in DC/RF performances is possible with these devices. In addition, GAA MOSFET shows a better potential for future RF application. [ABSTRACT FROM AUTHOR]