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Abstract Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect densities are increasing in future submicron technologies, more advanced solutions may be required for memories to be produced in the upcoming nanometric CMOS process generations. Moreover, this problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels of several orders of magnitude higher than in current CMOS technologies. For such defect densities, traditional memory repair is not adequate. This work presents several Built-In Self Repair techniques addressing memories affected by high defect densities as well as an evaluation of the area cost and yield. Statistical fault injection simulations were conducted and the obtained results show that BISR architectures can be used for future high defect technologies, providing close to 100% memory yield, by means of reasonable hardware cost. Thus, the extreme defect densities that many authors predict for nanotechnologies do not represent a show-stopper, at least as concerning memories.

This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach.

This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test,...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.

Self-checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This work is aimed to reach these requirements for the design of self-checking shifters and is part of a broader project concerning the design of self-checking data paths.

In this paper we first present an improved self-checking solution for the sequencing part of the Motorola MC 68000 microprocessor. compared to previous self-checking proposals for this microprocessor, the present scheme decreases the area overhead and simplifies the complexity of both functional circuits and checkers. In addition, the unified BIST method introduced recently, is applied to this scheme. This method uses a merging of self-checking and BIST techniques and allows a high fault coverage for all tests needed for the integrated circuits, e.g. off-line test for fabrication faults and for maintenance, and on-line concurrent error detection in the field.

Signature analyzers are very efficient output response compactors for BIST design. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this article, in order to increase the effectiveness of ROM BIST, we take advantage from the simplicity of the error patterns generated by ROMs and we show that aliasing free signature analysis can be achieved in ROM BIST.

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.

It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in self-checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples.