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In this study, we present low-energy proton single-event upset (SEU) data on a 65 nm SOI SRAM whose substrate has been completely removed. Since the protons only had to penetrate a very thin buried oxide layer, these measurements were affected by far less energy loss, energy straggle, flux attrition, and angular scattering than previous datasets. The minimization of these common sources of experimental interference allows more direct interpretation of the data and deeper insight into SEU mechanisms. The results show a strong angular dependence, demonstrate that energy straggle, flux attrition, and angular scattering affect the measured SEU cross sections, and prove that proton direct ionization is the dominant mechanism for low-energy proton-induced SEUs in these circuits.

This conference presents the recipients of the Outstanding Conference Paper Award from the 2015 IEEE Nuclear and Space Radiation Effects Conference.

The recipients of the 2014 NSREC Outstanding Conference Paper Award are Nathaniel A. Dodds, James R. Schwank, Marty R. Shaneyfelt, Paul E. Dodd, Barney L. Doyle, Michael Trinczek, Ewart W. Blackmore, Kenneth P. Rodbell, Michael S. Gordon, Robert A. Reed, Jonathan A. Pellish, Kenneth A. LaBel, Paul W. Marshall, Scot E. Swanson, Gyorgy Vizkelethy, Stuart Van Deusen, Frederick W. Sexton, and M. John Martinez, for their paper entitled "Hardness Assurance for Proton Direct Ionization-Induced SEEs Using a High-Energy Proton Beam." For older CMOS technologies, protons could only cause single-event effects (SEEs) through nuclear interactions. Numerous recent studies on 90 nm and newer CMOS technologies have shown that protons can also cause SEEs through direct ionization. Furthermore, this paper develops and demonstrates an accurate and practical method for predicting the error rate caused by proton direct ionization (PDI).

We report low-energy proton and alpha particle SEE data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) that demonstrates the criticality of understanding and using low-energy protons for SEE testing of highly-scaled technologies

The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data from 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. As a result, we show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.

The potential for using the degraded beam of high-energy proton radiation sources for proton hardness assurance testing for ICs that are sensitive to proton direct ionization effects are explored. SRAMs were irradiated using high energy proton radiation sources (~67-70 MeV). The proton energy was degraded using plastic or Al degraders. Peaks in the SEU cross section due to direct ionization were observed. To best observe proton direct ionization effects, one needs to maximize the number of protons in the energy spectrum below the proton energy SEU threshold. SRIM simulations show that there is a tradeoff between increasing the fraction of protons in the energy spectrum with low energies by decreasing the peak energy and the reduction in the total number of protons as protons are stopped in the device as the proton energy is decreased. Two possible methods for increasing the number of low energy protons is to decrease the primary proton energy to reduce the amount of energy straggle and to place the degrader close to the DUT to minimize angular dispersion. These results suggest that high-energy proton radiation sources may be useful for identifying devices sensitive to proton direct ionization.

We measured low-energy proton radiation induced soft error rates (SER) of standard and reduced-SER (RSER) latches, manufactured in 32 nm and 45 nm bulk CMOS technologies, and conclude that sequential logic elements built in these technologies are not yet susceptible. Further, our results demonstrate that at proton energies where direct ionization dominates, critical charge (Qcrit) plays a far bigger role than at proton energies above the nuclear reaction threshold.

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.

A 1 GeV/amu 56Fe ion beam allows for true 90° tilt irradiations of various microelectronic components and reveals relevant upset trends at the GCR flux energy peak. Three SRAMs and an SRAM-based FPGA evaluated at the NASA Space Radiation Effects Laboratory demonstrate that a 90° tilt irradiation yields a unique device response. These tilt angle effects need to be screened for, and if found, pursued with radiation transport simulations to quantify their impact on event rate calculations.

We report new results from both broad-beam, heavy-ion and proton experiments for circuit-level RHBD techniques in SiGe digital logic. Redundant circuit elements within the latches are used to significantly reduce single-event upset rates in shift registers and clock paths, without resorting to TMR techniques.

We investigate a novel implementation of junction isolation to harden a 200 GHz SiGe:C HBT technology without deep trench isolation against single event effects. The inclusion of isolation is shown to have no effect on the dc or ac performance of the nominal device, and likewise does not reduce the HBTs inherent tolerance to TID radiation exposure on the order of a Mrad. A 69% reduction in total integrated charge collection across a slice through the center of the device was achieved. In addition, a 26% reduction in collected charge is reported for strikes to the center of the emitter. 3-D NanoTCAD simulations are performed on RHBD and control device models yielding a good match to measured results for strikes from the emitter center to 8 ?m away. This result represents one of the most effective transistor layout-level RHBD approaches demonstrated to date in SiGe.

Silicon-germanium heterojunction bipolar transistor (SiGe HBT) heavy ion-induced current transients are measured using Sandia National Laboratories' microbeam and high- and low-energy broadbeam sources at the Grand Acce?le?rateur National d'Ions Lourds, Caen, France, and the University of Jyva?skyla?, Finland. The data were captured using a custom broadband IC package and real-time digital phosphor oscilloscopes with at least 16 GHz of analog bandwidth. These data provide detailed insight into the effects of ion strike location, range, and LET.

We investigate the single-event transient (SET) response of bandgap voltage references (BGRs) implemented in SiGe BiCMOS technology through heavy ion microbeam experiments. The SiGe BGR circuit is used to provide the input reference voltage to a voltage regulator. SiGe HBTs in the BGR circuit are struck with 36-MeV oxygen ions, and the subsequent transient responses are captured at the output of the regulator. Sensitive devices responsible for generating transients with large peak magnitudes (more than 5% of the dc output voltage) are identified. To determine the effectiveness of a transistor-layout-based radiation hardened by design (RHBD) technique with respect to immunity to SETs at the circuit level, the BGR circuit implemented with HBTs surrounded by an alternate reverse-biased pn junction (n-ring RHBD) is also bombarded with oxygen ions, and subsequent SETs are captured. Experimental results indicate that the number of events causing transients with peak magnitude more than 5% above the dc level have been reduced in the RHBD version; however, with the inclusion of the n-ring RHBD, new locations for the occurrence of transients (albeit with smaller peak magnitude) are created. Transients at the transistor-level are also independently captured and are presented. It is demonstrated that while the transients are short at the transistor level (ns duration), relatively long transients are obtained at the circuit level (hundreds of nanoseconds). In addition, the impact of the SET response of the BGR on the performance of an ultra-high-speed 3-bit SiGe analog-to-digital converter (ADC) is investigated through simulation. It is shown that ion-induced transients in the reference voltage could eventually lead to data corruption at the output of the ADC.

We investigate the applicability of current total ionizing dose (TID) test protocols in the context of advanced transistor technologies such as Silicon-Germanium heterojunction bipolar transistors(SiGe HBTs). In SiGe HBTs, an unexpected shift in collector current is observed during total dose irradiation. Using both device and circuit measurements, we investigate this phenomenon and assess its potential importance in hardness assurance of SiGe components. TCAD simulations were performed to explain the observed current shifts.

This work examines the individual impact of drift and diffusion charge collection in the collector-base (CB) and collector-substrate (CS) junctions on single-event-upset (SEU) in SiGe HBT current mode logic (CML) circuits. The CS junction diffusion charge collection has negligible impact on circuit SEU, despite its large charge collection magnitude. The CB and CS drift charge collection are primarily responsible for the observed SEU in CML circuits. The CB drift charge collection is as important as the CS drift charge collection, even though its charge magnitude is much less, because the resulting current excitation appears between collector and base nodes, and hence is amplified. Using selective ion track placement, we show that an ion track passing through the physical CS junction is much more effective in causing SEU than an ion track not passing through the CS junction because of potential funneling and consequent large induced drift current magnitude, which is necessary for SEU of CML circuit.

The mechanism for ionizing radiation damage in multi-finger SOI CMOS devices is presented for the first time. We analyzed the effects of shallow-trench isolation on ionizing radiation response of 65 nm Silicon-On-Insulator (SOI) CMOS technology. The radiation response of the CMOS devices was investigated using 63 MeV protons and 10 keV X-rays. The implications of proton irradiation and X-ray irradiation on the dc and RF performance of these devices are presented. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. Even though there is charge-accumulation in the buried-oxide, there is minimal impact on the front-gate characteristics of the partially-depleted SOI devices in this 65 nm CMOS technology. The implications of parasitic conduction along the STI on device design constraints, particularly for varying device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that body-contacting schemes which eliminate sidewalls (e.g., H-body, T-body) will provide the necessary total-dose radiation tolerance for multi-finger analog and RF devices, without additional hardening techniques.

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events.

The effects of 63 MeV proton irradiation on 65nm Silicon-On-Insulator (SOI) CMOS technology are presented for the first time. The radiation response of the CMOS devices was investigated up to an equivalent total gamma dose of 4.1 Mrad (SiO2). We analyze the implications of proton irradiation on RF performance of these devices. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. High-frequency measurements show that the input and output matching conditions are not affected, up to a cumulative dose of 4.1 Mrad. The implications of proton irradiation on device design constraints, particularly device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that the higher finger width devices, of sufficient gate width, are well-suited for the development of total-dose radiation tolerant analog and RF circuits without additional radiation hardening.

The effects of materials surrounding the active devices on single event-induced charge generation in a proton-irradiated Si diode array are shown be significant. Particle scatters in layers underlying the device have an impact on the response of a focal plane array. This effect is likely to be important in a variety of semiconductor devices.

This paper presents the first comprehensive investigation of the impact of proton irradiation on the performance of high-voltage (HV) nMOS transistors implemented in a low-voltage (LV) SiGe BiCMOS technology. The effects of irradiation gate bias, irradiation substrate bias, and operating substrate bias on the radiation response of these transistors are examined. Experimental results show that the radiation-induced subthreshold leakage current under different irradiation biasing conditions remains negligible after exposure to a total dose of 600 krad(Si). We find that there are differences in the radiation response of LV and HV MOSFETs, suggesting that the mechanisms involved in causing degradation in LV and HV transistors could be of fundamentally different origins.

This work presents 3-D mixed-mode simulation results of single event transients (SET) in SiGe HBT emitter followers. The impact of circuit design parameters, including biasing current and resistance are detailed. A simple increase of biasing emitter current is shown to be ineffective for hardening. Instead, during SET, the emitter voltage upset simply follows the base voltage upset due to the inherent nature of the emitter follower topology during circuit operation. The duration and the peak value of the base voltage upset are determined by the impedance and electric field between collector and base. As a result, the use of a smaller base biasing resistance is desirable for reducing SETs in emitter followers.

We report the first irradiation results on high-frequency SiGe HBT and CMOS phase shifters for space-based, phased-array antennas used in radar or wireless communication systems. Both phase shifter circuits remain functional with acceptable dc and RF performance up to multi-Mrad proton exposure, and are thus suitable for many orbital applications. In addition, simulation results probing the limits of phase shifter performance in a radiation environment are presented. These results show that both CMOS and SiGe HBT based phase shifters can be used for space-based applications without any specific radiation hardening techniques.

Experimental results are presented on proton induced single-event-upsets (SEU) on a 65 nm silicon-on-insulator (SOI) SRAM. The low energy proton SEU results are very different for the 65 nm SRAM as compared with SRAMs fabricated in previous technology generations. Specifically, no upset threshold is observed as the proton energy is decreased down to 1 MeV; and a sharp rise in the upset cross-section is observed below 1 MeV. The increase below 1 MeV is attributed to upsets caused by direct ionization from the low energy protons. The implications of the low energy proton upsets are discussed for space applications of 65 nm SRAMs; and the implications for radiation assurance testing are also discussed.

Microbeam measurements and TCAD simulations are used to examine the effects of ion angle of incidence on the charge collected from events occurring in a Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT). The results identify the geometrically driven charge-collection mechanisms that dominate the low LET broad beam SEU response. The deep trench isolation that surrounds the transistor significantly modulates the charge transport and, therefore, the charge collected by the collector. A new way of estimating critical charge, , for upset in SiGe HBT circuits is proposed based on TCAD simulation results and measured broadbeam data.

We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from the sub-collector to substrate junction. The inclusion of the n-ring affects neither the DC nor AC performance of the SiGe HBT and does not compromise its inherent multi-Mrad TID tolerance. The effects of ion strike location and angle of incidence, as well as n-ring placement, area, and bias on charge collection are investigated experimentally using a 36 MeV O2 microbeam. The results indicate that charge shunting through the n-ring can result in up to a 90% reduction in collector collected charge for strikes outside the DT and a 18% reduction for strikes to the emitter center. 3-D transient strike simulations using NanoTCAD are used to verify the experimental observations, as well as shed insight into the underlying physical mechanisms. Circuit implications for this RHBD technique are discussed and recommendations made.

This work draws on experimental and simulation results to derive a generalized SEU response model for bulk SiGe HBTs. The model was validated using published heavy ion and new proton data gathered from high-speed HBT digital logic integrated circuits fabricated in the IBM 5AM SiGe BiCMOS process. Calibrating to heavy ion data was sufficient to reproduce the proton data without further adjustment. The validated model is used to calculate upset event rates for low-earth and geosynchronous orbits under typical conditions.

In this work we present a new circuit-level hardening technique for SEU mitigation in high-speed SiGe BiCMOS digital logic. A reduction in SEU vulnerability is realized through the implementation of an additional storage cell redundancy block to achieve the required decoupling. When compared with latch duplication, current sharing or gated feedback techniques, this method incurs a lower power penalty and no speed penalty. The hardened circuit is implemented in CML and LVL families and circuit simulation models predict significant reduction in the number of upsets compared to the corresponding unhardened versions. The technique is also easy to incorporate into existing designs.

This paper presents a study of the performance degradation in a proton environment of long wavelength infrared (LWIR) HgCdTe detectors. The energy dependence of the Non-Ionizing Energy Loss (NIEL) in HgCdTe provides a framework for estimating the responsivity degradation in LWIR HgCdTe detectors due to on-orbit exposure from protons. Banded detector arrays of different detector designs were irradiated at proton energies of 7, 12, and 63 MeV. These banded detector arrays allowed insight into how the fundamental detector parameters degraded in a proton environment at the three different proton energies. Measured data demonstrated that the detector responsivity degradation at 7 MeV is 5 times larger than the degradation at 63 MeV. Comparison of the responsivity degradation at the different proton energies suggests that the atomic Columbic interaction of the protons with the HgCdTe detector is likely the primary mechanism responsible for the degradation in responsivity at proton energies below 30 MeV.

We investigate the effects of both X-ray and proton irradiation on a novel 200 GHz/90 GHz (npn/pnp) complementary SiGe:C HBT technology. The DC forward mode total dose tolerance of the pnp HBTs is shown to exceed that of the npn HBTs by a significant margin after being subjected to both 63-MeV proton and 10-keV X-ray sources, while the AC characteristics of both devices exhibit no degradation up to X-ray doses as high as 1.8 Mrad(SiO2). Pre- and post-irradiation results from a current feedback operational amplifier implemented in this technology and irradiated up to a dose of 1.8 Mrad(SiO2) are presented, showing no degradation in performance metrics under two low current density bias configurations.

Proton and X-ray irradiation effects are investigated in 0.35 m conventional, annular, and ringed-source radiation-hardening-by-design (RHBD) CMOS devices. Transistors were irradiated with protons at both 300 K and 77 K. Radiation-induced oxide trapped charges in the shallow trench isolation (STI) oxide deplete the p-substrate and effectively shunt the source and drain, inducing off-state leakage. Without the STI, RHBD nFETs exhibit no radiation-induced off-state shunt leakage currents for devices irradiated at both 300 K and 77 K. Conventional 0.35 mum pFETs were not degraded by proton irradiation, since the leakage path cannot be formed in the n-well. A simple CMOS logic inverter shows no degradation in output voltage after proton irradiation for all tested temperature and bias conditions. More advanced 130 nm node nFETs show less TID sensitivity to STI leakage due possibly to the smaller physical STI volume and/or additional doping located on the STI sidewall.

Proton-induced energy deposition in a silicon P-i-N focal plane array is analyzed with Monte Carlo based simulations. These simulations include all physical processes, including events resulting from multiple particles incident on a single pixel, to describe the experimental data accurately. Post-processing of Monte Carlo simulations is done to account for the effects of pile up (multiple hits on a single pixel during one integration time) and non-radiation-induced noise in experiment. The results are compared with experimental data, and demonstrate how direct ionization dominates the cross section, yet fluctuations in dE/dx cause a broad range of energy depositions not addressed by an average LET calculation. An event rate is predicted for a full space proton flux and the dominance of direct ionization is shown and compared to computation using constant LET methods in CREME96. This comparison shows that at lower energies, CREME96 sufficiently predicts the event rate, but at higher energies a high fidelity simulation method is needed to capture the distribution.

This paper presents a SEU hardening approach that uses a dummy collector to reduce charge collection in the main transistor. The dummy collector is obtained using the silicon space between adjacent HBTs. It is obtained without any process modification or area penalty. The simulations are performed for normal and angled strikes. The hardened device shows significant reduction in charge collection due to sharing of diffusive charge collection by the dummy collector. Multiple HBT arrays of regular and hardened HBT are simulated to study the simultaneous charge collection in multiple HBTs. With hardening, charge collection in multiple devices is suppressed considerably for normal and angled strikes as the shared dummy collector collects a large amount of charge.

The radiation tolerance of strained Si/SiGe n-MODFETs is investigated, using 10 keV X-rays, 63 MeV high energy protons, and 4 MeV low energy protons. The effects of radiation exposure on two major device design parameters (LSD and LG) in T-gate Si/SiGe n-MODFETs devices are examined. A strong dependence on source-drain spacing is observed for both the DC and RF characteristics. A drift-diffusion TCAD framework is used for 2-D device simulations. We believe that the low energy protons damage the SiGe/strained-Si/SiGe lattice, leading to partial strain relaxation. The conduction band-offset (CBO) of the strained SiGe/Si heterojunction is lowered leading to higher gate current leakage. The presence of radiation-induced bulk traps in the unrelaxed SiGe layers on the device behavior is also investigated.

The impact of 63.3 MeV proton and 10 keV X-ray irradiation on the DC and AC performance of complementary SiGe HBTs on thick-film SOI is investigated. Proton and X-ray induced changes in the forward and inverse Gummel characteristics, the output characteristics, and avalanche multiplication are reported for both npn and pnp SiGe HBTs, at both room temperature (300 K) and at cryogenic temperatures (down to 30 K). Comparison of room temperature and cryogenic data suggests interface trap formation at two distinct physical locations in the transistors. Experimental data and calibrated TCAD simulations are used to compare the radiation response of both thick-film SOI devices and thin-film SOI SiGe HBTs.

A comprehensive investigation of the performance dependencies of irradiated SiGe precision voltage reference circuits on (1) total ionizing dose (TID), (2) circuit topology, and (3) radiation source is presented. Two different bandgap voltage references were designed using a first-generation (50-GHz) SiGe BiCMOS technology platform, and subsequently exposed to X-rays at doses of 1080 krad(SiO2) and 5400 krad(SiO2). The degradation in circuit performance following X-ray irradiation depends on both the TID level and the chosen circuit topology. Measurement results show that large TID levels can significantly shift the magnitude of the output voltage. Explanations for the observed shifts are provided by utilizing detailed analyses of the two circuit topologies and considering device-to-circuit interactions. The primary factor responsible for the difference in the circuit response before and after irradiation can be attributed to the excess base leakage current in the SiGe HBT. To investigate the impact of radiation source, the circuit topology showing the worst-case degradation from the X-ray experiment was independently exposed to 63-MeV protons at the same effective TID level. A clear source dependence in the circuit response was observed, and possible origins of this behavior are identified.

We present an investigation of the observed variations in the total dose tolerance of the emitter-base spacer and shallow trench isolation oxides in a commercial 200 GHz SiGe HBT technology. Proton, gamma, and X-ray irradiations at varying dose rates are found to produce drastically different degradation signatures at the various oxide interfaces. Extraction and analysis of the radiation-induced excess base current, as well as low-frequency noise, are used to probe the underlying physical mechanisms. Two-dimensional calibrated device simulations are employed to correlate the observed results to the spatial distributions of carrier recombination in forward- and inverse-mode operation for both pre- and post-irradiation levels. Possible explanations of our observations are offered and the implications for hardness assurance testing are discussed

The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both proton-induced single event upset (SEU) and MBU responses have been shown to vary with angle and energy for certain technologies. This work analyzes SEU and MBU in a 130 nm CMOS SRAM in which the single-event response shows a strong dependence on the angle of proton incidence. Current proton testing methods do not account for device orientation relative to the proton beam and, subsequently, error rate prediction assumes no angular dependencies. Proton-induced MBU is expected to increase as integrated circuits continue to scale into the deep sub-micron regime. Consequently, the application of current testing methods will lead to an incorrect prediction of error rates

We compare, for the first time, the effects of 63 MeV protons on 1st generation and 3rd generation SiGe HBTs irradiated at both liquid nitrogen temperature (77 K) and at room temperature (300 K). The 1st generation SiGe HBTs irradiated at 77 K show less degradation than when irradiated at 300 K. Conversely, the 3rd generation SiGe HBTs exhibits an opposite trend, and the devices irradiated at 77 K show enhanced degradation compared to those irradiated at 300 K. The emitter-base spacer regions for these two SiGe technologies are fundamentally different in construction, and apparently are responsible for the observed differences in temperature-dependent radiation response. At practical circuit biases, both SiGe technology generations show only minimal degradation for both at 77 K and 300 K exposure, to Mrad dose levels, and are thus potentially useful for electronics applications requiring simultaneous cryogenic temperature operation and significant total dose radiation exposure

A comprehensive investigation of the effects of proton irradiation on the performance of SiGe BiCMOS precision voltage references intended for extreme environment operational conditions is presented. The voltage reference circuits were designed in two distinct SiGe BiCMOS technology platforms (first generation (50 GHz) and third generation (200 GHz)) in order to investigate the effect of technology scaling. The circuits were irradiated at both room temperature and at 77 K. Measurement results from the experiments indicate that the proton-induced changes in the SiGe bandgap references are minor, even down to cryogenic temperatures, clearly good news for the potential application of SiGe mixed-signal circuits in emerging extreme environments

We present, for the first time, an analysis of the error signatures captured during pulsed laser microprobe testing of high-speed digital SiGe logic circuits. 127-bit shift registers, configured using various circuit level latch hardening schemes and incorporated into the circuit for radiation effects self test serve as the primary test vehicle. Our results indicate significant variations in the observed upset rate as a function of strike location and latch architecture. Error information gathered on the sensitive transistor nodes within the latches and characteristic upset durations agree well with recently reported heavy-ion microprobe data. These results support the growing credibility in using pulsed laser testing as a lower-cost alternative to heavy-ion microprobe analysis of sensitive device and circuit nodes, as well as demonstrate the efficiency of the autonomous detection and error approach for high speed bit-error rate testing. Implications for SEU hardening in SiGe are addressed and circuit-level and device-level Radiation Hardening By Design recommendations are made

X-ray total ionizing dose effects in both fully-depleted and partially-depleted SiGe HBT-on-SOI transistors are investigated at room and at cryogenic temperatures for the first time. Devices irradiated in grounded and forward-active mode configurations exhibit a different behavior depending on the collector doping of the device. The degradation produced by 10 keV x-rays is compared to previously reported 63 MeV proton results on the same fully-depleted SiGe HBT-on-SOI devices, showing decreased degradation for proton irradiation. Both collector and substrate bias are shown to affect the two-dimensional nature of the current flow in these devices, resulting in significant differences in the avalanche multiplication characteristics (hence, breakdown voltage) across temperature

Delayed charge collection from ionizing events outside the deep trench can increase the SEU cross section in deep trench isolation technologies. Microbeam test data and device simulations demonstrate how this adverse effect can be mitigated through substrate engineering techniques. The addition of a heavily doped p-type charge-blocking buried layer in the substrate can reduce the delayed charge collection from events that occur outside the deep trench isolation by almost an order of magnitude, implying an approximately comparable reduction in the SEU cross section

Shift registers featuring radiation-hardening-by-design (RHBD) techniques are realized in IBM 8HP SiGe BiCMOS technology. Both circuit and device-level RHBD techniques are employed to improve the overall SEU immunity of the shift registers. Circuit-level RHBD techniques include dual-interleaving and gated-feedback that achieve SEU mitigation through local latch-level redundancy and correction. In addition, register-level RHBD based on triple-module redundancy (TMR) versions of dual-interleaved and gated-feedback cell shift registers is also realized to gauge the performance improvement offered by TMR. At the device-level, RHBD C-B-E SiGe HBTs with single collector and base contacts and significantly smaller deep trench-enclosed area than standard C-B-E-B-C devices with dual collector and base contacts are used to reduce the upset sensitive area. The SEU performance of these shift registers was then tested using heavy ions and standard bit-error testing methods. The results obtained are compared to the unhardened standard shift register designed with CBEBC SiGe HBTs. The RHBD-enhanced shift registers perform significantly better than the unhardened circuit, with the TMR technique proving very effective in achieving significant SEU immunity

The effect of proton irradiation on operating voltage constraints in SiGe HBTs is investigated for the first time in 120 GHz and 200 GHz SiGe HBTs. A variety of operating bias conditions was examined during irradiation, including terminals grounded, terminals floating, and forward active (FA) bias operation. The excess base current degradation at 5.0/spl times/10/sup 13/ p/cm/sup 2/ was similar in all cases. BV/sub CEO/ and BV/sub CBO/ showed no significant signs of degradation with irradiation. We also investigated for the first time the impact of radiation on SiGe HBTs biased under so-called "unstable" conditions (i.e., operating point instabilities). In the case of unstable bias conditions, device degradation under proton exposure is significantly different than for stable bias, and bias conditions can play a significant role in the damage process, potentially raising issues from a hardness assurance perspective.

We present the results of gamma irradiation on third-generation, 200 GHz SiGe HBTs. Pre- and post-radiation dc figures-of-merit are used to quantify the tolerance of the raised extrinsic base structure to Co-60 gamma rays for varying device geometries. Additionally, the impact of technology scaling on the observed radiation response is addressed through comparisons to second generation, 120 GHz SiGe HBTs. Comparisons to previous proton-induced degradation results in these 200 GHz SiGe HBTs are also made, and indicate that the STI isolation oxide of the device shows increased degradation following Co-60 irradiation. The EB spacer oxide, on the other hand, demonstrates increased susceptibility to proton damage. Low dose rate proton testing was also performed and indicate that although there is a proton dose rate effect present in these devices, it cannot fully explain the observed trends. Similar trends have previously been observed for buried oxides and isolation oxides in several MOS technologies and have been attributed to increased charge yield in these oxides for 1.2 MeV Co-60 gamma rays when compared to 63 MeV protons.

SEE testing at multi-Gbit/s data rates has traditionally involved elaborate high speed test equipment setups for at-speed testing. We demonstrate a generally applicable self test circuit approach implemented in IBM's 5AM SiGe process, and describe its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s. Comparisons of data acquired with FPGA control of the CREST ASIC versus conventional bit error rate test equipment validate the approach. In addition, we describe SEE characteristics of the IBM 5AM process implemented in five variations of the D flip-flop based serial register. Heavy ion SEE data acquired at angles follow the traditional RPP-based analysis approach in one case, but deviate by orders on magnitude in others, even though all circuits are implemented in the same 5AM SiGe HBT process.

We present a new back junction approach for reducing SEU-induced charge collection in SiGe HBTS, and demonstrate its effectiveness in a state-of-the-art 200 GHz SiGe HBT using full 3-D device simulation. An additional n/sup +/ layer is used below the p-type isolation layer to form a back junction. The back junction limits potential funneling to within the p-type layer, which effectively limits the total amount of drift charge collection that is now shared by the collector-to-substrate junction and the back junction. The back junction also cuts off the diffusion charge coming from the substrate, further limiting charge collection by the HBT collector. A thinner p-type "substrate" layer and a better contact to the added n/sup +/ layer are shown to help reduce charge collection by the HBT collector, the sensitive node.

Proton radiation effects in vertical SiGe HBTs fabricated on CMOS-compatible silicon-on-insulator (SOI) are investigated for the first time. Proton irradiation at 63 MeV is found to introduce base leakage current at low base-emitter voltage, delay the onset of Kirk effect at high injection, and increase the frequency response of SiGe HBTs on SOI. The latter two effects are in contrast to those found in conventional bulk SiGe HBTs. Proton irradiation also generates positive fixed oxide and interface charge in the buried oxide, which alters both M-1 and BV/sub CEO/ in the SiGe HBT by modulating the electric field in the collector region.

A Hubble space telescope wide field camera 3 e2v CCD was irradiated while operating at -84/spl deg/C and the dark current studied as a function of temperature while the charge coupled device was warmed to a sequence of temperatures up to a maximum of +30/spl deg/C. The device was then cooled back down to -84/spl deg/ and remeasured. Hot pixel populations were tracked during the warm up and cool down. Hot pixel annealing began below -40/spl deg/C and the anneal process was largely completed by the time the detector reached +20/spl deg/C. There was no apparent sharp annealing temperature. Although a large fraction of the hot pixels fell below the threshold to be counted as a hot pixel, they nevertheless sustained a higher leakage rate than the remaining population. The mechanism for hot pixel annealing is not presently understood. Room temperature irradiations do not adequately characterize the hot pixel distributions for cooled applications.

We present measurements of proton-induced single event transients in ultra-low noise HgCdTe IR detector arrays being developed for space-based astronomy and compare to modeling results.