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Non-TMR SEU-Hardening Techniques for SiGe HBT Shift Registers and Clock Buffers
- Source :
- IEEE Transactions on Nuclear Science. 57:2119-2123
- Publication Year :
- 2010
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2010.
-
Abstract
- We report new results from both broad-beam, heavy-ion and proton experiments for circuit-level RHBD techniques in SiGe digital logic. Redundant circuit elements within the latches are used to significantly reduce single-event upset rates in shift registers and clock paths, without resorting to TMR techniques.
- Subjects :
- Nuclear and High Energy Physics
Materials science
business.industry
Computer science
Heterojunction bipolar transistor
Electrical engineering
Electrical element
Hardware_PERFORMANCEANDRELIABILITY
Clock skew
Upset
Silicon-germanium
chemistry.chemical_compound
Nuclear Energy and Engineering
chemistry
Single event upset
Hardening (metallurgy)
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Optoelectronics
Current-mode logic
Hardware_ARITHMETICANDLOGICSTRUCTURES
Electrical and Electronic Engineering
business
Hardware_LOGICDESIGN
Shift register
Subjects
Details
- ISSN :
- 15581578 and 00189499
- Volume :
- 57
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Nuclear Science
- Accession number :
- edsair.doi.dedup.....0e7e8085f90bd57489183254fe729517