Search

The effects of shallow-trench-isolation-induced mechanical stress on radiation-induced off-state leakage current are reported in 90-nm NMOS devices. The radiation-induced leakage current increases with increasing active device-to-isolation spacing. The leakage current also depends on channel width; narrow devices exhibit less leakage before irradiation, but more after irradiation. These geometrical factors affect the mechanical stress in the device, which impact the dopant diffusion and activation and the charge trapping in the STI oxide. The combined effects of these layout-related phenomena affect the sensitivity to radiation-induced charge. [ABSTRACT FROM AUTHOR]

Radiation-induced dopant passivation is evidenced for the first time in partially-depleted SOI n-channel MOSFETs. Isochronal annealing experiments following 10 Mrad(SiO2) irradiation demonstrate that the neutralization of boron atoms in the NMOSFET body is most pronounced in the 125°C-150°C temperature range. This results in an abrupt decrease of the threshold voltage and the subthreshold swing, due to the transition of the body from partial to full depletion. The SO! four-gate transistor, inherently present in the partially-depleted MOSFET structure, is demonstrated to be a very efficient tool for monitoring dopant neutralization through irradiation and annealing. Radiation-induced dopant passivation has important consequences regarding the reliability of short-channel partially-depleted NMOSFETs. [ABSTRACT FROM AUTHOR]

Total dose effects on silicon on insulator (SOI) UNI BOND wafers are studied via optical second harmonic generation (SHG). This technique is qualitatively compared with the pseudo-MOSFET technique for monitoring charges at the interfaces. optical and electrical methods are combined to separate the contribution of the signal from each interface to the total SHG intensity. Radiation-induced oxide and interface traps increase the interface fields as determined from the SHG signals and the results are compared with electrical measurements. [ABSTRACT FROM AUTHOR]

We evaluate the total-ionizing-dose (TID) responses of InGaAs nMOS fin field-effect transistors (FinFETs) with a modified gate-stack irradiated with 10-keV X-rays under different gate biases. This modified InGaAs nMOS FinFET process shows decreased subthreshold leakage current and increased hysteresis in as-processed devices, and reduced hole trapping in irradiated devices, than first-generation development-stage devices. The reduction in subthreshold leakage current is attributed to changing the buffer layer from GaAs to In0.3Ga0.7As, thereby enhancing the material quality. Both the increased hysteresis in as-processed devices and reduced hole trapping in irradiated devices are attributed primarily to thinning the Al2O3 layer that separates the HfO2 from the InGaAs layers. This facilitates charge exchange with defects at the HfO2/Al2O3 interface and reduces the percentage of radiation-induced holes that are generated in Al2O3 and trapped in HfO2. The removal of a tungsten layer above the TiN gate reduces the interface dose enhancement. [ABSTRACT FROM AUTHOR]

The effects of total-ionizing-dose irradiation are investigated in HfO2/InGaAs quantum-well MOSFETs. Radiation-induced hole trapping is higher for irradiation under positive gate bias than under negative gate bias. Electrical stress-induced electron trapping compensates radiation-induced hole trapping during positive gate-bias irradiation. Stress-induced hole trapping adds to the effects of radiation-induced hole trapping under negative gate bias. Radiation-induced charge trapping increases with the channel length. [ABSTRACT FROM PUBLISHER]

Single and multiple-event upsets in \ HfO_2/\ Hf one transistor, one resistor (1T1R) resistive random access memory (RRAM) structures are modeled dynamically using 3-D technology computer-aided design (TCAD) simulations. A dynamic single-event compact model is presented that allows direct correlation of the ion-generated voltage transient across the RRAM and the change in RRAM resistance. Experiments and modeling demonstrate an exponential relationship between the susceptibility of the RRAM and the applied voltage. Two implementations of the model are also presented including hardening voltage-susceptible resistive memory technologies and the impact of highly scaled access transistors. [ABSTRACT FROM PUBLISHER]

We have investigated the effects of biased and unbiased X-ray irradiation on the subsequent time-dependent dielectric breakdown (TDDB) of 130-nm MOSFETs irradiated up to 1 Mrad(SiO2). We found a small but measurable increase in TDDB lifetime after irradiation at the worst-case irradiation bias. The influence of radiation bias on subsequent TDDB is more significant in the PMOSFETs than the NMOSFETs. The increased TDDB lifetime and the irradiation-bias dependence are attributed to the influence of radiation-induced traps on the stressing current during the reliability testing. [ABSTRACT FROM AUTHOR]

The effects of gate length and drain bias on the off-state drain leakage current of irradiated fully-depleted SOI n-channel MOSFETs are reported. The experimental results are interpreted using a model based on the combined effects of band-to-band tunneling (BBT) and the trapped charge in the buried oxide. For negative gate-source voltages, the drain leakage current increases with the drain voltage because the electric field in the gate-to-drain overlap region is increasing. The off-state current in these devices increases with total ionizing dose due to oxide trapped charge build up in the buried oxide, enhanced by the BBT mechanism. The experimental data show that these effects are more significant for devices with shorter gate-lengths. Simulation results suggest that the BBT-generated holes are more likely to drift all the way from the drain to the source in shorter devices, enhancing the drain leakage current, while they tend to tunnel across the gate oxide in longer devices. [ABSTRACT FROM PUBLISHER]

Radiation induced charge trapping in ultrathin HfO2-based n-channel MOSFETs is characterized as a function of dielectric thickness and irradiation bias following exposure to 10 keV X-rays and/or constant voltage stress. Positive and negative oxide-trap charges are observed, depending on irradiation and bias stress conditions. No significant interface-trap buildup is found in these devices under these irradiation and stress conditions. Enhanced oxide-charge trapping occurs in some cases for simultaneous application of constant voltage stress and irradiation, relative to either type of stress applied separately. Room temperature annealing at positive bias after irradiation of transistors with thicker gate dielectric films leads to positive oxide-trapped charge annihilation and/or neutralization in these devices, and net electron trapping. The oxide thickness dependence of the radiation response confirms the extreme radiation tolerance of thin HfO2 dielectric layers of relevance to device applications, and suggests that hole traps in the thicker layers are located in the bulk of the dielectric. A revised methodology is developed to estimate the net effective charge trapping efficiency, fot, for high-κ dielectric films. As a result, estimates of fot for Hf silicate capacitors and Al2O3 transistors in previous work are reduced by up to 18%. [ABSTRACT FROM AUTHOR]

Modeling systems containing commercial-off-the-shelf (COTS) parts exposed to total ionizing dose (TID) are difficult due to large parameter variability in the parts as a function of dose. This article provides a rapid approach to predicting the system performance as a function of TID given these parameter variations. A radiation-aware model for an IRF510 power MOSFET is generated from a small population of irradiated parts, and this model is randomly sampled for each of the transistors in an example circuit, utilizing the degraded parameters. The simulations predict the circuit operating in one of three distinct modes, with circuits containing large variability in parts failing in some instances. The simulated data are compared to experimental data using a method that involves interchanging irradiated parts in a socketed printed circuit board (PCB) to produce a large number of different combinations of test circuits. The simulated data correctly predicted the circuit modes of operation, and the part-swapping technique eliminated the cost of building many test boards. [ABSTRACT FROM AUTHOR]

Total-ionizing-dose (TID) effects are compared in 1) conventional high-temperature processed planar fully-depleted silicon-on-insulator (FD-SOI) p-channel MOSFETs, 2) 3-D sequentially integrated (3DSI) FD-SOI MOSFETs in the bottom layer with additional thermal budget and process flows due to the creation of the top layer, and 3) 3DSI low-temperature-processed FD-SOI MOSFETs in the top layer. When irradiated under worst case negative bias, 3DSI bottom-isolated transistors show significantly enhanced charge trapping and transconductance degradation than planar devices. The enhanced degradation for bottom-isolated devices is attributed primarily to increased interface- and border-trap formation at the buried oxide (BOX)/Si interface and/or lateral charge nonuniformities in the BOX. The radiation-induced transconductance degradation in top-isolated devices is attributed to the increased resistance of the portion of the channel that underlies the source/drain spacers. [ABSTRACT FROM AUTHOR]

The total-ionizing-dose (TID) response of indium gallium arsenide (InGaAs) MOSFETs with Al2O3 gate dielectrics and several channel lengths is evaluated under different biases. DC static characteristics show large negative threshold voltage Vth shifts and subthreshold stretchout (SS), indicating net positive charge trapping in the gate oxide and generation of the interface and border traps. Hysteresis and Id – Vgs measurements from cryogenic to high temperatures show the important role of defects in the Al2O3 gate dielectric to the TID response. Radiation-induced-hole trapping is attributed to oxygen vacancies in the Al2O3. The relatively large hysteresis in these devices is attributed primarily to dangling Al bonds in the near-interfacial Al2O3. Analysis of the temperature dependence of Vth and SS suggests that the rate at which electrons leave the Al2O3 during a positive-to-negative gate-bias sweep is higher than the rate at which they enter during a negative-to-positive gate-bias sweep. [ABSTRACT FROM AUTHOR]

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust. [ABSTRACT FROM AUTHOR]

Variability of the solar energetic particle environment is investigated for single-event burnout (SEB) reliability of silicon carbide power metal-oxide-semiconductor field-effect transistors. A probabilistic assessment of failure evaluates the benefits of derating voltage, shielding, and mission length. The Prediction of Solar particle Yields for Characterizing Integrating Circuits code is used to calculate a cumulative density function for the fluence of the environment. The lethal ion method is then used to determine what proportion of the environment will cause SEB. The operating voltage determines the lowest linear energy transfer (LET) particle that will cause SEB, and that should be included in the environment distribution. The shielding and mission length also determines the final environment distribution of the mission fluence. When the critical LET for a device is relatively low for the expected mission environment, the method in this article can calculate the probability of failure from a destructive event. The calculated probability of failure enables the consideration of part use outside the safe operating area, especially when derating the operating voltage would eliminate the technology advantage of the part. [ABSTRACT FROM AUTHOR]

The onset of ion-induced reverse leakage current in SiC Schottky diodes is shown to depend on material properties, ion linear energy transfer (LET), and bias during irradiation, but not the voltage rating of the parts. This is demonstrated experimentally for devices from multiple manufacturers with voltage ratings from 600 to 1700 V. Using a device with a higher breakdown voltage than required in the application does not provide increased robustness related to leakage current degradation, compared to using a device with a lower voltage rating. [ABSTRACT FROM AUTHOR]

A two-photon absorption technique is used to understand the mechanisms of single-event effects (SEEs) in silicon carbide power metal–oxide–field-effect transistors (MOSFETs) and power junction barrier Schottky diodes. The MOSFETs and diodes have similar structures enabling the identification of effects associated specifically with the parasitic bipolar structure that is present in the MOSFETs, but not the diodes. The collected charge in the diodes varies only with laser depth, whereas it varies with depth and lateral position in the MOSFETs. Optical simulations demonstrate that the variations in collected charge observed are from the semiconductor device structure and not from metal/passivation-induced reflection. The difference in the spatial dependence of collected charge between the MOSFET and diode is explained by bipolar amplification of the charge carriers in the MOSFETs. Technology computer-aided design (TCAD) device simulations extend this analysis to heavy-ion-induced charge collection. In addition, there is discussion comparing this analysis with experimental results from prior works that show enhanced charge collection resulting from heavy-ion irradiation. [ABSTRACT FROM AUTHOR]

Heavy ion-induced single-event burnout (SEB) is investigated in high-voltage silicon carbide power MOSFETs. Experimental data for 1200-V SiC power MOSFETs show a significant decrease in SEB onset voltage for particle linear energy transfers greater than 10 MeV/cm2/mg, above which the SEB threshold voltage is nearly constant at half of the rated maximum operating voltage for these devices. TCAD simulations show a parasitic bipolar junction transistor turn-on mechanism, which drives the avalanching of carriers and leads to runaway drain current, resulting in SEB. [ABSTRACT FROM AUTHOR]

The radiation response of complementary metal–oxide–semiconductor (CMOS) gate oxides is typically insensitive to true dose-rate effects, but damage in deep-sub-micrometer technologies is dominated by ionization mechanisms in thick isolation oxides surrounding the transistors. Recent results in 65-nm FETs demonstrated that performance degradation in ultrahigh total ionizing dose (TID) experiments is due to defects in the isolation shallow trench isolation oxide or in the materials composing the lightly doped drain spacers. These insulators are thick, deposited, and crossed by a low electric field, characteristics similar to those typical of passivation oxides in linear bipolar technologies for which an enhanced low-dose-rate sensitivity (ELDRS) has been observed and systematically studied. We report in this paper the clear evidence of a dose-rate sensitivity of the TID-induced damage in both 130- and 65-nm CMOS technologies exposed to different radiation sources (X-rays and $\gamma $ -rays from a 60Co source). This sensitivity is attributed to mechanisms similar to those explaining ELDRS in bipolar devices and represents a significant challenge to the definition of a qualification procedure for circuits to be used in extreme radiation environments. [ABSTRACT FROM AUTHOR]

We demonstrate the utility of focused, pulsed X-rays for investigating localized total ionizing dose effects in bipolar analog integrated circuits. Using the LM139 comparator as a test vehicle, we show how the technique can be used to identify the sources of degradation as a result of irradiating different transistors of the device and how this impacts the input bias current, input offset voltage, and output voltage. The 2-D mapping of the sensitive regions of transistors is presented, where the results of localized irradiation impact the monitored operational parameters. [ABSTRACT FROM PUBLISHER]

A tunable wavelength laser system and high-resolution transient capture system are introduced to characterize transients in high-mobility MOSFETs. The experimental configuration enables resolution of fast transient signals and new understanding of charge collection mechanisms. The channel layer is critical in the charge collection process for the InGaAs FinFETs examined here. The transient current mainly comes from the channel current, due to shunt effects and parasitic bipolar effects, instead of the junction collection. The charge amplification factor is found to be as high as 14, which makes this technology relatively sensitive to transient radiation. The peak current is inversely proportional to the device gate length. Simulations show that the parasitic bipolar effect is due to source-to-channel barrier lowering caused by hole accumulation in the source and channel. Charge deposited in the channel causes prompt current, while charge deposited below the channel causes delayed and slow current. [ABSTRACT FROM PUBLISHER]

We have characterized the total ionizing dose response of strained Ge p MOS FinFETs built on bulk Si using a fin replacement process. Devices irradiated to 1.0 Mrad(SiO2) show minimal transconductance degradation (less than 5%), very small \text {V}_{th} shifts (less than 40 mV in magnitude) and very little ON/OFF current ratio degradation (<5%), and only modest variation in radiation response with transistor geometry (typically less than normal part-to-part variation). Both before and after irradiation, the performance of these strained Ge p$ MOS FinFETs is far superior to that of past generations of planar Ge $p$ MOS devices. These improved properties result from significant improvements in processing technology, as well as the enhanced gate control provided by the strained Ge FinFET technology. [ABSTRACT FROM PUBLISHER]

Charge collection mechanisms are investigated in surface channel GaAs MOSFETs under broadbeam heavy ion irradiation and pulsed two-photon-absorption laser irradiation. The large barrier between the gate dielectric and GaAs eliminates gate conduction current, but there is significant gate displacement current. Charge enhancement occurs because radiation-generated holes accumulate in the substrate, which increases the local electrostatic potential. The increased potential enhances the source-to-drain current, resulting in excess collected charge. The collected charge increases significantly with gate bias, due to the long tails of the charge waveforms that occur for higher gate bias. The collected charge increases with increasing drain bias. [ABSTRACT FROM PUBLISHER]

Single-event transients in SiGe MOS devices with ultrathin quantum well channels have been shown in previous work to exhibit opposite polarities for source and drain strikes. This work reports polarity reversal in similar devices with thick Ge channels due to the favorability of prompt hole collection by either the source or drain region, depending on the strike location. A slower charge-collection mechanism is also present due to the n-well/p-substrate structure, which allows ion-generated carriers from the substrate to flood the body of the device. [ABSTRACT FROM PUBLISHER]

Simulations of the SEB hardness of power MOSFETs are carried out with an experimentally calibrated structure. The effects of incorporating high permittivity gate dielectric layers and increasing channel doping concentration are investigated. The simulation results indicate that high-k dielectrics and high channel doping are promising methods to achieve SEB-hardened power MOSFETs. This offers a potential path to power MOSFETs that are resistant to SEB with thinner, more radiation-tolerant gate dielectrics. [ABSTRACT FROM PUBLISHER]

A new geometry-aware single-event enabled compact model for sub-50 nm partially depleted silicon-on-insulator MOSFETs is presented. The model extends the bias-dependent single-event modeling methods with an integrated parasitic BJT using the SPICE Gummel Poon equations and parameters derived from the manufacturer’s process design kit, physical layout, and technology information. The model compares well with TCAD and test data. [ABSTRACT FROM AUTHOR]

The single-event-transient response of InGaAs MOSFETs exposed to heavy-ion and laser irradiations is investigated. The large barrier between the gate oxide and semiconductor regions effectively suppresses the gate transients compared with other types of III-V FETs. After the initial radiation-induced pulse, electrons and holes flood into the channel region at short time. The electrons are collected efficiently at the drain. The slower moving holes accumulate in the channel and source access region and modulate the source-channel barrier, which provides a pathway for transient source-to-drain current lasting for a few nanoseconds. The peak drain transient current reaches its maximum when the gate bias is near threshold and decreases considerably toward inversion and slightly toward depletion and accumulation. Two-dimensional TCAD simulations are used to understand the charge collection mechanisms. [ABSTRACT FROM PUBLISHER]

The total-dose radiation tolerance of 32-nm nFETs is investigated. nFETs built in 32-nm RF-CMOS-on-SOI technology with high-k dielectrics show increased off-state leakage current and electron trapping in the gate oxide. The impact of CMOS-on-SOI technology scaling (from 65-nm to 32-nm) on the total-dose radiation tolerance and hot-carrier reliability (HCR) is investigated through both experiments and supporting TCAD simulations. The 32-nm nFETs exhibit less total-dose degradation compared to 45-nm nFETs. However, the hot-carrier degradation increases as the technology scales. An interplay of electric-field in the gate oxide and impact ionization in the channel region is responsible for the observed differences in the degradation mechanisms for the three technologies. [ABSTRACT FROM AUTHOR]

Irradiated Ge pMOSFETs have been characterized via charge pumping (ICP) and 1/f noise. The noise increases much more with irradiation than does ICP for devices with eight Si monolayers at the interface, while devices with five Si monolayers and lower halo implantation dose exhibit comparable increases in noise and ICP with irradiation. These results suggest that border traps in the HfO2 affect the noise more than interface traps, and that devices with eight Si monolayers have a higher border-trap density than devices with five Si monolayers. Noise measurements as a function of gate voltage show that the border trap density increases significantly toward the Ge valence band edge, while three-level charge pumping reveals an interface trap density that increases slightly toward midgap. [ABSTRACT FROM AUTHOR]

The total ionizing dose response of triple-gate MOSFETs is investigated for various fin widths and bias conditions. Experiments and simulations are used to analyze the buildup of trapped charge in the buried oxide and its impact on the threshold-voltage shift and subthreshold-slope degradation. The higher total-dose tolerance of multiple-gate FinFETs with narrow fins is attributed to lateral gate control over the electrostatic potential in the body and especially at the Si fin/BOX interface. It is demonstrated that ON-state irradiation is the worst-case bias configuration for triple-gate MOSFETs through extensive experimental analysis. [ABSTRACT FROM PUBLISHER]

A new methodology of prediction for SEU is proposed based on SET modeling. The modeling of multi-node charge collection is performed using the ADDICT model for predicting single event transients and upsets in bulk transistors and SRAMs down to 65 nm. The predicted single event upset cross sections agree well with experimental data for SRAMs. [ABSTRACT FROM AUTHOR]

The irradiation and annealing responses of Ge pMOSFETs have been investigated under transmission gate bias. Both the radiation-induced charge trapping and the low frequency (1/ f ) noise increase with total ionizing dose and decrease with annealing time. The smallest increases in noise after irradiation are observed for Ge pMOSFETs with the lowest halo implantation doses. The smallest increases in oxide and interface trap charge densities are obtained for devices with eight monolayers of Si at the interface, as compared to devices with five Si monolayers. [ABSTRACT FROM AUTHOR]

The irradiation and annealing responses of Ge pMOSFETs are investigated as a function of device processing. Transmission gate bias is found to be the worst-case irradiation bias condition. Junction leakage increases with total dose, which leads to a decrease in the I on /I off ratio. The I on /I off ratio recovers with room temperature annealing. Both band-to-band tunneling and trap-assisted tunneling contribute to the observed leakage. Device leakage before and after irradiation is found to be sensitive to halo implant dose and the number of Si monolayers at the Ge/insulator interface. Interface trap densities and body leakage also increase with dose and decrease with annealing. [ABSTRACT FROM AUTHOR]

We have characterized the total ionizing dose (TID) response of SOI FinFETs, fabricated in two different technologies, operated in 1T-DRAM mode, one with poly-crystalline Si gates and a SiO2 gate dielectric, and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage (GIDL) programming methods. 1T-DRAM cells programmed with back-gate pulses are quite sensitive to total ionizing dose radiation, with the memory sensing margin and retention time decreasing significantly with increasing dose. In contrast, the sensing margin and retention time show high tolerance to total ionizing dose irradiation when the 1T-DRAM cells are programmed via GIDL. The sensing margin increases significantly with decreasing gate length for 1T-DRAM cells programmed via GIDL. We conclude that capacitor-less 1T-DRAMs programmed via GIDL are strong candidates for embedded memory applications for ultimately scaled CMOS devices in high-TID applications. [ABSTRACT FROM AUTHOR]

The total-dose response of Ge p-MOSFETs and p+-n junction diodes is reported for devices fabricated with several process variations. Radiation-induced reduction of the on-off current ratio increases with halo-doping density. Increasing the number of Si monolayers at the substrate/dielectric interface reduces total-dose sensitivity for p-MOSFETs. Reduced mobility degradation is observed after irradiation for devices with a higher number of Si monolayers. The radiation-induced increase in junction leakage is related to the increasing perimeter component of the leakage current. MOSFETs with a higher number of Si monolayers at the dielectric/substrate interface also have reduced perimeter leakage current. Diode leakage current increases with increasing halo-doping density. [ABSTRACT FROM AUTHOR]

Silicon-carbide-based MOS capacitors were formed on either 3C (epitaxial on Si) or 4H substrates and using SiO2 gate dielectrics both with and without interfacial nitrogen. The charge trapping properties of these structures were examined after expo- sure to ionizing radiation. In all cases interfacial nitrogen results in improved trap density and increased oxide charge trapping. For equivalent nitrogen content, 3C-based devices exhibit more charge trapping than the 4H-based equivalents. [ABSTRACT FROM AUTHOR]

Radiation-induced charge trapping and mobility degradation are measured on uniaxially stressed HfO2-based nMOSFETs. Controlled external mechanical stress is applied via a four-point bending jig while the samples are irradiated using 10-keV X-rays. Positive charge trapping is observed for unstressed devices, and for devices irradiated under both compressive and tensile stress. Reduced trapped charge is measured as the uniaxial stress level increases. These results suggest that the increased stress leads to a reconfiguration of defect microstructure, as compared to the unstressed devices. The reconfiguration consists of changes in bond lengths and angles and a corresponding change in trap energy levels, which can (1) reduce the probability that a defect can capture holes, (2) increase the probability for electron and trapped-hole recombination, and/or (3) increase the mobility of the transporting holes in the oxides of the devices that are irradiated under stress. These results show that increased mechanical stress in high-k dielectrics does not degrade their radiation hardness. We also observe that the post-irradiation channel mobility degrades less in uniaxially stressed devices than unstressed devices. [ABSTRACT FROM PUBLISHER]

This paper evaluates the radiation responses of 2.5 V 110 transistors and regular-threshold MOSFETs from a 90 nm commercial bulk CMOS technology. The data obtained 60Co ionizing radiation experiments indicate enhanced TID susceptibility in 110 devices and circuits, which is attributed to the p-type body doping. A quantitative model is used to analyze the effects of doping and oxide trapped charge buildup along the sidewall of the shallow trench isolation oxide. These effects are captured in the general electrostatic equation for surface potential, which can be correlated to off-state leakage current. Device simulations are used in concert with experimental measurements and the analytical model to provide physical insight into the radiation response of each device type. [ABSTRACT FROM AUTHOR]

Proton and X-ray irradiation effects are investigated in 0.35 µm conventional, annular, and ringed-source radiation-hardening-by-design (RHBD) CMOS devices. Transistors were irradiated with protons at both 300 K and 77 K. Radiation-induced oxide trapped charges in the shallow trench isolation (STI) oxide deplete the p-substrate and effectively shunt the source and drain, inducing off-state leakage. Without the STI, RHBD nFETs exhibit no radiation-induced off-state shunt leakage currents for devices irradiated at both 300 K and 77 K. Conventional 0.35 µm pFETs were not degraded by proton irradiation, since the leakage path cannot be formed in the n-well. A simple CMOS logic inverter shows no degradation in output voltage after proton irradiation for all tested temperature and bias conditions. More advanced 130 nm node nFETs show less TID sensitivity to STI leakage due possibly to the smaller physical STI volume and/or additional doping located on the STI sidewall. [ABSTRACT FROM AUTHOR]

Total ionizing dose effects on fully-depleted (FD) silicon-on-insulator (SOI) transistors are studied when the devices are operated in single gate (SG) and double gate (DG) mode. The devices exhibit superiority in mobility and drain current when op- erated in DG mode compared to SG mode. Moreover, the dc characteristics of DG operated device are less vulnerable to total dose radiation induced damage. In particular, radiation-induced interface traps have less electrical effect in DG mode operation. [ABSTRACT FROM AUTHOR]