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The parasitic effects of on-chip interconnections on power-efficient CMOS radio-frequency integrated circuits (RF ICs) are studied. Findings highlight the effect of metal layer resistivity and layout parasitics on an RF power amplifier (PA) and a low-noise amplifier (LNA).

Two complementary structures of p-i-n and n-i-p [In.sub.0.10][Ga.sub.0.90]Sb diodes are grown on a metamorphic layer of partially relaxed [In.sub.0.15][Ga.sub.0.85]Sb on GaSb substrates and postgrowth analysis has shown the device-layer composition estimated from in-plane lattice constant calculations. The metamorphic growth method is used for the growth of pseudosubstrates of arbitrary alloy compositions containing the antimonides that can be incorporated into novel midinfrared detectors and lasers.

Avalanche photodiodes (APDs) of different sizes and their driving circuits are fabricated in a commercial 0.18 [micro]m CMOS technology. These APDs have displayed very good avalanche breakdown characteristics and they have improved the fill factor along with the speed of the pixel.

The fabrication and analysis of an active pixel sensor (APS) in d 0.18[mu]m technology is discussed. The proposed pixel seems to offer higher sensitivity at lower levels of light.

Compact modeling of high-frequency (HF) noise sources of MOSFETs is presented, and analytical expressions for MOSFETs noise parameters are developed. Limitations of commonly used noise models in predicting HF noise parameters of MOSFETs are examined and methods to overcome these limitations are suggested.

Developments in compact-modeling principles and solutions for nanoscale double-gate (DG) and gate-all-around (GAA) MOSFETs are presented and reviewed. Techniques are presented to extend these compact models to the high-frequency regime and to study the main high-frequency parameters and characteristics such as noise.

The impact of octyltrichlorosilane (OTS) on the capacitance characteristics of metal-polymer-oxide-silicon (MPOS) structure was investigated. The surface modification of gate oxide is found to improve the carrier enhancement in the active polymer layer of MPOS.

Accurate modeling and efficient parameter extraction of a scalable lumped-element model for n-well meander-line resistors that are suitable for radio frequency integrated circuit (RFIC) applications are presented. It is concluded that the scalable model, with its model parameters can be easily implemented in a subcircuit in SPICE or SpectreRF, making this good physical model for the RF circdcouit designer.

High-frequency (HF) modeling of MOSFET's for radio-frequency (RF) integrated circuit (IC) design is discussed. The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model.

A model is presented to investigate the frequency response of waveguide (WG) p-i-n photodetectors (PDs) is presented. The effect of WG geometry on the bandwidth-quantum efficiency product is analyzed and some results on the optimum design of a WG p-i-n PD for maximum bandwidth-quantum efficiency product are tabulated.

An accurate model for the time response of the resonant cavity enhanced photodetectors (RCE-PDs), which incorporates the effects of their parasitics, is presented. Studies reveal that the functioning of the photodetector can be improved with an external inductor, as it counterbalances a few degradations caused by capacitive parasitics.

A conceptual physics-based model of the waveguide separated absorption charge multiplication avalanche photodetector (WG-SACM-APD) is presented. Findings derived from the circuit model of the WG-SACM-APD are compared with published experimental findings and excellent agreement is observded.d

Simple analytical expression for MOSFETs noise parameters are prepared and verified based on the analytical modeling of MOSFETs channel noise and are found to be useful for circuit design purposes. It is revealed that including induced gate noise in the modeling of MOSFETs noise parameters causes ~5% improvement in the accuracy of the simple expressions given.

Electrical characteristics of two polymer thin-film transistors (TFTs) fabricated by spin-coating of P3HDT and P3HT are investigated. Higher field-effect mobility, a lower off current, a lower inverse subthreshold slope and a larger on current ratio is demonstrated by experimental results from the TFTs based on P3HDT.

Effects of hot carrier stress on fully integrated negative resistance LC-tank CMOS oscillators are examined and reported.

A physical model of the Resonant Cavity Enhanced-Separated Absorption Graded Charge Multiplication-Avalanche Photodetector (RCE-SAGCM-APD) is presented.

The development of a new model for the avalanche build-up of carriers in an avalanche photodiode (APD) including the dead-space effect is described. This model is useful for understanding the frequency response of a resonant-cavity-enhanced (RCE) separate absorption, grading, charge and multiplication (SAGCM) avalanche photodiode (APD).

A new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs is presented. Hot electron effect and the noise contributed from the velocity saturation region are also discussed.

Evidence of the low-frequency noise in high-speed polysilicon emitter bipolar junction transistors (BJTs) originating from generation-recombination (g-r) centers is presented, accompanied by a new model. It is shown that BJTs with large emitter areas id proportional to 1/f, and in contrast, the noise spectrum for BJTs with submicron A(sub E) showed a strong variation from 1/f-dependence, due to presence of several g-r centers.

It is shown that the forward body biasing improves the low-frequency noise performance of the p-channel metal-oxide semiconductor (PMOS) transistors with a certain value. Forward body biasing is also preferred for analog designs, low supply voltage and low power, low noise circuits.

The high-frequency AC and noise modeling of MOSFETs for radio frequency integrated circuit design is discussed. Several noise models including the radio frequency (RF) model are examined, and it is shown that the radio frequency (RF) model can predict the channel thermal noise better than the other models.

The low frequency noise in rectifier diodes in the breakdown region is investigated as a function of the reverse current. The results showed that two processes balance in the diode breakdown, that is, impact ionization, and microplasma switching and conducting.

A scalable, physically based, lumped element model was presented that accurately models thin film meander-line resistors at microwave frequencies fabricated in a silicon technology process. The scalable model presented has been verified for various structure sizes.

Presentation of an extraction method to obtain the induced gate noise, channel noise and their cross correlation in submicron MOSFETs directly from scattering and RF noise measurements was given. The elements used for the extraction procedure of RF noise model are described.

Low-frequency noise (LFN) properties of field-effect transistor s (FET) that rely on polymers as substrate materials are examined. Explanation is provided in terms of nonstationary mobility in the semiconducting polymer.

Optoelectronic integrated circuit photoreceiver design is discussed.

The cryogenic self heating of integrated Si devices is described.

An examination into the current bias-dependence of low-frequency noise spectra in single growth planar separate absorption, charge, multiplication and grading APDs is reported.

The low-frequency noise in several MOSFETs subjected to high-energy proton radiation has been measured. The MOSFETs are typical of those found in the output stage of CCD cameras aboard artificial satellites. They are lightly-doped drain n-type buried-channel devices with aspect ratios between four and six. Results show radiation increased the low-frequency noise of MOSFETs. The presence of bulk trapping states indicate that noise is a generation-recombination phenomenon. The noise is negligible at the operating temperature of the CCD camera but increases at room temperature.

The fabrication of a gate-controlled lateral PNP transistor having four electrodes, namely collector, base, emitter and gate, uses BiCMOS technology. The presence of internal hybrid device features of a surface PMOS and a bulk lateral PNP in parallel impart unique large signal DC characteristics to this transistor. This device helps in building of functional analog circuits such as a variable-gain amplifier and a mixer circuit. The device in conjunction with other digital and analog signal processing circuits provides applications in portable wireless communication systems.

An analytical model accurately simulates the propagation of defects from the sub-spacer region to the gate-overlapped LDD region in NMOSFETs. The correlation between increasing barrier height and increasing drain parasitic resistance to electron implantation provides a simulation framework involving negatively charged oxide traps in the gate-edge/spacer oxide region. The early mode of the two-stage hot-carrier degradation is characterized by a fast degradation of the linear transconductance and a reduction in the substrate current.

The floating gate technique, and the forward and reverse saturation I(sub DS) against V(sub GS) characteristics describe the nature of an early hot-carrier degradation in an LDD NMOSFET. The early mode influences the forward and reverse saturation I(sub DS) versus V(sub GS). The reduction in the peak substrate current with the floating gate cycles and simulations help in the location and quantification of the damage at the edge of the gate. These observations are useful in qualifying the LDD structure.

A non-destructive method accurately derives two characteristic parameters, namely multiple layer thickness and the integrated areal charge density, in separate absorption, grading, charge, and multiplication InP/InGaAs avalanche photodiodes. The technique accounts for systematic uncertainties due to the neglect of ionization in the absorption and charge layers, and the variation in ionization rates. The method uses breakdown and punchthrough voltages from DC photocurrent measurements. Error analysis determines the exact uncertainty of the two parameters.

Breakdown voltage (Vbr) in separate absorption, grading, charge, and multiplication (SAGCM) InP/InGaAs avalanche photodiodes is, nearly, a linear function of temperature. The temperature coefficient is between 0.13 and 0.16 V/deg C. At breakdown, electric field in multiplication layer is a linear function of temperature. A model is prepared to demonstrate these findings. There is good agreement between theoretical and experimental predictions.

The effect of drain-induced barrier lowering (DIBL) is studied in short-channel, n-channel metal oxide semiconductor devices at 300 and 77 K. Experiments show that the DIBL is enhanced when the channel length (L) is more than 1.2 micrometer and less than 0.6 micrometer but deteriorates when 0.6 < L < 1.2 micrometer. Numerical simulations with the Minima software provide an explanation for the phenomena.

A method, based on an accurate formulation and measurement of ac conductances with respect to gate terminal of an MOS transistor in saturation, to extract asymmetry in source and drain parasitic resistances of a MOSFET, is given. It shows asymmetry arises due to faulty layout, processing relate problems and hot-carrier stressing.