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This paper describes the clock distribution and synchronization network for a 64 bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40 nm CMOS technology and operates at 3.0 GHz. The system PLL has a measured rms jitter ${ 1 ps and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the clock distribution uses both CML and CMOS circuits to minimize period jitter and nominally achieves ${ 0.8 ps/mV $\,\vert\,$ rms and ${ 9 ps of period jitter and skew, respectively. By using local Duty Cycle Adjustment circuits in each core to properly offset the clock duty cycle and ease timing critical paths, the processor performance improves by more than 5%. A simple probing circuit for high speed clock measurements can be used to monitor the high frequency excursions of the internal supply to counteract any timing violation that could occur. Finally an enhanced latch, which improves MTBF by up to 5 orders of magnitude and thus is suited for high speed synchronization operations, is proposed.

Timing compensation between the clock period and datapath delay in the presence of resonant supply noise has drawn a great deal of attention from the circuit design community. This effect, which is often referred to as the clock data compensation effect, manifests itself as an increase in maximum operating frequency for high performance microprocessors. In this work, we propose an adaptive phase-shifting PLL that can achieve optimal clock data compensation by digitally programming the supply noise sensitivity and the phase shift of the PLL clock period. Measurement results from a 1.2 V, 65 nm test chip demonstrate a 3.4-7.3% improvement in the maximum operating frequency across different clock distribution designs and resonant frequencies. A mathematical framework for simulating the performance of the adaptive phase-shifting PLL is presented for better insight on how the proposed PLL performs when used in different clock network configurations. In addition, the impact of the proposed technique on PLL stability as well as its effectiveness in a 32 nm process has been explored.

A phase-locked loop (PLL) for analog video RGB signal acquisition interface requires precise clock generation from a very noisy and low-frequency horizontal synchronization signal (HSYNC). In such applications, the frequency multiplication ratio is always larger than 800 and can be up to over 2600. The output pixel clock has to be phase aligned to the HSYNC. Otherwise, the displayed image will become blurry. A fast phase tracking all-digital PLL (ADPLL) for video pixel clock generation in a 65 nm CMOS technology is presented in this paper. In the proposed ADPLL, the digital loop filter eliminates the reference clock jitter effects and then the period jitter of the output pixel clock can be reduced. A time-to-digital converter (TDC) and a delta-sigma modulator (DSM) are used to perform the fast phase tracking, and the tracking jitter is controlled at less than one-third of the output pixel clock period. As compared to prior studies, the proposed ADPLL does not require an extra external oscillator to overcome the reference clock jitter effects. Thus, it has a small chip area and low power consumption, and is well-suited to video pixel clock generation applications in 65 nm CMOS process.

Active deskewing is an important technique for managing variability in clock distributions but introduces latency and power-supply-noise sensitivity into the resulting networks. In this paper, an adaptively deskewed resonant clock network, based on an injection-locked distributed differential oscillator, is described, in which the delay lines required for deskewing are incorporated into the injection-lock source, dramatically improving jitter immunity. A power management system based on automatic amplitude control of the resonant grid further enhances energy efficiency. A prototype system operates at a nominal 2-GHz frequency in a 0.18 mum technology with on-chip jitter and skew measurement circuits and with more than 25 pF/mm2 of clock loading.

Resonant clock distributions have the potential to save power by recycling energy from cycle-to-cycle while at the same time improving performance by reducing the clock distribution latency and filtering out non-periodic noise. While these features have been successfully demonstrated in several small-scale experiments, there remained a number of concerns about whether these techniques would scale to a product application. By modifying the Cell broadband engine processor to incorporate a large resonant global clock network, power savings with full functionality is demonstrated over a 20% range in clock frequencies, and a 6-8 Watt power savings at 4 GHz. This was achieved by changing one wiring level and adding an additional thick copper level to create inductors and capacitors.

A compact wireless clock distribution system with an external planar array antenna which can provide phase and amplitude distributions suitable for synchronizing circuits over a 35-mm diameter circular area at 3 GHz is proposed. The computer systems using this wireless clock distribution can have a comparable form factor as systems using a conventional clock network. The system is composed of a transmitter with an off-chip antenna, and multiple clock receivers with on-chip antennas distributed over an integrated circuit or over multiple ICs. The transmitter, which was fabricated in a 130-nm CMOS process, generates a 17-GHz clock signal which is periodically amplitude-modulated in order to initialize all of the receivers' clock dividers to the same clock phase. Besides increasing the synchronization area, this wireless approach effectively eliminates the dispersion problem in conventional clock networks. The experimental results presented show the feasibility and potential benefits of the wireless clock distribution system using an external antenna.

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-mum CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of plusmn6.6 ps at 1.3 GHz

This paper presents a distributed differential oscillator global clock network where the clock capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude and clock phase are both uniform across the entire global distribution, making this design scalable and compatible with existing local clocking methodologies. The resonant network, combined with phase averaging of the distributed oscillator, provides high immunity to process-, voltage-, and temperature-variation-induced timing uncertainty. Measurement results from a prototype design implemented in a 0.18-mum CMOS technology show almost an order of magnitude less jitter and power than a traditional tree-driven grid global clock distribution. On-chip measurement circuits are used to characterize the jitter on the test chip, while a simulation model is used to examine skew and higher-order resonances in the resonant clock network

An Itanium Architecture microprocessor in 90-nm CMOS with 1.7B transistors implements a dynamically-variable-frequency clock system. Variable frequency clocks support a power management scheme which maximizes processor performance within a configured power envelope. Core supply voltage and clock frequency are modulated dynamically in order to remain within the power envelope. The Foxton controller and dynamically-variable clock system reside on die while the variable voltage regulator and power measurement resistors reside off chip. In addition, high-bandwidth frequency adjustment allows the clock period to adapt during on-die supply transients, allowing higher frequency processor operation during transients than possible with a single-frequency clock system.

This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns.

The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm/sup 2/. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global clock distribution, local clocking, and the clock skew optimization feature.

A new DLL-based approach for all-digital multiphase clock generation is presented. By using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-based solution can overcome the false-lock problem in conventional designs. Furthermore, the proposed all-digital multiphase clock generator (ADMCG) can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity in many different applications. The test chip shows that our proposal demonstrates a wide frequency range to meet the needs of many digital communication applications.

A clock generation circuit having the function of multiphase locking was designed using the synchronous mirror delay (SMD) scheme. The internal clock can be synchronized to the external clock with intended phase difference. The synchronizing error of the clock generation circuit is reduced below the delay time of unit delay stage by compensation characteristics of detecting circuit in SMD. A 32-M double data rate (DDR) SRAM including the clock generation circuit is fabricated using 0.13-/spl mu/m CMOS technology. To measure the synchronizing error of the clock generation circuit, the test elements group (TEG) system is designed and fabricated with the main system. The synchronizing error of the clock generation circuit is far smaller than the delay time of unit delay stage at zero phase locking and similar to the delay time of unit delay stage at multiphase locking.

In this paper, a global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The key design issues involved in generating standing waves on a chip are discussed, including minimizing wire loss within an available technology. A standing-wave oscillator, which is a distributed oscillator that sustains ideal standing waves on lossy wires, is introduced. A clock grid architecture comprised of coupled standing-wave oscillators and differential low-swing clock buffers is presented, along with a compact circuit model for networks of oscillators. The measured results for a prototyped standing-wave clock grid operating at 10 GHz and fabricated in a 0.18-/spl mu/m 6M CMOS logic process are presented. A technique is proposed for on-chip skew measurements with subpicosecond precision.

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.

Core and I/O clock design for the Pentium(R) 4 microprocessor is described. Two phase-locked loops generate core and I/O clocks supporting concurrent multiple frequencies. A clock distribution network with skew optimization and jitter reduction is designed to achieve low clock inaccuracies for processors at frequencies /spl ges/2 GHz for the core and /spl ges/4 GHz for the rapid execution engine. A global medium clock frequency is distributed. Local clock drivers generate pulsed or regular (nonpulsed) clocks at fast, medium, and slow frequencies. A 3.2-GB/s system bus is achieved using a dedicated I/O phase-locked loop with glitch protection and detection. Silicon speed path tools and clock debug features are designed to enable a short debug cycle.

Most modern microprocessors use a balanced tree to distribute the clock. However, at gigahertz clock speeds an increasing fraction of skew and jitter comes from random variations in gate and interconnect delay. The majority of jitter in a clock tree is introduced by buffers and inter-line coupling to the clock wires. A relatively small amount comes from noise in the source oscillator. This distributed clock network generates the clock signal with phase locked loops (PLLs) at multiple points (nodes) across a chip, and distributes each only to a small section of the chip (tile). Phase detectors (PD) at the boundaries between tiles produce error signals that are summed by an amplifier in each tile and used to adjust the frequency of the node oscillator.

The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market.

A 1.3-cycle lock-in time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation is proposed with an array structure of short-circuit-current-suppression interpolators. The circuits have been fabricated with a 0.25-/spl mu/m digital CMOS and operated in any condition where digital CMOS circuits operate. Measured results have achieved 1.3 clock cycle lock time and cycle-to-cycle jitter suppression characteristics. The circuits have been verified in 622-Mb/s clock and data recovery that satisfied the ITU-T G.958 jitter tolerance specification.

A nonfeedback CMOS digital-clock-generator, direct-skew-detect synchronous-mirror-delay (direct SMD) circuit has been developed that achieves clock-skew suppression in only two clock cycles for application-specific integrated circuits having unfixed and various clock paths. The direct SMD circuit detects both clock skew and clock cycle by using a direct-skew detector and clock-suspension circuitry. The skew-detection scheme removes the phase errors caused by delay in the clock-driver circuit. Measurements demonstrated that the direct SMD circuit eliminates various amounts of clock skew (2.0-3.0 ns) at 200 MHz in two clock cycles.

In telecommunications systems, the commonly used method to generate clocks is based on phase-locked loop or delay-locked loop related frequency synthesis. In this paper, we address a method of digital multiphase clock/pattern generation (MPCG) to generate a system clock or pulse pattern vector when a multiphase clock is available. The advantages of the multiphase clock method are: (a) the design method is digital; (b) the working frequency range is very wide; and (c) the sensitivity to noise is less than analog methods. Different approaches to implement the basic blocks in MPCG are described. A design example implemented in BiCMOS uses eight clock phases at 622 MHz obtained by dividing a 5-GHz clock to generate a clock at 622 MHz/spl times/32/53=376 MHz. By such a method, we can generate a pulse pattern vector as well. The maximum time resolution is equal to half of the phase difference. A low power solution is achieved without loss of circuit speed.

This paper discusses the design of the clock generator for the Alpha 21264. As the speed performances are of primary concern in the whole design, the clock-generator jitter and phase misalignment must be as low as possible in a very noisy environment. A dedicated on-chip voltage regulator based on a bandgap reference has been designed to reduce the effect of supply noise on the clock generator. To avoid a large voltage drop across the power-supply bond wires during the startup sequence, the core frequency can be increased by steps in one period of the core clock, with a limited frequency overshoot and no missing pulses. The circuit has been implemented in a CMOS 0.35 /spl mu/m process. The voltage-controlled-oscillator frequency range is between 350 MHz and 2.8 GHz, with a peak-to-peak cycle-to-cycle jitter lower than 16 ps. While booting Unix on a system, the maximum phase misalignment is lower than /spl plusmn/100 ps.

The clocking methodology for the 600 MHz Alpha microprocessor allows increased performance goals to be met through multi-level buffering. In addition power savings are realized through reduced metal usage and conditional clocks. Two distinct analysis methods are required to verify the clock design. One is used for large, globally distributed clocks and the other is applied to small, locally distributed clocks. The clock is generated from an 80-200 MHz reference clock multiplied by an on-chip phase-locked loop (PLL) to a nominal frequency of 600 MHz. The clock distribution network up to and including the global clock (GCLK) is included in the feedback loop of the PLL to control phase alignment. GCLK is the primary timing reference for the chip. The generation of GCLK begins at the PLL and is routed through a high-gain buffer network to a central point on the die. From there the clock is driven through buffered X, H and RC trees to distributed GCLK drivers located in a windowpane pattern across the chip. The final physical stage of the global clock distribution network is a grid of upper-level low-impedance metal that covers the entire die.

As cycle time of chips shrinks and die size grows, clock skew measured as a fraction of the cycle time is increasing. Traditional domino circuits shown are especially sensitive because skew must be budgeted in both half-cycles. The problem with such domino pipelines is that evaluation starts when the clock connected to the first gate in the half-cycle rises but the output needs to be valid before the clock on the output latch falls. In the worst case, the evaluate clock is late and the latch clock is early, decreasing time for logic. Many designers realize that some of the overhead can be reduced by using differential domino (also called dual rail) designs. An SR latch or pipeline latch at the end of dual-rail circuits lessens sensitivity to the falling edge. Self-timed techniques eliminate clocks and clock skew, but raise new issues of control overhead, timing assumption verification, and testability. The methodology reported here boosts operating frequency by tolerating clock skew, eliminating latches from the critical path, and better balancing logic between phases of the pipeline.

A front-end IC for EPR-IV partial-response maximum likelihood (PRML) detection systems used in magnetic recording systems is developed. Reorganization of the front-end architecture reduces clock acquisition time and lowers chip complexity and power. A new six-pole 80-MHz continuous-time filter equalizes waveforms to the desired ERR-IV target. The equalizer is tuned in quality-factor and frequency to a synthesized system clock, reducing drifts due to processing and temperature variations. An on-chip timing recovery circuit, incorporating a 160-MHz sampled-analog phase detector and 200-MHz voltage-controlled oscillator (VCO) regenerates the data clock. The phase detector used is appropriate for (1, 7) code, and can be extended to operate on (0, k) codes. During head seeks, a secondary loop incorporating the VCO locks to the write clock and acquires the anticipated read-clock frequency. All signal paths are serial and fully differential. The chip is fabricated in a 1-/spl mu/m CMOS process.

The HP-PA8000 is a 180-MHz quad-issue custom VLSI implementation of the HP-PA 2.0 64-b architecture delivering 11.84 SPECint95 and 20.18 SPECfp95 with 3.8 million transistors integrated on a 17.68 mm/spl times/19.1 mm die in a 3.3-V, 0.5-/spl mu/m CMOS process. Specialized clock circuits and extensive use of dynamic logic are key factors in this microprocessor's performance. Attention to clock analysis and distribution resulted in a 170 ps clock skew between any two clock nodes. This microprocessor utilizes a 56-entry instruction reorder buffer (IRE), register renaming, and dual functional units to fully exploit instruction level parallelism.

A programmable digital clock generator that produces a wide range of clock frequencies with fine resolution is described. The clock generator consists of a noise-shaping control loop and a number-controlled oscillator. The generated clock has a time-varying period. When this clock is used as the sampling clock in a switched-capacitor filter (SCF) to set its frequency response, the time-varying period causes nonuniform sampling, which is acceptable under certain conditions that are described. Measured performance of a 2-/spl mu/m CMOS implementation of the clock generator is presented. Also, measured data for the clock generator driving two SCF's are reported. >

This paper describes the application of a digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASICs. For a computer system consisting of nine PC boards ("modules") plugged into a back plane with two clock chips per board and six ASICs per clock chip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns.

A circuit measuring the phase of incoming asynchronous signals relative to the system clock in digital signal processing is described. The system clock can be in the range from 10 to 20 MHz, as is typical for video signal processing applications. As a reference in the asynchronous signal the positive or negative slope is taken. Its phase is measured with a resolution of 1/32 of a system clock cycle (approximately 1.5 to 3 ns). Pure digital CMOS technology without precision components is used, to enable combined integration on processor chips. Timing precision (jitter) is better than 200 ps without any adjustments. One external capacitor is needed. >

Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 mu m BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz. >

To ease global clock distribution in a synchronous system extending over several levels of interconnect (for example between logic blocks within a chip, chips mounted on a printed circuit board and boards of chips across a backplane), a race-free clocking scheme for CMOS VLSI requiring a single clock line is presented. Since the technique is race-free, the clock line may be driven by a sinusoid, thereby avoiding the transmission of the higher frequency components associated with fast clock edges. In this way, clock signal distortion due to transmission line effects will be kept to a minimum.

Delays of two clock signals propagating along their respective CMOS logic circuit paths can be matched against all processing variations if the sum of the pull-up delays of PFETs along the first signal path is matched to that of the second path, and if the sum of the pull-down delays of NFETs along the first path is matched to that of the second path. This design technique allows generation of a skewless pair of upgoing and downgoing CMOS clocks, and the technique allows the design of CMOS VLSI free from process-induced race conditions. The technique is flexible for light or heavy clock load and for the choice of decoder logic. The technique has a wide application in MOS circuits other than clock decoders.

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz. >

The authors describe the synchronous clock distribution problem in VLSI and techniques for its solution. In particular, the advantages and disadvantages of a hierarchical design technique for minimizing clock skew within a VLSI circuit are discussed. In addition, a model for clock distribution networks which considers the effects of distributed interconnect impedances on clock skew is described.

A single-phase clock has two edges. A clocking scheme utilizing the two edges of a single-phase clock to control the movement of data is presented. The scheme is similar to the two-phase nonoverlapping clocking scheme. A single-phase clock CMOS shift register to illustrate this clocking schemes is proposed. This shift register utilizes the bistable element, 'sense amplifier', to sense the state of its previous stage. There are two stages. The first stage triggers on the rising edge and the second stage triggers on the trailing edge. It is a static register with no minimum clocking frequency. Instead of four clock phases used in conventional CMOS dynamic shift registers, or two clock phases used in existing static registers, only one clock phase is used. This single-phase clocking scheme greatly reduces the overhead of having to route two or four clock signals around the chip. It also eliminated the clock skewing difficulty plaguing the conventional shift register. >

A programmable 8-b digital signal processor core with an instruction cycle time of 20 ns is developed. A 37.5-mm chip is fabricated by advanced 1.0- mu m double-level-metal CMOS technology. This processor has a reconfigurable high-speed data path supporting several multiply/accumulate function, including 16-tap linear-phase transversal filtering, high-speed adaptive filtering, and eight-point discrete cosine transformation. To provide high-speed operation within the chip, a programmable phase-locked loop circuit is built on the chip. This circuit generates a high-speed clock, which is a multiple of the system clock fed from outside, and is synchronized to the system clock. >

The design of clock generation circuitry being used as a part of a high-performance microprocessor chip set is described. A self-calibrating tapped delay line is used to generate four nonoverlapping clock phases of a system clock. A charge-pump phase-locked loop (PLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between the off-chip reference clock and the internal clock signals. Experimental results show that required timing relations can be obtained with less than 2-ns clock skew for frequencies from 1 to 18 MHz.

The authors describe two dynamic circuit techniques, using only a single-phase clock which is never inverted. This class of circuits has the advantages of simple clock distribution, small area for clock lines reduced clock skew problems, and high speed. Several examples are demonstrated.