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Clock generation and distribution for the first IA-64 microprocessor
- Source :
- IEEE Journal of Solid-State Circuits. 35:1545-1552
- Publication Year :
- 2000
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2000.
-
Abstract
- The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market.
- Subjects :
- Synchronous circuit
Clock signal
Computer science
business.industry
Underclocking
Clock rate
Skew
Static timing analysis
Clock gating
Integrated circuit design
Digital clock manager
Clock skew
Clock synchronization
Timing failure
law.invention
Microprocessor
Logic synthesis
Clock domain crossing
law
Embedded system
Master clock
Electrical and Electronic Engineering
business
CPU multiplier
Asynchronous circuit
Subjects
Details
- ISSN :
- 1558173X and 00189200
- Volume :
- 35
- Database :
- OpenAIRE
- Journal :
- IEEE Journal of Solid-State Circuits
- Accession number :
- edsair.doi...........bad983d8664c9d8a65df2b3f165576bb