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An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time
- Source :
- IEEE Journal of Solid-State Circuits. 38:198-204
- Publication Year :
- 2003
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2003.
-
Abstract
- An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.
- Subjects :
- Frequency synthesizer
Synchronous circuit
Clock signal
Pulse (signal processing)
Computer science
Clock rate
Clock gating
Digital clock manager
Integrated circuit
Clock skew
Phase detector
law.invention
Phase-locked loop
Time-to-digital converter
CMOS
Clock domain crossing
law
Electronic engineering
Inverter
Clock generator
Digitally controlled oscillator
Electrical and Electronic Engineering
CPU multiplier
Asynchronous circuit
Jitter
Subjects
Details
- ISSN :
- 00189200
- Volume :
- 38
- Database :
- OpenAIRE
- Journal :
- IEEE Journal of Solid-State Circuits
- Accession number :
- edsair.doi...........4a492cd8a01695e2f3aa6662a31f11d5