Search

Copper (Cu) material is being widely used in the advance ultra large-scale integration (ULSI) in the metallization process due to its low resistivity and good performance on EM in 130nm and below technology node. In Cu metallization process of 130nm, crescent pits defect on wafer edge is often scanned and found post Cu CMP process. Thus interconnect reliability and yield loss become key issue to ensure device quality and performance. In the filed, some studies focus on the Cu plating wetting ability improvement to reduce pits defect. In this paper, atmosphere VOC (Vapor Organic Compound) effect is studied to reduce crescent pits formation.

CMEMS(CMOS and Micro Electro Mechanical Systems) process is integration of CMEMS and cap wafer, which is realized through bonding process and has been more and more important in IC industry currently. The bonding process is kernel in CMEMS manufacture and is impacted by material, pressure, temperature and so on. In standard bonding process, Al-Ge bonding which is selected for the good adhesion comparing with other bonding material. In this paper, the bonding process conditions are designed according to the structure of CMEMS and characteristics of Al-Ge material, and experiments including leakage rate and bonding strength are implemented to discuss the bonding quality. In the end, suitable bonding process and its summary of side effect for Al-Ge are put forward.

Hillock is formed at the film surface in Cu metallization process. During the growth of hillock, the tensile stress built in the copper (Cu) metal film due to the relieved thermal expansion coefficients. These "hillocks" are just areas of localized copper elevation relative to the rest of the surface that can lead to non-uniformity during etch-stop dielectric deposition. It is important to understand how the hillock is created in order to develop an effective preventative process. In this paper, the degas temperature performance and effect on the hillock in Cu metallization process is introduced, then an effective approach to reduce hillock defect is demonstrated.

Shallow Trench Isolation(STI) is widely used in advanced CMOS technologies. This paper describes a shallow trench isolation for 0.13um CMOS technologies development which utilizes AMAT Ultima Plus High Density Plasma (HDP) CVD oxide process to fill 0.18um wide and 0.5um deep trenches with void free. Through optimizing source/bias RF power, process gas flow and cross section verification, as a result, we got a robust gap-fill recipe with void free.

Copper has been used as inter-wiring in deep-submicron integrated circuit (IC) for its lower resistivity and potentially higher resistance to electro migration. Copper Chemical-mechanical polishing/planarization (Cu CMP) is used to remove the redundant Cu and Ta/TaN/oxide to achieve dual damascene interconnect structure. Crater defect is one of the most dangerous killer defects in Cu CMP process. In this research, we will focus on study the forming mechanism of one typical ring type crater defect. Also the solution is studied and carried out to eliminate this ring type crater defect.

The influence of the SiN cap-layer deposition process including different pre-clean treatments on the voltage breakdown (VBD) and electromigration (EM) behavior of copper dual damascene metallization has been studied. A remarkable improvement for voltage breakdown and electromigration were revealed depending primarily on the pre-clean treatment before cap-layer deposition rather than the deposition process itself.

With the device dimension rapidly shrinking, Tungsten Chemical Mechanical Polishing (WCMP) becomes one of the critical manufacturing processes for multi-layer interconnection of ULSI (ultra large scale integrated) circuits. The effectiveness of Post-CMP cleaning is one of critical step for particles removal and product Cp yield improvement. WCMP re-clean process is a general way to further reduce particles on high-defect-density impacted wafers in IC manufacturing. However, W loss defect could be generated frequently due to the extra re-clean process introduced in post WCMP step for sub-0.13um devices. In this paper, the mechanism of W loss defect after re-clean process is studied. Also one novel approach is proposed to prevent W loss and improve product CP yield.

With the advancement of technology nodes, the demands on oxide CMP have become more stringent. Defectivity, rate, profile, selectivity to various films (in special applications), planarization efficiency, process window, as well as costs, are the main considerations in an advanced oxide CMP process. Polishing rate and profile tuning by slurry formulations are challenging in certain silica based slurry systems. In this paper, various designed, novel additives are explored to enhance oxide CMP performance. The effects of key factors including abrasive types, chemistry, and pH range on within wafer non-uniformity, especially on the wafer edge rate drop, have been studied. The results indicated that a controlled removal rate and desired wafer edge profile can be achieved through the optimum combination of functional chemistry compositions, abrasive type and properties, and pH. A number of possible mechanisms will also be discussed.

In advance Cu BEOL process, Encore Ta/TaN deposition process is widely used for barrier layer deposition to achieve lower via resistance and better electro migration and stress migration performance. However, wafer micro arcing existed frequently due to complex chamber design and DC/RF/AC/ESC adoption in Encore Ta process. To solve the micro arcing issue is the one of key topics in Encore Ta process. In this study, the formation mechanism of micro arcing is analyzed. Gas plug is introduced into Encore Ta process to prevent micro arcing.