A Robust Shallow Trench Isolation High Density Plasma Chemical Vapor Deposition Void Free Process for 0.13?m CMOS Technology

Shallow Trench Isolation(STI) is widely used in advanced CMOS technologies. This paper describes a shallow trench isolation for 0.13um CMOS technologies development which utilizes AMAT Ultima Plus High Density Plasma (HDP) CVD oxide process to fill 0.18um wide and 0.5um deep trenches with void free. Through optimizing source/bias RF power, process gas flow and cross section verification, as a result, we got a robust gap-fill recipe with void free.