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Low temperature measurements at 4.2 K and 77 K are performed on n- and p-MOSFETs of a 0.13 μm CMOS technology. Two parasitic current contributions are identified in the subthreshold regime and strong inversion at 4.2 K. The first one is related to a parasitic parallel conduction inherent to Shallow Trench Isolation. Whereas the second one, resulting in a second peak in the linear transconductance, is discussed in terms of a stronger impact of substrate majority carriers due to a higher substrate resistivity at 4.2 K. The measured substrate current in n-MOSFETs is probably originating from electrons tunneling from the substrate valence band to the gate. At 4.2 K, the substrate current induces a reduction of the threshold voltage resulting in the measured “kink" of the $\rm I_D(V_G)$characteristic and the second transconductance peak at low drain bias.

An extended low temperature study of 0.13 μm Partially-Depleted Silicon-On-Insulator nMOSFETs without body contact is carried out. The impact of HALO doping characteristics on device output performance is investigated. The electrical properties of the technology are explored in terms of circuit applications both in digital and analog sense. The occurrence of inherent parasitic bipolar effects is also studied.

In a first part, the impact of low temperature operation on the classical short channel effects will be discussed critically. Particular attention will be given to the reduction of the threshold voltage VTwith effective device length in the temperature range 4.2 K to 300 K and to the short-channel behaviour of the subthreshold swing 1/S. In a second part, the impact of dopant freeze-out on the static operation of deep submicron n-MOSFETs will be studied. A comparison is made between standard 0.25 µm B doped and exploratory 0.1 µm In doped transistors. Although the experimental threshold voltage behaviour of deep submicron MOSFETs at cryogenic temperatures can be qualitatively described by the standard equations, a significant difference is noted between the measured and the calculated VT, which is most pronounced in the liquid helium temperature range. Possible additional factors which should be taken into account in a refined modeling will be pointed out, with particular emphasis on the contribution of the interface state charge.

This work studies the influence of the back gate voltage on the LDD SOI nMOSFETs series resistance at 300 K and 77 K and corresponding to two different buried oxide thicknesses. The MEDICI simulated results were used to support the analysis. It was observed that for lower buried oxide thickness the influence of the back gate bias is higher, mainly at 77 K. However, this influence becomes negligible when the back interface below the LDD region is inverted and the depletion region in the LDD reaches its maximum saturation value.

This paper presents a review of the evolution of the cryo-electronics since the 50's up to date. With this review we make a prediction of applicability for RF-electronics, nanoelectronics, and giga-scaled electronics, in a perspective for the years 2000 to come. This study is based on a survey of scientific papers/reports published since the years 1950's up to date in the field of semiconductor materials, devices and electronic systems for cryo-applications. With the very recent advent of nanotechnologies, multiple-level-wiring interconnections, hybrid superconductor-semiconductor systems, the rapid evolution of mini- and micro-coolers, and the appearance of physical limitations for further downscaling, it is worth to explore the option of cryo-operation of electronic devices/systems, and identify possible limitations, possible applications, and establish future guidelines.

The possibilities and limitations of non-destructive extended defect characterization techniques, i.e. X-ray topography, carrier recombination imaging and laser scattering tomography are illustrated by a case study whereby a dislocation problem occurred during the local isolation step of a CMOS compatible diode process. It is shown that the diode yield is correlated with the presence of dislocations observed after the full process. The “in process" application of the techniques is illustrated by investigating defect formation after different local isolation processes.

This paper describes the static I-V characteristics at cryogenic temperatures (77 K and 4.2 K) of so-called dual-gate Silicon-on-Insulator (SOI) MOSFETs, fabricated in the Gate-all-Around (GAA) technology. The n-channel devices are characterised by an increase of the threshold voltage and the transconductance upon cooling, which is observed both for the edgechannel component and for the primary drain current. It is shown that the devices suffer less from the hysteresis and transient effects, which have been reported before in standard SOI transistors. For the first time, the occurrence of the back-gate induced Multistable-Charge-Controlled-Memory (MCCM) effect in GAA devices is demonstrated at 4.2 K. The p-channel devices on the other hand show specific instabilities at deep cryogenic temperatures, which are related to the unexpected reduction of |VT|.

This paper describes the cryogenic operation of partially depleted Silicon-On-Insulator inverters. As is shown, the floating operation yields a degradation of the transfer characteristics, which increases upon cooling. Additionally, at cryogenic temperatures, hysteresis effects further deteriorate the performance. These observations will be discussed in view of the cryogenic SOI MOSFET characteristics and anomalies. Finally, the impact of the so-called twingate configuration on the improvement of the inverter characteristics at low temperatures will be demonstrated and discussed.

In this paper, an overview is given of the methods for practical parameter extraction for MOSFETs operated at cryogenic temperatures. The methods considered are based on the input characteristics of the device, from which the charge threshold voltage, the subthreshold slope, the effective mobility, the series resistance and the effective gate length is derived. Whenever possible, the physical basis of the mostly semi-empirical methods will be outlined. Finally, pitfalls and problems, related to low temperature MOSFET characterisation, like transient and freeze-out effects, self-heating, etc, are briefly discussed.

This work studies the influence of mobility degradation on the effective channel length Leff( Leff= Lm-ΔL) extraction in submicron fully depleted SOI MOSFETs at 77 K. Second-order effects can cause mobility degradation, mainly at 77 K, and if standard techniques have been used, negative values of ΔL can be obtained. It will be shown that this result can be caused by a length-dependent mobility degradation factor.

Although the oxygen precipitation process has been extensively studied during the last two decades, there still exists controversy concerning the electrical activity of the precipitates and the associated extended defect complexes. Therefore in the present study a unique combination of complementary characterization techniques is used to gain a better insight into the structural and electrical properties of oxygen-precipitation induced extended defects. TEM and LST are used for the structural analyses, while DLTS, PL, lifetime measurements, EBIC analyses and low frequency noise spectroscopy are used for the electrical characterization. The experimental observations are compared with relevant data available in the literature. Strong evidence is given that in clean processed wafers, the dominant recombination activity is associated with the dislocations, rather than with the precipitates themselves.

Abstract The degradation of the electrical properties of IGBTs (Insulated-Gate Bipolar Transistors) by 2-MeV electron irradiation at high-temperatures was studied. The irradiation temperatures were 25, 100, 200 and 300∘C, and the fluence was fixed at 1015 e/cm2. For most experimental conditions, the threshold voltage (VTH) is observed to recover partially during 100∘C and the saturation voltage (VCEsat) increase is most pronounced at 100∘C. It is shown that in this irradiation temperature range, the temperature dependency of the voltage shift due to the radiation-induced interface traps (Δ Vit) and the voltage shift due to the radiation-induced oxide traps (Δ Vot) are different, which suggests a possible degradation mechanism for these phenomena. It is tentatively suggested that the diffusion of hydrogen released from the gate by the 2-MeV electrons passivates the interface traps during the high temperature irradiation.

Abstract The impact of radiation damage on the device performance of 4H-SiC Schottky diodes, which are irradiated at room temperature with 2-MeV electrons is studied. After irradiation the reverse current increases, while the forward current and the capacitance decrease with barrier height and carrier density. The decrease of the barrier height is mainly responsible for the increase of the reverse current, while the decrease of the forward current for a high fluence is caused by the increase of the resistance in the bulk of the crystal. Although no electron capture levels are observed before irradiation, three electron capture levels (E1, E2, and E3) are induced after irradiation. It is noted that the decrease in carrier density is partly caused by the contribution of non-observed electron capture level in the DLT spectrum, which compensates the free carriers.

Abstract A new method for body potential estimation of ultra thin gate oxide fully-depleted silicon-on-insulator MOSFETs in accumulation mode operation is presented. The impact of the back gate voltage, gate length and drain voltage on the body potential is investigated. The magnitude of the Electron Valence Band gate tunneling-induced 2nd peak of the transconductance, characteristic of these ultra thin gate oxide FD SOI MOSFETs, is analyzed in terms of body potential changes and front gate characteristics shifts. Finally, a decrease of the body potential for strong accumulation back gate biases is revealed and discussed.

This paper reports on a Deep Level Transient Spectroscopy (DLTS) study of both oxygen-related thermal donors (OTDs) and radiation-induced defects (RDs) formed in high-temperature 1 MeV electron irradiated n-type Czochralski silicon. The heating of Si samples is done in-situ by the electron beam. The formation of deep levels is studied on both heat-treated and irradiated at high temperature sides of samples. The interaction between OTDs and RDs is investigated. (© 2004 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Results are presented of a detailed study of the effects of a high-temperature 2-MeV electron irradiation on the performance degradation of shallow trench isolation (STI) diodes. The macroscopic device performance will be correlated with the radiation-induced defects, observed by deep level transient spectroscopy (DLTS). It was found that the reverse current increases after irradiation. After 20 °C irradiation, two majority hole capture levels with (Ev+0.18 eV) and (Ev+0.34 eV) were induced in the n-Si substrate, while one hole capture level at (Ev+0.14 eV) was also found after 200 °C irradiation. Additionally, the degradation of the device performance and the introduction rate of the lattice defects decrease with increasing irradiation temperature. This result suggests that the creation and recovery of the radiation damage proceeds simultaneously at high temperatures.

Results are presented of a detailed study of the effects of high-temperature 4-MeV neutron irradiation on the performance degradation of Si pin photodiodes together with the radiation-induced defects, observed by deep level transient spectroscopy (DLTS). It was found that the dark current increases after irradiation, while the photocurrent decreases. After irradiation, two majority electron capture levels with (Ec–0.22 eV) and (Ec–0.40 eV) were induced in the n-Si substrate, while one minority hole capture level with (Ev+0.37 eV) was found. Additionally, the degradation of the device performance and the introduction rate of the lattice defects decreases with increasing irradiation temperature. For a 250 °C irradiation, the reduction of the reverse current is only 20% of the starting value. This result suggests that the creation and recovery of the radiation damage proceeds simultaneously at high temperatures.

The authors present a review of low-frequency noise (LFN) in polysilicon-emitter (PE) bipolar junction transistors (BJTs). It includes noise results from unstressed as well as stressed devices. A discussion of the possible physical origins of low-frequency noise is presented. Details of noise measurement and a simple noise equivalent circuit, with related noise spectral-density expressions, are given. The first part of the paper deals with noise in virgin or unstressed devices. It starts with a detailed discussion of low-frequency noise results in virgin devices. This includes noise in ultra-small transistors and a discussion of the possible physical origin(s) of the noise. Low-frequency noise in npn and pnp transistors and a technique to estimate the collector 1/f noise are then presented. Since devices are scaled to achieve better high-frequency performance, a discussion of low-frequency noise as a function of emitter geometry for transistors from several different technologies is presented. The second part of the paper deals with degradation of the LFN performance due to electrical stress. It begins with a discussion of degradation mechanisms, followed by a phenomenological discussion of low-frequency noise after hot-carrier (HC) stress. A discussion of the modelling of low-frequency noise after hot-carrier degradation due to reverse current or reverse bias voltage stresses is presented. The effects of forward bias degradation on the low-frequency noise in BJTs are presented and discussed. Finally, it is demonstrated that the noise in PE-BJTs is more sensitive to degradation than the DC characteristics.

Results are presented of a study on the radiation damage and its recovery behavior resulting from thermal annealing of n-MOSFETs fabricated in a 0.8-μm single-well BiCMOS process, subjected to γ-rays, 1-MeV electrons and 1-MeV neutrons. After irradiation, the base (substrate) current and interface trap density normally increase with increasing fluence. This result points out that both ionization damage in the gate oxide and lattice defects in the p-well are induced by the irradiation. The interface trap density recovers by 85% for γ-ray irradiation with a fluence of 1×108rad, after a 300 °C annealing.

The impact of the thickness of the cobalt-silicide layer on the electrical diode characteristics will be reported, with particular emphasis on the current-voltage (I-Vcharacteristics, the surface and bulk carrier recombination lifetime and the low-frequency noise. It is shown that for thicker silicides the generation-recombination of holes in the top n+-layer is enhanced, giving rise to a higher diffusion current, an increase in the noise and a larger surface recombination velocity. It is believed that these parameters are closely linked, as the underlying physical phenomenon is the minority carrier recombination. In addition, it is shown by transmission electron microscopy that the silicide-silicon interface roughness is increased for larger cobalt thickness, which may explain some of the observations.

The impact of the well doping profile on the current–voltage (I-V) and capacitance–voltage (C-V) characteristics of cobalt-silicided n+-pp+-n junction diodes fabricated in a 0.18 βm CMOS compatible processing scheme is studied. It will be shown that the nature of the junction (abrupt or linearly graded) has a strong influence on the resulting leakage current. Moreover, the extra thermal budget to create a nitrided gate oxide may drastically change the B-profile in the p-well and deteriorate the overall characteristics. From a detailed analysis, it is concluded that the increased leakage current observed for the nitrided case occurs at the perimeter of the diodes, where the Co-silicide may form a Schottky contact with the underlying n- or p-well. In order to control the leakage, the overall thermal budget should be optimized, particularly with respect to the back-end processing.

This paper presents a modified excess carrier profiling technique using carrier decay cross-sectional scans of wafers using a narrow excitation fiber guided beam and by using infrared light as well as microwave probes. The theoretical principles of the technique are based on the analysis of the depth variation of decay shape and the amplitude.