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In this work, we have investigated the performance of a 4H–SiC radiation sensor in the temperature range from 25 °C to 450 °C to explore its compatibility as detector of fast ion losses in plasma diagnostic of future nuclear fusion reactors. To simulate the escape of fusion-born alpha particles in D-T (deuterium-tritium) fusion plasmas, spectroscopic measurements were carried out in a vacuum chamber by irradiating the detector with a 3.5 MeV alpha beam from a Tandem accelerator. The detector was found to have an energy resolution ≤2% over the entire temperature range analyzed. Relevantly, the excellent spectrometric capabilities of the device have allowed us to calculate from experimental data, with unprecedented accuracy, the average energy required to create a single electron-hole pair in 4H–SiC as a function of temperature.

Graphene solution-gated field-effect transistors (gSGFETs) offer high potential for chemical and biochemical sensing applications. Among the current trends to improve this technology, the functionalization processes are gaining relevance for its crucial impact on biosensing performance. Previous efforts are focused on simplifying the attachment procedure from standard multi-step to single-step strategies, but they still suffer from overreaction, and impurity issues and are limited to a particular ligand. Herein, a novel strategy for single-step immobilization of chemically modified aptamers with fluorenylmethyl and acridine moieties, based on a straightforward synthetic route to overcome the aforementioned limitations is presented. This approach is benchmarked versus a standard multi-step strategy using thrombin as detection model. In order to assess the reliability of the functionalization strategies 48-gSGFETs arrays are employed to acquire large datasets with multiple replicas. Graphene surface characterization demonstrates robust and higher efficiency in the chemical coupling of the aptamers with the single-step strategy, while the electrical response evaluation validates the sensing capability, allowing to implement different alternatives for data analysis and reduce the sensing variability. In this work, a new tool capable of overcome the functionalization challenges of graphene surfaces is provided, paving the way toward the standardization of gSGFETs for biosensing purposes.

Silicon carbide (SiC) is a wide bandgap semiconductor with outstanding properties that make it especially appropriate for radiation monitoring in radiation harsh environments and for elevated temperature operation. In this work, radiation effects in electron-, neutron-, and proton-irradiated 4H-SiC p-n junction diodes are investigated by means of electrical characterization, including current-voltage characteristics measured at different temperatures ranging from -50 °C to +200°C. Moreover, the stability of the radiation-induced effects is evaluated through a series of low-temperature treatments (up to 400 °C). Interestingly for applications, partial recovery of diode rectification functionality is observed for electron-irradiated devices. Furthermore, partial recuperation of detectors' charge collection efficiency (CCE) is registered on either electron-, neutron-, or proton-irradiated devices. Remarkably, it is observed that the limited conduction registered for highly irradiated SiC detectors allows their operation in forward bias conditions. In fact, while providing some lower CCE, they show better energy resolution than in conventional reverse bias operation. Advantages of using SiC devices in alpha particle detection in harsh environments, as well as simplification of current Si experiments, can be envisaged.

The present invention refers to a method for exfoliating and transferring graphene from a doped silicon carbide substrate to another substrate, the method being based on exfoliation induced by hydrogen bubbles produced in the electrolysis of water

Due to their low leakage current, low noise levels, high thermal conductivity, and potential radiation hardness, SiC devices offer various advantages over Si devices in certain applications. As a result, they are being considered for operation in harsh environments, such as plasma diagnostic systems in future nuclear fusion reactors or in high energy physics applications. We report on relevant results of the GRACE project, which seeks to deliver a new generation of SiC sensors with graphene-enhanced contacts. Such devices are aimed to be radiation-hard and functional at high temperatures. The work presented in this paper focuses on the optimisation of the electrical contacts, along with the electrical characterisation and radiation-tolerance assessment of the first sensor prototypes produced.

Due to their low leakage current, low noise levels, high thermal conductivity, and potential radiation hardness, SiC devices offer various advantages over Si devices in certain applications. As a result, they are being considered for operation in harsh environments, such as plasma diagnostic systems in future nuclear fusion reactors or in high energy physics applications. We report on relevant results of the GRACE project, which seeks to deliver a new generation of SiC sensors with graphene-enhanced contacts. Such devices are aimed to be radiation-hard and functional at high temperatures. The work presented in this paper focuses on the optimisation of the electrical contacts, along with the electrical characterisation and radiation-tolerance assessment of the first sensor prototypes produced.

Due to their low leakage current, low noise levels, high thermal conductivity, and potential radiation hardness, SiC devices offer various advantages over Si devices in certain applications. As a result, they are being considered for operation in harsh environments, such as plasma diagnostic systems in future nuclear fusion reactors or in high energy physics applications. We report on relevant results of the GRACE project, which seeks to deliver a new generation of SiC sensors with graphene-enhanced contacts. Such devices are aimed to be radiation-hard and functional at high temperatures. The work presented in this paper focuses on the optimisation of the electrical contacts, along with the electrical characterisation and radiation-tolerance assessment of the first sensor prototypes produced.

La presente invención se refiere a un dispositivo MOSFET dispuesto sobre un sustrato (10), que comprende una primera (11) y una segunda (14) tiras fuertemente dopadas recubiertas de una primera (13) y una segunda (15) toma de contacto, dichas dos tiras estando separado por un canal (18) que también aparece sobre el sustrato (10), estando el canal recubierto por una capa dieléctrica (20) sobre la cual se coloca una tercera toma de contacto (21). El dispositivo se caracteriza porque el canal (18) incorpora una fina película ligeramente dopada (19) con átomos dopantes del mismo tipo que el canal, en la interfaz con la capa dieléctrica (20), estando distribuidos los átomos dopantes sobre cada lado de la interfaz.

Due to their low leakage current, low noise levels, high thermal conductivity, and potential radiation hardness, SiC devices offer various advantages over Si devices in certain applications. As a result, they are being considered for operation in harsh environments, such as plasma diagnostic systems in future nuclear fusion reactors or in high energy physics applications. We report on relevant results of the GRACE project, which seeks to deliver a new generation of SiC sensors with graphene-enhanced contacts. Such devices are aimed to be radiation-hard and functional at high temperatures. The work presented in this paper focuses on the optimisation of the electrical contacts, along with the electrical characterisation and radiation-tolerance assessment of the first sensor prototypes produced.

[Abstract] In recent years, the quest for surface modifications to promote neuronal cell interfacing and modulation has risen. This course is justified by the requirements of emerging technological and medical approaches attempting to effectively interact with central nervous system cells, as in the case of brain-machine interfaces or neuroprosthetic. In that regard, the remarkable cytocompatibility and ease of chemical functionalization characterizing surface-immobilized graphene-based nanomaterials (GBNs) make them increasingly appealing for these purposes. Here, we compared the (morpho)mechanical and functional adaptation of rat primary hippocampal neurons when interfaced with surfaces covered with pristine single-layer graphene (pSLG) and phenylacetic acid-functionalized single-layer graphene (fSLG). Our results confirmed the intrinsic ability of glass-supported single-layer graphene to boost neuronal activity highlighting, conversely, the downturn inducible by the surface insertion of phenylacetic acid moieties. fSLG-interfaced neurons showed a significant reduction in spontaneous postsynaptic currents (PSCs), coupled to reduced cell stiffness and altered focal adhesion organization compared to control samples. Overall, we have here demonstrated that graphene substrates, both pristine and functionalized, could be alternatively used to intrinsically promote or depress neuronal activity in primary hippocampal cultures.

Die-level current crowding phenomena are analyzed at the microsecond timescale with an internal IR-Laser Deflection set-up. To this end, the 4H-SiC plasma-optical coefficient for the refractive index is reported for the first time. A SiC Schottky diode with an edge termination based on a junction termination extension is used as a test vehicle. Under biasing conditions, the edge termination starts a local bipolar conduction along the device active area perimeter, leading to current crowding effects. Using refractive index measurements, a depth-resolved carrier profile is extracted and assessed using both, simulation and Free Carrier Absorption measurements.

The present invention refers to a method for exfoliating and transferring graphene from a doped silicon carbide substrate to another substrate, the method being based on exfoliation induced by hydrogen bubbles produced in the electrolysis of water

A MOSFET device arranged on a substrate 10 having first and second heavily-doped strips 11 and 14 respectively covered by first and second contacts 13 and 15, these two strips being spaced apart by a channel 18 that also appears on the substrate 10, the channel being covered by a dielectric layer 20, itself surmounted by a third contact 21. The channel 18 incorporates a thin film 19 lightly doped with dopant atoms of a same type as the channel, at the interface with the dielectric layer 20, the dopant atoms being distributed on both sides of the interface.

[FR] La présente invention concerne un dispositif MOSFET agencé sur un substrat (10) comprenant une première (11) et une seconde (14) bande fortement dopées recouvertes d'une première (13) et d'une seconde (15) prise de contact, ces deux bandes étant séparées par un canal (18) figurant lui aussi sur le substrat (10), le canal étant recouvert d'une couche diélectrique (20) elle-même surmontée d'une troisième prise de contact (21). Le dispositif est remarquable en ce que le canal (18) intègre un film mince (19) légèrement dopé avec des atomes dopant de même type que le canal, à l'interface avec la couche diélectrique (20), les atomes dopant étant répartis de chaque côté de l'interface., [EN] The present invention relates to a MOSFET device arranged on a substrate (10), comprising a first (11) and a second (14) heavily doped strip covered with a first (13) and a second (15) contact tap, said two strips being separated by a channel (18) which also appears on the substrate (10), the channel being covered with a dielectric layer (20) on top of which a third contact tap (21) is positioned. The device is characterised in that the channel (18) incorporates a thin, lightly-doped film (19) with doping atoms of the same type as the channel, at the interface with the dielectric layer (20), the doping atoms being distributed on each side of the interface.

A device for improving the mobility of carriers in a mosfet channel on silicon carbide 5 arranged on a substrate 10 comprising first and second heavily-doped strips 11 and 14 respectively covered by first and second contacts 13 and 15, these two strips being spaced apart by a channel 18 that also appears on 10 the substrate 10, the channel being covered by a dielectric channel 20, itself surmounted by a third contact 21. Incorporated a thin film 19 lightly doped with dopant 15 atoms of a same type as the channel, at the interface with the dielectric layer 20, the dopant atoms being distributed on both sides of the interface.

The exploration and colonization of the outer space represents a foreseeable future for the Humanity. This endeavour involves deepening our knowledge about the formation and evolution of the solar system, of other planetary systems, emergence of life (and its prospects once it exists), the interaction between Earth and Space (particularly with its Sun) and the impact of space conditions (radiation, gravity, etc.) on Earth-borne organisms. Materialization of this exploration and colonization currently drives technological developments in several fronts as optics, electronics and sensors just to mention a few. Other aspects as well law & ethics, psychology, biology, etc., cannot be discarded.

Procedimiento de exfoliación y transferencia de grafeno de un sustrato de carburo de silicio dopado a otro sustrato La presente invención se refiere a un procedimiento de exfoliación y transferencia de grafeno de un sustrato de carburo de silicio dopado a otro sustrato, donde dicho procedimiento se basa en su exfoliación inducida por el burbujeo de hidrógeno que se produce en la electrolisis del agua

The present invention relates to a MOSFET device arranged on a substrate 10 comprising first and second heavily-doped strips 11 and 14 respectively covered by first and second contacts 13 and 15, these two strips being spaced apart by a channel 18 that also appears on the substrate 10, the channel being covered by a dielectric layer 20, itself surmounted by a third contact 21. The device is remarkable in that the channel 18 incorporates a thin film 19 lightly doped with dopant atoms of a same type as the channel, at the interface with the dielectric layer 20, the dopant atoms being distributed on both sides of the interface.

La présente invention concerne un dispositif MOSFET agencé sur un substrat 10 comprenant une première 11 et une seconde 14 bande fortement dopées recouvertes d'une première 13 et d'une seconde 15 prise de contact, ces deux bandes étant séparées par un canal 18 figurant lui aussi sur le substrat 10, le canal étant recouvert d'une couche diélectrique 20 elle-même surmontée d'une troisième prise de contact 21. Le dispositif est remarquable en ce que le canal 18 intègre un film mince 19 légèrement dopé à l'interface avec la couche diélectrique 20, les atomes dopant étant répartis de chaque côté de l'interface.

La présente invention concerne un dispositif MOSFET agencé sur un substrat 10 comprenant une première 11 et une seconde 14 bande fortement dopées recouvertes d'une première 13 et d'une seconde 15 prise de contact, ces deux bandes étant séparées par un canal 18 figurant lui aussi sur le substrat 10, le canal étant recouvert d'une couche diélectrique 20 elle-même surmontée d'une troisième prise de contact 21. Le dispositif est remarquable en ce que le canal 18 intègre un film mince 19 légèrement dopé à l'interface avec la couche diélectrique 20, les atomes dopant étant répartis de chaque côté de l'interface.

Owing to their low dark current, high transparency, high thermal conductivity, and potential radiation hardness, there is a special interest in silicon carbide (SiC) devices for radiation monitoring in radiation harsh environments and with elevated temperatures and, especially, for the plasma diagnostic systems in future nuclear fusion reactors. In this work, four-quadrant p-n junction diodes produced on epitaxial 4H-SiC substrates are studied. The impact of electron, neutron, and proton irradiations (up to fluences of 1 × 10 16 electrons (e)/cm 2 , 2 × 10 15 neutrons (n)/cm 2 , and 2.5 × 10 15 protons (p)/cm 2 , respectively) on the electrical characteristics is studied by means of current-voltage (I-V) and capacitance-voltage (C-V) techniques. Regardless of the particle type and applied fluences, the results show similar low reverse currents for irradiated SiC devices, which are at least about four orders of magnitude lower than comparable Si devices. The effects of irradiation on interquadrant resistance and charge build-up in the interquadrant isolation are assessed. Furthermore, device performance as a radiation detector is investigated upon exposure to a collimated 239 Pu- 241 Am- 244 Cm trialpha source. The performance at room temperature is preserved even for the highest irradiation fluences, despite the fact that the rectification character in electrical characteristics is lost. From the results, advantages of using SiC devices in alpha particle detection in harsh environments can be envisaged.

Transistor de efecto campo (MOSFET) y procedimiento de fabricación del mismo. La invención comprende un transistor metal-oxido-semiconductor de efecto campo (MOSFET) de diamante para alta potencia, así como el procedimiento de fabricación mediante crecimiento lateral/selectivo. La combinación del crecimiento sobre el sustrato de las primeras capas de forma vertical estándar con el uso de un crecimiento lateral selectivo sobre la estructura mesa grabada confiere al dispositivo MOSFET de una estructura tridimensional novedosa. Esta evita los efectos de borde de los contactos metálicos y los altos campos eléctricos internos, mejora la calidad cristalina del diamante y reduce los tiempos, costes y tamaño del dispositivo dotándole a su vez de una mayor versatilidad para su implementación sobre arquitecturas más compleja. [ES], The invention relates to a field-effect transistor (MOSFET) and a method for manufacturing same. The invention comprises a high-power diamond metal-oxide-semiconductor field-effect transistor (MOSFET), as well as the method for manufacturing same by lateral/selective growth. The combination of growth on the substrate of the first layers with a standard vertical shape and the use of selective lateral growth on the etched-mesa structure grants the MOSFET device a novel three-dimensional structure. This avoids the edge effects of the metal contacts and the high internal electrical fields, improves the crystalline quality of the diamond and reduces the times, costs and size of the device, also making it more versatile for implementation on more complex architectures. [EN]

Transistor de efecto campo (MOSFET) y procedimiento de fabricación del mismo. La invención comprende un transistor metal-oxido-semiconductor de efecto campo(MOSFET) de diamante para alta potencia, así como el procedimiento de fabricación mediante crecimiento lateral/selectivo. La combinación del crecimiento sobre el sustrato de las primeras capas de forma vertical estándar con el uso de un crecimiento lateral selectivo sobre la estructura mesa grabada confiere al dispositivo MOSFET de una estructura tridimensional novedosa. Esta evita los efectos de borde de los contactos metálicos y los altos campos eléctricos internos, mejora la calidad cristalina del diamante y reduce los tiempos, costes y tamaño del dispositivo dotándole a su vez de una mayor versatilidad para su implementación sobre arquitecturas más complejas.

La presente invención se refiere a un conjunto de máscaras metálicas auto alineadas para depositar, de modo selectivo, capas finassobre dispositivos y substratos microelectrónicos que comprendelas partes siguientes: a) una máscara superior metálica con los orificios o zonas que definen los motivos que se han de metalizar,provista de los agujeros de centrado, b) una máscara inferior metálica con los orificios de las mismas dimensiones y forma que los sustratos o dispositivos a metalizar y otros auxiliares de centrado del conjunto, c) una pieza o base provista de unos vástagoscoincidentes con los agujeros auxiliares, que permite el centradode las partes anteriores,una pieza o marco superior que permitefijar y mantener alineado el conjunto completo mediante tornillosy ligera presión; este conjunto puede a su vez fijarse al portamuestras de la máquina de deposición. [ES], The invention in question relates to a self-aligned metal mask assembly for selectively depositing thin films on microelectronic substrates and devices, comprising the following parts: a) an upper metal mask with the orifices or zones that define the patterns to be metallized, said mask having centring holes, b) a lower metal mask with orifices of the same size and shape as the substrates or devices to be metallized, and further auxiliary holes for centring the assembly, c) a piece or base with rods corresponding to the auxiliary holes, for centring the above parts, an upper piece or frame for securing and keeping the complete assembly aligned by means of screws and slight pressure. The assembly can in turn be secured to the sample-holder of the deposition machine. [EN]

The present invention relates to a MOSFET device arranged on a substrate (10), comprising a first (11) and a second (14) heavily doped strip covered with a first (13) and a second (15) contact tap, said two strips being separated by a channel (18) which also appears on the substrate (10), the channel being covered with a dielectric layer (20) on top of which a third contact tap (21) is positioned. The device is characterised in that the channel (18) incorporates a thin, lightly-doped film (19) with doping atoms of the same type as the channel, at the interface with the dielectric layer (20), the doping atoms being distributed on each side of the interface. [EN], La présente invention concerne un dispositif MOSFET agencé sur un substrat (10) comprenant une première (11) et une seconde (14) bande fortement dopées recouvertes d'une première (13) et d'une seconde (15) prise de contact, ces deux bandes étant séparées par un canal (18) figurant lui aussi sur le substrat (10), le canal étant recouvert d'une cuche diélectrique (20) elle-même surmontée d'une troisème prise de contact (21). Le dispositif est remarquable en ce que le canal (18) intègre un fil mince (19) légèrement dopé avec des atomes dopant de même type que le canal, à l'interface ave la couche diéletrique (20), les atomes dopant étant répartis de chaque côté d'interface. [FR]

The exploration and colonization of the outer space represents a foreseeable future for the Humanity. This endeavour involves deepening our knowledge about the formation and evolution of the solar system, of other planetary systems, emergence of life (and its prospects once it exists), the interaction between Earth and Space (particularly with its Sun) and the impact of space conditions (radiation, gravity, etc.) on Earth-borne organisms. Materialization of this exploration and colonization currently drives technological developments in several fronts as optics, electronics and sensors just to mention a few. Other aspects as well law & ethics, psychology, biology, etc cannot be discarded.

A sustainable future requires efficient power electronic converters at any stage of the electrical energy consumption. Silicon carbide (SiC) is one of the most technologically advanced wide bandgap semiconductors that can outperform silicon limits for power devices. SiC power MOSFETs are of the greatest interest since they are unipolar gate-controlled switches with high blocking voltage capability and reasonably low specific on-resistance. The focus of this thesis is on the design optimisation and process technology refinement towards the improvement of high-voltage SiC MOSFETs. Previous developments in our group were taken as a reference for this work. The results of this research allowed the fabrication of large-area SiC power MOSFETs with voltage ranges targeting 1.7 kV up to 6.5 kV. The inherent properties of SiC entail challenging technological solutions to successfully integrate a power MOSFET of such high-voltage capability. To ensure suitable blocking capability, different planar edge termination structures have been designed, optimised by TCAD simulation and implemented on PiN diodes. The termination schemes considered are single-zone JTE, FGRs and a novel RA-JTE structure combining JTE with rings. RA-JTE design, with the lowest sensitivity to fabrication process deviations and a lower consumed area, achieved more than 90% of the ideal breakdown voltage and suitable blocking capability up to 6.5 kV. The optimisations performed on the unit-cell of the SiC power MOSFET target both the layout design and the fabrication process. The optimisation has been performed by TCAD modelling and experimental evaluation of specific test structures. Several techniques to improve the performance of the fabricated devices have been considered: i) the use of an offset retrograde p-body profile to provide an adequate Vth value while preventing p-body punch-through, ii) a submicronic self-aligned channel definition, iii) a boron treatment to the gate oxide to improve channel mo, Un futur sostenible requereix convertidors electrònics d'alta potència eficients per totes les fases del consum d'energia elèctrica. El carbur de silici (SiC) és un dels semiconductors de banda prohibida ampla més avançats que permet superar els límits de silici en dispositius de potència. El gran interès en els MOSFETs de potència SiC recau en que són interruptors unipolars que presenten una alta capacitat de tensió de bloqueig i una resistència específica relativament baixa. L’objectiu d’aquesta tesi és la optimització del disseny i el perfeccionament de la tecnologia de processos per a la millora dels MOSFETs d’alta tensió SiC tenint com a referencia els desenvolupaments previs realitzats pel grup. Els resultats d'aquesta investigació han permès la fabricació de MOSFETs de potència de SiC d’àrea gran amb capacitat de bloqueig des de 1,7 kV fins a 6,5 kV. Les inherents propietats del SiC requereixen solucions tecnològiques específiques per a integrar amb èxit un MOSFET de potència de tensió tan elevada. Per garantir una bona capacitat de bloqueig, s'han dissenyat diferents estructures de terminació planars, optimitzades per simulació i implementades sobre díodes PiN. Els esquemes de terminació considerats son JTE mono-zona, FGR i una nova estructura RA-JTE que combina una JTE amb anells flotants. La terminació RA-JTE, amb una menor sensibilitat a desviacions del procés de fabricació i menor àrea consumida, ha aconseguit més del 90% de la tensió ideal i bona capacitat de bloqueig per dispositius de fins a 6,5 kV. Les millores realitzades a la cel·la del MOSFET de SiC afecten tant al disseny com al procés de fabricació. L’optimització de la cel·la bàsica s’ha realitzat mitjançant simulacions TCAD i l’avaluació de dades experimentals mesurades en estructures de test específiques. Les tècniques aplicades per a la millora del rendiment dels MOSFETs de SiC inclouen: i) l’ús d’un perfil de dopatge retrògrad pel pou p per obtenir un valor de Vth adequada alhora que s'evit, Postprint (published version)

Tesi per compendi d'articles, amb diferents seccions retallades per drets de l'editor., Although silicon (Si) is used in most current commercial power semiconductor components, Si capabilities are insufficient for new energy conversion requirements. Some of its important limitations are related with power losses, operation temperature, radiation hardness and switching speed. Then, new semiconductor materials must be developed to face the future global energetic challenges, overcoming Si intrinsic limitations. Silicon Carbide (SiC) is a proper wide bandgap (WBG) semiconductor with high critical electric field strength and a high saturation carrier’s drift velocity, which makes it able to sustain higher voltages with lower conduction losses. Furthermore, in a similar way to Si, SiC native oxide (SiO2) can be formed. However, a drawback of SiC MOSFETs is their poor oxide reliability and low channel mobility values attributed to a poor SiO2/SiC interface quality, with high density of interface traps (Dit) and near interface oxide traps (NIOTs). Nitridation processes, consisting in a nitric or nitrous oxide (NO, N2O) annealing is considered as the standard post oxidation annealing approach in 4H-SiC MOSFETs, being commonly used in commercial SiC power MOSFETs for reducing the Dit and NIOTs. However the nitridation interface passivation is not enough and, furthermore the limit of the improvement provided by nitridation has been reached. This thesis is focused on 4H-SiC-based power devices, particularly, on one of the major issues in SiC technology: to find a suitable and reliable fabrication process that improves the gate oxide and SiO2/SiC interface quality and reliability. Regarding electrical performances, we will focus on two of the major challenges of this field: the improvement of the inversion channel mobility, and the gate oxide stability, in order to further reduce the on-resistance and enhance the gate oxide reliability. Both problems are related to the defects near the SiO2/SiC interface. To meet these challenges and improve the current gate oxide, El silici (Si) és el semiconductor utilitzat en la majoria de components comercials de potència, no obstant, les seves propietats intrínseques són insuficients per als nous requeriments de conversió energètica, fent que sigui necessari el desenvolupament de nous materials semiconductors. Les seves limitacions estan relacionades amb les pèrdues tèrmiques, la temperatura de funcionament, la resistència a la radiació o la velocitat de commutació. Un material semiconductor adequat és el Carbur de Silici (SiC) el qual té un alt valor de camp elèctric crític i un alt valor de saturació de la velocitat de portadors, cosa que el fa capaç de mantenir altes tensions amb menors pèrdues per conducció. A més a més, com passa amb el Si, es pot formar diòxid de silici (SiO2) natiu sobre el SiC. Un inconvenient dels MOSFETs de SiC és la baixa fiabilitat del òxids i els baixos valors de mobilitat de canal, atribuïts a una mala qualitat de la interfície SiO2/SiC, que conté una alta densitat de trampes a la interfície (Dit) i al òxid proper a la interfície (NIOTs). Els MOSFETs comercials de 4H-SiC són sotmesos a un procés tèrmic standard post-oxidació. Aquest consisteix en un recuit en òxid nítric o òxid nitrós (NO, N2O), amb propòsit de reduir la Dit i els NIOTs. Tot i així, la passivació de la interfície assolida mitjançant la nitridació no és suficient i s'ha arribat al límit de millora que pot proporcionar aquest procediment. Aquesta tesi està dirigida a resoldre un dels principals problemes de la tecnologia en 4H-SiC: trobar un procés de fabricació adequat i fiable que millori la qualitat i la fiabilitat tant de l’òxid de porta com de la interfície SiO2/SiC, per a la seva aplicació en dispositius de potència. Pel que fa a les prestacions elèctriques, ens centrem en dos dels principals reptes d’aquest àmbit: la millora de la mobilitat del canal d’inversió i l’estabilitat de l’òxid de porta, per tal de reduir la resistència del canal drenador-font i millorar la fiabilitat de l’òxid, Postprint (published version)

La presente invención se refiere a un procedimiento de exfoliación y transferencia de grafeno de un sustrato de carburo de silicio dopado a otro sustrato, donde dicho procedimiento se basa en su exfoliación inducida por el burbujeo de hidrógeno que se produce en la electrolisis del agua. [ES], The present invention relates to a method for exfoliating and transferring graphene from a doped silicon carbide substrate to another substrate, the method being based on exfoliation induced by hydrogen bubbles produced in the electrolysis of water. [EN]

The present invention relates to a method for exfoliating and transferring graphene from a doped silicon carbide substrate to another substrate, the method being based on exfoliation induced by hydrogen bubbles produced in the electrolysis of water. [EN], La presente invención se refiere a un procedimiento de exfoliación y transferencia de grafeno de un sustrato de carburo de silicio dopado a otro sustrato, donde dicho procedimiento se basa en su exfoliación inducida por el burbujeo de hidrógeno que se produce en la electrolisis del agua. [ES]

Recording infraslow brain signals (<0.1 Hz) with microelectrodes is severely hampered by current microelectrode materials, primarily due to limitations resulting from voltage drift and high electrode impedance. Hence, most recording systems include high-pass filters that solve saturation issues but come hand in hand with loss of physiological and pathological information. In this work, we use flexible epicortical and intracortical arrays of graphene solution-gated field-effect transistors (gSGFETs) to map cortical spreading depression in rats and demonstrate that gSGFETs are able to record, with high fidelity, infraslow signals together with signals in the typical local field potential bandwidth. The wide recording bandwidth results from the direct field-effect coupling of the active transistor, in contrast to standard passive electrodes, as well as from the electrochemical inertness of graphene. Taking advantage of such functionality, we envision broad applications of gSGFET technology for monitoring infraslow brain activity both in research and in the clinic.

This is the first book dedicated exclusively to epitaxial graphene on silicon carbide (EG-SiC). It comprehensively addresses all fundamental aspects relevant for the study and technology development of EG materials and their applications, using quantum Hall effect studies and probe techniques such as scanning tunneling microscopy and atomic resolution imaging based on transmission electron microscopy. It presents the state of the art of the synthesis of EG-SiC and profusely explains it as a function of SiC substrate characteristics such as polytype, polarity, and wafer cut as well as the in situ and ex situ conditioning techniques, including H2 pre-deposition annealing and chemical mechanical polishing. It also describes growth studies, including the most popular characterization techniques, such as ultrahigh-vacuum, partial-pressure, or graphite-cap sublimation techniques, for high-quality controlled deposition. The book includes relevant examples on synthesis and characterization techniques as well as device fabrication processing and performance and complements them with theoretical modeling and simulation studies, which are helpful in the fundamental comprehension of EG-SiC substrates and their potential use in electronic applications. It addresses the fundamental aspects of EG-SiC using quantum Hall effect studies as well as probe techniques, such as scanning tunneling microscopy or atomic resolution imaging based on transmission electron microscopy. It comprises chapters that present reviews and vision on the current state of the art of experts in physics, electronic engineering, materials science, and nanotechnology from Europe and Asia.

This is the first book dedicated exclusively to epitaxial graphene on silicon carbide (EG-SiC). It comprehensively addresses all fundamental aspects relevant for the study and technology development of EG materials and their applications, using quantum Hall effect studies and probe techniques such as scanning tunneling microscopy and atomic resolution imaging based on transmission electron microscopy. It presents the state of the art of the synthesis of EG-SiC and profusely explains it as a function of SiC substrate characteristics such as polytype, polarity, and wafer cut as well as the in situ and ex situ conditioning techniques, including H2 pre-deposition annealing and chemical mechanical polishing. It also describes growth studies, including the most popular characterization techniques, such as ultrahigh-vacuum, partial-pressure, or graphite-cap sublimation techniques, for high-quality controlled deposition. The book includes relevant examples on synthesis and characterization techniques as well as device fabrication processing and performance and complements them with theoretical modeling and simulation studies, which are helpful in the fundamental comprehension of EG-SiC substrates and their potential use in electronic applications. It addresses the fundamental aspects of EG-SiC using quantum Hall effect studies as well as probe techniques, such as scanning tunneling microscopy or atomic resolution imaging based on transmission electron microscopy. It comprises chapters that present reviews and vision on the current state of the art of experts in physics, electronic engineering, materials science, and nanotechnology from Europe and Asia.

This paper reviews advanced gate dielectric processes for SiC MOSFETs. The poor quality of the SiO2/SiC interface severely limits the value of the channel field-effect mobility, especially in 4H-SiC MOSFETs. Several strategies have been addressed to overcome this issue. Nitridation methods are effective in increasing the channel mobility and have been adopted by manufacturers for the first generations of commercial power devices. Gate oxide doping techniques have also been successfully implemented to further increase the channel mobility, although device stability is compromised. The use of high-k dielectrics is also analyzed, together with the impact of different crystal orientations on the channel mobility. Finally, the performance of SiC MOSFETs in harsh environments is also reviewed with special emphasis on high temperature operation.

The invention concerns a method for producing a field effect transistor having a trench gate comprising: • - the forming (110) of at least one trench (11, 12, 13) in a semi-conductive substrate (1) having a first type of conductivity, said substrate comprising two opposing faces called front face and rear face, • - the primary implantation (120) of ions having a second type of conductivity so as to implant each trench of the substrate to form an active gate area, • - the depositing (160) of a layer of polycrystalline silicon having the second type of conductivity on the implanted active gate area, • - the oxidation (160) of the layer of polycrystalline silicon, and • - the metallisation (180) of the substrate on the front and rear faces of same in order to form active source and drain areas

[FR] L'invention concerne un procédé de fabrication d'un transistor à effet de champ de type à grille en tranchée comprenant : • - la formation (110) d'au moins une tranchée (11, 12, 13) dans un substrat semi-conducteur (1) d'un premier type de conductivité, ledit substrat comprenant deux faces opposées dite face avant et face arrière, • - l'implantation primaire (120) d'ions ayant un deuxième type de conductivité de sorte à implanter chaque tranchée du substrat pour former une région active de grille, • - le dépôt (160) d'une couche de silicium poly-cristallin du deuxième type de conductivité sur la région active de grille implantée, • - l'oxydation (160) de la couche de silicium poly-cristallin, et • - la métallisation (180) du substrat sur ses faces avant et arrière pour former des régions actives de source et de drain, [EN] The invention concerns a method for producing a field effect transistor having a trench gate comprising: • - the forming (110) of at least one trench (11, 12, 13) in a semi-conductive substrate (1) having a first type of conductivity, said substrate comprising two opposing faces called front face and rear face, • - the primary implantation (120) of ions having a second type of conductivity so as to implant each trench of the substrate to form an active gate area, • - the depositing (160) of a layer of polycrystalline silicon having the second type of conductivity on the implanted active gate area, • - the oxidation (160) of the layer of polycrystalline silicon, and • - the metallisation (180) of the substrate on the front and rear faces of same in order to form active source and drain areas

La invención se refiere a un método para producir un transistor de efecto de campo que tiene una puerta de zanja que comprende:. - la formación (110) de al menos una zanja (11, 12, 13) en un sustrato semiconductor (1) que tiene un primer tipo de conductividad, comprendiendo dicho sustrato dos caras opuestas llamadas cara frontal y cara posterior,. - la implantación primaria (120) de iones que tienen un segundo tipo de conductividad para implantar cada zanja del sustrato para formar un área de compuerta activa,. - el depósito (160) de una capa de silicio policristalino que tiene el segundo tipo de conductividad en el área de la compuerta activa implantada,. - la oxidación (160) de la capa de silicio policristalino, y. - la metalización (180) del sustrato en las caras delantera y trasera del mismo para formar una fuente activa y áreas de drenaje.

La presente invención comprende un procedimiento para producir láminas de cobre con estructura cuasi-monocristalina, y un procedimiento de producción de grafeno de alta calidad utilizando dichas láminas de cobre como sustrato catalizador. También comprende una lámina de cobre para la producción de grafeno, obtenida por el procedimiento descrito en la presente invención, que presenta una estructura cuasi-monocristalina.

La presente invención comprende un procedimiento para producir láminas de cobre con estructura cuasi-monocristalina, y un procedimiento de producción de grafeno de alta calidad utilizando dichas láminas de cobre como sustrato catalizador. También comprende una lámina de cobre para la producción de grafeno, obtenida por el procedimiento descrito en la presente invención, que presenta una estructura cuasi-monocristalina.

Graphene exhibits outstanding electronic properties such as high carrier mobility and ballistic transport at room temperature. However, the lack of bandgap and the absence of an affordable method for its mass scale production are still major hurdles for its full exploitation in the field of electronics. Controlled synthesis of high quality graphene on silicon carbide (SiC) substrates points out that this technique is a competitive approach for producing wafer-scale epitaxial graphene (EG). Remarkably, EG on SiC shows major advantages compared with other methods, e.g. CVD graphene, such as cost efficient compatibility with complementary metal–oxide–semiconductor (CMOS) technology. Beyond EG deposition by SiC graphitization, applying advanced device fabrication, such as novel strategies based on ion implantation and homoepitaxial growth of doped SiC on top of a semi-insulating SiC buffer layer have opened a new avenue to develop e.g. back-gated graphene transistors. In this talk, we will summarize several of our recent advances in the synthesis and device technology on EG on SiC. For instance, our technology development results reflect our capability to create a buried implanted layer in SiC substrates at determined depth compatible with EG. This architecture enables back gate control of graphene electronic devices. The resources of Graphene Nanotech (GPNT), a startup company emerged from the collaboration between the Institute of Microelectronics of Barcelona (IMB-CNM-CSIC), the Institute of Nanoscience of Aragon (INA), and the Aragon Material Science Institute (ICMA), will be fully introduced. GPNT is devoted to fabrication and characterization of EG and EG-based devices, and offers its know-how to both academia and industry.

It seems that we are entering the era of two dimensional materials, that ever since they have been isolated showed amazing potential for developing new devices based on their extraordinary properties. When it comes to industrialization and commercialization, two main issues have to be faced: utilization of reproducible and affordable standardized manufacturing processes and high quality of the final product. For that purpose, we fabricate graphene by selective sublimation of Silicon Carbide (SiC), using an optimized protocol developed in our company. Our typical graphene layers grown on Si face SiC present mobilities in the range of 3000-4000 cm2 V-1s-1 at room temperature and up to almost 40000 at low temperature. Furthermore, pursuing the inclusion of graphene in the field of electronics, we produced a novel graphene product grown on top of pre-processed SiC substrates with a buried conducting layer at a depth of 300 nm, formed by ion implantation. By these means, we can provide a substrate where graphene can be easily back gated by biasing the semiconductor buried layer. Our quality inspections, in terms of Raman investigations, revealed that we obtained SiC substrates covered with more than 75% of graphene of superior quality. Moreover, measurements performed on Hall bar devices fabricated along the SiC terraces corroborated those results. That is: mobilities of the electrons as high as 8000 cm2 V-1s-1 at low temperature and 2800 cm2 V-1s-1 at RT, as well as, low magnetic field plateaux on the Quantum Hall Effect have been observed. Even if these performances are pretty good in this first generation material, the pre-processing of the semiconductor substrate is still impacting the graphene performances and we are working to improve the SiC processing to reach the electrical values obtained on graphene grown on virgin SiC substrates. All those premises make our graphene an ideal candidate to overcome the difficulties in bringing its potential to the desired indus

Silicon (Si) power device’ technologies have reached a high maturity level, but current limitations on mechanic, temperature operation and electric performances require to investigate other semiconductor materials that can potentially compete with and overcome those border issues. This is the case of Silicon Carbide (SiC) and Gallium Nitride (GaN) which are becoming serious competitors to the Si due to their superior physical properties. Concerning SiC, the 4Hpolytype seems to be the best suitable candidate for high power MOSFETs according to its band gap, electric field strength, electron bulk mobility, and attainable threshold voltage, among others. But still, technological processes must be optimized in order to SiC MOSFETS can compete with their Si counterparts. This is the case of the gate oxidation process. A reduction of interface charge density is required for threshold voltage stability, and further improvements of the interface quality are also needed for high inversion mobility values. Once solved these problems, a path toward new perspectives of high power applications will be opened. This work is the direct continuation of the Aurore Constant’s work. It is focused on 4HSiC based devices, more specifically on the gate oxidation processes and their behaviour under different harsh environments. Up to now, most of the works carried out were focused on the improvement of the Silicon Dioxide-Silicon Carbide (SiO2/SiC) interface quality. Solving those problems would allow designing high-speed and low-switching losses MOSFETs. In the past work, the main strength was focused on a new surface pre-treatment and on a gate oxidation process. Results showed improved electrical performances. However, we are convinced that better values can be obtained by optimizing the post-oxidation annealing step, by performing surface counter doping or by performing special irradiation treatments. All the efforts of this work will oriented to the development of reliable SiC MOSFETs, Las tecnologías de dispositivos de potencia en silicio (Si) han alcanzado una gran madurez. Sin embargo, las limitaciones del Si debidas a sus restricciones mecánicas, térmicas y eléctricas hacen necesario otros materiales semiconductores que puedan competir con el Si y superar sus limitaciones. Este es el caso del Carburo de Silicio (SiC) y del Nitruro de Galio (GaN) que ya comienzan a ser serios competidores del Si debido a sus mejores propiedades físicas. En lo que respecta al SiC, el politipo 4H es el candidato más adecuado para la integración de MOSFETs de potencia debido, entre otros, a los valores del bandgap, campo eléctrico crítico, movilidad volumíca de los electrones y tensión umbral alcanzable. A pesar de estas ventajas teóricas del material, es necesario optimizar cada uno de los procesos tecnológicos involucrados en la fabricación de un MOSFET en SiC para que realmente pueda competir con su contrapartida en Si. Este es el caso del proceso de oxidación para la formación del dieléctrico de puerta. Concretamente, una buena estabilidad de la tensión umbral del componente requiere disminuir la densidad de cargas en la interfase óxido/semiconductor, y mejoras adicionales en la calidad de esta interfase son también necesarias para obtener altos valores de la movilidad de los portadores en el canal de inversión. La solución de los problemas tecnológicos anteriormente enunciados abrirá nuevas perspectivas a las aplicaciones de alta potencia. Este trabajo es una continuación directa del de Aurore Constant. Se centra en dispositivos basados en 4H-SiC, y más específicamente en los procesos de oxidación de puerta, y de sus comportamientos eléctricos en diferente ambientes de trabajo hostiles. Hasta la fecha, la mayor parte de la investigación se ha centrado en la mejora de la calidad de la interfase dióxido de silicio/carburo de silicio (SiO2/SiC). La solución de estos problemas debería permitir el diseño de MOSFETs muy rápidos y con pérdidas de conmutación muy baj, Postprint (published version)

The invention concerns a method for producing a field effect transistor having a trench gate comprising: • - the forming (110) of at least one trench (11, 12, 13) in a semi-conductive substrate (1) having a first type of conductivity, said substrate comprising two opposing faces called front face and rear face, • - the primary implantation (120) of ions having a second type of conductivity so as to implant each trench of the substrate to form an active gate area, • - the depositing (160) of a layer of polycrystalline silicon having the second type of conductivity on the implanted active gate area, • - the oxidation (160) of the layer of polycrystalline silicon, and • - the metallisation (180) of the substrate on the front and rear faces of same in order to form active source and drain areas

[EN] Method for manufacturing at least one flexible, biocompatible and implantable neuronal microprobe, which comprises the steps of: providing a rigid substrate layer (100); providing a soluble polymer layer (110) on said rigid substrate layer; providing a first polymer layer (130); etching at least one opening (151; 152) in said first polymer layer; providing a two-dimensional conductive layer (160) on said first polymer layer; etching at least one microelectrode having at least one contact area in said two-dimensional conductive layer; providing a finishing assembly (195) on the microelectrode; and dissolving said soluble polymer in a solution (120). The resulting microelectrode (160) is sandwiched between two polymer layers (190, 195), one of which comprises an opening (151; 152) for accessing said contact area., [ES] Procedimiento de fabricación de al menos una micro-sonda neuronal flexible, biocompatible e implantable, que comprender las etapas de: proporcionar una capa de un sustrato rígido (100); proporcionar una capa de un polímero soluble (110) sobre dicha capa de sustrato rígido; proporcionar una capa de un primer polímero (130); grabar en dicha capa de primer polímero al menos una abertura (151; 152); proporcionar una capa de un material conductor bidimensional (160) sobre dicha capa de primer polímero; grabar en dicha capa de material conductor bidimensional al menos un microelectrodo provisto de al menos un área de contacto; proporcionar un ensamblaje de acabado (195) sobre microelectrodo; y disolver dicho polímero soluble en una solución (120). El microelectrodo resultante (160) queda intercalado entre dos capas de material polimérico (190, 195), una de las cuales comprende una abertura (151; 152) para acceder a dicha área de contacto.

Procedimiento de fabricación de al menos una micro-sonda neuronal flexible, biocompatible e implantable, que comprender las etapas de: proporcionar una capa de un sustrato rígido (100); proporcionar una capa de un polímero soluble (110) sobre dicha capa de sustrato rígido; proporcionar una capa de un primer polímero (130); grabar en dicha capa de primer polímero al menos una abertura (151; 152); proporcionar una capa de un material conductor bidimensional (160) sobre dicha capa de primer polímero; grabar en dicha capa de material conductor bidimensional al menos un microelectrodo provisto de al menos un área de contacto; proporcionar un ensamblaje de acabado (195) sobre microelectrodo; y disolver dicho polímero soluble en una solución (120). El microelectrodo resultante (160) queda intercalado entre dos capas de material polimérico (190, 195), una de las cuales comprende una abertura (151; 152) para acceder a dicha área de contacto.

Procedimiento de fabricación de al menos una micro-sonda neuronal flexible, biocompatible e implantable, que comprende las etapas de: proporcionar una capa de un sustrato rígido; proporcionar una capa de un polímero soluble sobre dicha capa de sustrato rígido; proporcionar una capa de un primer polímero; grabar en dicha capa de primer polímero al menos una abertura; proporcionar una capa de un material conductor bidimensional sobre dicha capa de primer polímero; grabar en dicha capa de material conductor bidimensional al menos un microelectrodo provisto de al menos un área de contacto; proporcionar un ensamblaje de acabado sobre dicho ensamblaje de microelectrodo; y disolver dicho polímero soluble en una solución. La micro-sonda resultante queda intercalada entre dos capas de material polimérico, una de las cuales comprende una abertura para acceder a dicho área de contacto.