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With the development of high-density integrated chips, low-k dielectric materials are used in the back end of line (BEOL) to reduce signal delay. However, due to the application of fine-pitch packages with high-hardness copper pillars, BEOL is susceptible to chip package interaction (CPI), which leads to reliability issues such as the delamination of interlayer dielectric (ILD) layers. In order to improve package reliability, the effect of CPI at multi-scale needs to be explored in terms of package integration. In this paper, the stress of BEOL in the flip-chip chip-scale packaging (FCCSP) model during thermal cycling is investigated by using the finite-element-based sub-model approach. A three-dimensional (3D) multi-level finite element model is established based on the FCCSP. The wiring layers were treated by the equivalent homogenization method to ensure high prediction accuracy. The stress distribution of the BEOL around the critical bump was analyzed. The cracking risk of the interface layer of the BEOL was assessed by pre-cracking at a dangerous location. In addition, the effects of the epoxy molding compound (EMC) thickness, polyimide (PI) opening, and coefficient of thermal expansion (CTE) of the underfill on cracking were investigated. The simulation results show that the first principal stress of BEOL is higher at high-temperature moments than at low-temperature moments, and mainly concentrated near the PI opening. Compared with the oxide layer, the low-k layer has a higher risk of cracking. A smaller EMC thickness, lower CTE of the underfill, and larger PI opening help to reduce the risk of cracking in the BEOL. [ABSTRACT FROM AUTHOR]

In this paper, nano-silver and nano-silver coated tin solder joints with hot pressing bonding conditions of 250 °C, 2 min and 15 MPa were selected to study the shear strength of solder joints and their service reliability under hot cycling conditions. The main conclusions are as follows: The addition of nano-tin plays a dispersion strengthening role, which increases the shear strength of nano-silver solder joint from 40 MPa to 50 MPa. After thermal cycling, the main failure mode of the nano-silver-coated tin solder joints is ductile fracture. The main failure mode of the nano-silver solder joints is brittle fracture, firstly, the delamination appears at the interface, and then the crack passes through the outer side of the solder joints, showing cleavage fracture of the grain. The thermal fatigue life of the nano-silver solder joint is 145 cycles, and the thermal fatigue life of the nano-silver-coated tin solder joint is 175 cycles. [ABSTRACT FROM AUTHOR]

To satisfy the strict demands of 5G radio frequency communication, we propose high-quality, flexible temperature-compensated single-crystalline AlN film bulk acoustic wave resonators (TC-SABARs) based on a 6-inch sapphire substrate. An AlGaN sacrificial layer and a 600-nm-thick single-crystalline AlN epitaxial layer are deposited on a sapphire substrate by metal organic chemical vapor deposition (MOCVD). Two types of TC-SABARs are fabricated and their performances are compared with published results. The results indicate that one of the TC-SABARs has a maximum Bode Q of 3406, an effective coefficient ( K eff 2 ) of 6.21%, and a temperature coefficient of frequency (TCF) of −9.5 ppm/°C. The other TC-SABAR exhibits a maximum Bode Q of 3022, a K eff 2 of 5.99%, and a TCF of +0.7 ppm/°C. This performance can be attributed to the high-quality single-crystalline AlN film and the temperature-compensation structure with nonmetallic flip-chip bonding film transfer process and a thick SiO2 layer. [ABSTRACT FROM AUTHOR]

With the advancement of high-integration and high-density interconnection in chip manufacturing and packaging, Cu bumping technology in wafer- and panel- level packaging is developed to micrometer-sized structures and pitches to accommodate increased I/O numbers on high-end integrated circuits. Driven by this industrial demand, significant efforts have been dedicated to Cu electroplating techniques for improved pillar shape control and solder joint reliability, which substantially depend on additive formulations and electroplating parameters that regulate the growth morphology, crystal structure, and impurity incorporation in the process of electrodeposition. It is necessary to investigate the effect of an additive on Cu pillar electrodeposition, and to explore the Kirkendall voids formed during the reflowing process, which may result from the additive-induced impurity in the electrodeposited Cu pillars. In this work, a self-synthesized polyquaterntum (PQ) was made out with dual suppressor and leveler effects, and was combined with prototypical accelerator bis- (sodium sulfopropyl)-disulfide (SPS) for patterned Cu pillar electroplating. Then, Sn96.5/Ag3.0/Cu0.5 (SAC305) solder paste were screen printed on electroplated Cu pillars and undergo reflow soldering. Kirkendall voids formed at the joint interfaces were observed and quantified by SEM. Finally, XRD, and EBSD were employed to characterize the microstructure under varying conditions. The results indicate that PQ exhibits significant suppressive and levelled properties with the new structure of both leveler and suppressor. However, its effectiveness is dependent on liquid convection. PQ and SPS work synergistically, influencing the polarization effect in various convective environments. Consequently, uneven adsorption occurs on the surface of the Cu pillars, which results in more Kirkendall voids at the corners than at the center along the Cu pillar surface. [ABSTRACT FROM AUTHOR]

Currently, the high-speed performance of thin-film lithium niobate electro-optic modulator chips is evolving rapidly. Nevertheless, due to the inherent technical limitations imposed by the packaging design and material architecture, the intrinsic electro-optic bandwidth of thin-film lithium niobate electro-optic modulator chips often exceeds the bandwidth of their packaging interfaces, which can constrain the realization of modulation performance. Bump bonding emerges as a high-bandwidth EO interconnection technology, outperforming wire bonding for faster optical communication. In this paper, we present a high-speed thin-film lithium niobate modulator chip tailored for concave–convex bonding, alongside an analysis and design of the chip's flip-chip bonding packaging. By exploiting the superior electrical characteristics of concave–convex bonding, we effectively mitigate the radio frequency losses of modulator chip and packaging. The simulated half-wave voltage (Vπ) of 3.5 V and E-O modulation bandwidth greater than 150 GHz is obtained for a 0.5 cm long modulator after flip-chip bonding packaging. [ABSTRACT FROM AUTHOR]

As an essential part of integrated circuit, chip manufacturing has increasingly demanding requirements for quality, cost and others. Some technical limitations and the development direction of miniaturisation and high density have led to defects in the manufacturing process, which affect the performance and life of the chip. Therefore, the detection, identification and classification of defects are very important to improve the chip reliability. Based on the orderly and concise literature research, this paper focuses on a comprehensive review of the main research results in the field of non-contact non-destructive testing imaging methods for chip defects. Firstly, various defects that may occur in the chip design and packaging process are introduced. Then the contact detection methods including manual and probe method are clarified, and the principles, properties and development applications of NDT methods are introduced in detail, also the defect identification methods after imaging are briefly introduced. Moreover, the advantages and limitations of NDT technologies are summarised through comparative studies. Finally, the future development trend of non-destructive testing methods is predicted. This work hopes to provide some reference for the non-destructive testing of chips, which is of great significance for the health testing of chips in the electronics manufacturing industry. [ABSTRACT FROM AUTHOR]

The article explores the roadmap to neuromorphic computing with a focus on emerging technologies, challenges, and potential solutions in the field. It discusses the significance of materials engineering, various approaches to neuromorphic research, and the importance of balancing performance with sustainability. The text also delves into the potential of 2D-LMs in mimicking synapses and neurons in artificial neural networks, highlighting the stable resistive switching observed in certain materials. Efforts are ongoing to address challenges and further advance the use of 2D-LMs in neuromorphic computing, offering promising solutions to computational challenges faced by traditional digital computers. [Extracted from the article]

We present mutual optical coupling in terahertz (THz) quantum cascade wire laser arrays that are flip-chip bonded to a dielectric substrate. The mounting substrate is patterned for individual electrical contacting of each wire laser of the array. The resulting sandwich-like structure supports wire laser modes with a significant part propagating outside the cavity and mediates the long range coupling. The evanescent field part of the modes couples to the adjoining ridge, which, in turn, leads to mutual optical injection-locking between them. We demonstrate this effect for both geometrically similar and dissimilar wire lasers when biased in pulsed operation with temporally overlapping bias pulses. Finite element simulations confirm our measurement results. By applying time-shifted bias pulses to individual array elements, a controllable optical injection seeding of the wire cavity is achieved. We observe intensity modification of the laser modes with changing bias pulse overlap as a result of the injection locking. By choosing both the physical spacing of the laser ridges and the intensity of the seeding laser correctly, the relative intensities of the favored lasing modes are enhanced up to 95 percent. Understanding the coupling in THz wire laser arrays is important for future device improvements in terms of higher continuous-wave operating temperatures through better thermal dissipation, and higher output power and an improved far field due to controlled coupling of their modes. [ABSTRACT FROM AUTHOR]

The demand for high-performance electromechanical resonators is ever-growing across diverse applications, ranging from sensing and time-keeping to advanced communication devices. Among the electromechanical materials being explored, thin-film lithium niobate stands out due to its strong piezoelectric properties and low acoustic loss. However, in nearly all existing lithium niobate electromechanical devices, the configuration is such that the electrodes are in direct contact with the mechanical resonator. This configuration introduces an undesirable mass-loading effect, producing spurious modes and additional damping. Here, we present an electromechanical platform that mitigates this challenge by leveraging a flip-chip bonding technique to separate the electrodes from the mechanical resonator. By offloading the electrodes from the resonator, our approach yields a substantial increase in the quality factor of these resonators, paving the way for enhanced performance and reliability for their device applications. [ABSTRACT FROM AUTHOR]

Hydraulic technology with smaller sizes and higher reliability trends, including fault prediction and intelligent control, requires high-performance temperature and pressure-integrated sensors. Current designs rely on planar wafer- or chip-level integration, which is limited by pressure range, chip size, and low reliability. We propose a small-size temperature/high-pressure integrated sensor via the flip-chip technique. The pressure and temperature units are arranged vertically, and the sensing signals of the two units are integrated into one plane through silicon vias and gold–gold bonding, reducing the lateral size and improving the efficiency of signal transmission. The flip-chip technique ensures a reliable electrical connection. A square diaphragm with rounded corners is designed and optimised with simulation to sense high pressure based on the piezoresistive effect. The temperature sensing unit with a thin-film platinum resistor measures temperature and provides back-end high-precision compensation, which will improve the precision of the pressure unit. The integrated chip is fabricated by MEMS technology and packaged to fabricate the extremely small integrated sensor. The integrated sensor is characterised, and the pressure sensor exhibits a sensitivity and sensitivity drift of 7.97 mV/MPa and −0.19% FS in the range of 0–20 MPa and −40 to 120 °C. The linearity, hysteresis, repeatability, accuracy, basic error, and zero-time drift are 0.16% FS, 0.04% FS, 0.06% FS, 0.18% FS, ±0.23% FS and 0.04% FS, respectively. The measurement error of the temperature sensor and temperature coefficient of resistance is less than ±1 °C and 3142.997 ppm/°C, respectively. The integrated sensor has broad applicability in fault diagnosis and safety monitoring of high-end equipment such as automobile detection, industrial equipment, and oil drilling platforms. [ABSTRACT FROM AUTHOR]

Eco‐friendly and low‐cost aluminum gallium nitride (AlGaN) for the epitaxial growth of ultraviolet‐B (UVB) light‐emitting diodes (LEDs) on c‐Sapphire has the possibility of high external‐quantum efficiency (EQE). In this review paper a special growth techniques for 50% relaxed and 4 μm thick AlGaN buffer layer underneath the multi‐quantum wells (MQWs) are challenged to achieve a maximum internal‐quantum efficiency of 50–57% in 310–290 nm band UVB LEDs. The influence of a thin "Valley" layer in p‐type multi‐quantum barrier electron‐blocking layer on 2D hole generation and injection via intraband tunneling was attempted. Finally, the influence of soft polarized Mg‐doped p‐type Al‐graded AlGaN hole injection layer assisted by excimer laser annealing for better hole injection toward the MQWs was investigated and quite high hole concentration of 2 × 1016 cm−3 and resistivity of 24 Ω‐cm at room temperature was achieved. Consequently, the EQE of transparent 310 and 304 nm UVB LEDs, respectively, reached to a confirmed world record values of ≈5% and ≈10% with light powers of 29 and 40 mW on wafer. This EQE value can surpass 21% if flip‐chip, nanoPSS, photonic crystal, and lens with highly reflective p‐electrodes are incorporated in LED. [ABSTRACT FROM AUTHOR]

Purpose: The purpose of this study is to propose a simplifying approach for modelling a reliability test. Modelling the reliability tests of printed circuit board (PCB)/microelectronic component assemblies requires the adoption of several simplifying assumptions. This study introduces and validates simplified assumptions for modeling a four-point bend test on a PCB/wafer-level chip scale packaging assembly. Design/methodology/approach: In this study, simplifying assumptions were used. These involved substituting dynamic imposed displacement loading with an equivalent static loading, replacing the spherical shape of the interconnections with simplified shapes (cylindrical and cubic) and transitioning from a three-dimensional modelling approach to an equivalent two-dimensional model. The validity of these simplifications was confirmed through both quantitative and qualitative comparisons of the numerical results obtained. The maximum principal plastic strain in the solder balls and copper pads served as the criteria for comparison. Findings: The simplified hypotheses were validated through quantitative and qualitative comparisons of the results from various models. Consequently, it was determined that the replacement of dynamic loading with equivalent static loading had no significant impact on the results. Similarly, substituting the spherical shape of interconnections with an equivalent shape and transitioning from a three-dimensional approach to a two-dimensional one did not substantially affect the precision of the obtained results. Originality/value: This study serves as a valuable resource for researchers seeking to model accelerated reliability tests, particularly in the context of four-point bending tests. The results obtained in this study will assist other researchers in streamlining their numerical models, thereby reducing calculation costs through the utilization of the simplified hypotheses introduced and validated herein. [ABSTRACT FROM AUTHOR]

Bonding distance is defined by the projected distance on a substrate plane between two solder points of a bonding wire, which can directly affect the morphology of the bonding wire and the performance between internal components of the chip. For the inspection of the bonding distance, it is necessary to accurately recognize gold wires and solder points within the complex imagery of the chip. However, bonding wires at arbitrary angles and small-sized solder points are densely distributed across the complex background of bonding images. These characteristics pose challenges for conventional image detection and deep learning methods to effectively recognize and measure the bonding distances. In this paper, we present a novel method to measure bonding distance using a hierarchical measurement structure. First, we employ an image acquisition device to capture surface images of integrated circuits and use multi-layer convolution to coarsely locate the bonding region and remove redundant background. Second, we apply a multi-branch wire bonding inspection network for detecting bonding spots and segmenting gold wire. This network includes a fine location branch that utilizes low-level features to enhance detection accuracy for small bonding spots and a gold wire segmentation branch that incorporates an edge branch to effectively extract edge information. Finally, we use the bonding distance measurement module to develop four types of gold wire distribution models for bonding spot matching. Together, these modules create a fully automated method for measuring bonding distances in integrated circuits. The effectiveness of the proposed modules and overall framework has been validated through comprehensive experiments. [ABSTRACT FROM AUTHOR]

Quantum dots have been rapidly developed in the display field, especially as photoluminescent color conversion layers. At the same time, quantum dots have also made increasing research progress in the detection field. We reported a short‐wave infrared sensor based on colloidal quantum dot technology. The photosensitive layer of the sensor uses HgTe colloidal quantum dot material. The detection band is 0.9~1.7um, the resolution is 1280*1024, and the pixel pitch is 15um. Colloidal quantum dot short‐wave infrared sensors get rid of the limitations of the indium pillar flip‐chip bonding process of traditional indium gallium arsenide CMOS short‐wave infrared focal plane sensors. The preparation process is simple, the yield is higher, and the cost is low. Based on the colloidal quantum dot shortwave infrared sensor, we implemented a shortwave infrared camera and characterized its performance parameters, and then we successfully captured shortwave infrared images through the shortwave infrared camera. [ABSTRACT FROM AUTHOR]

Performance, reliability, and costs are the three core attributes of any integrated circuits (IC) and microelectronics system products. Continuous advances of microsystem chips have been made possible by relentless physical scaling-down in IC technologies, predominantly in complementary metal-oxide-semiconductor (CMOS). Rapid ending of Moore's Law calls for smart futuristic chips, toward which CMOS+X heterogeneous integration emerges as the main and viable pathway where X represents various innovative, nontraditional technologies and devices to be hetero-integrated into Si CMOS platform to deliver superior system performance with rich functional diversities and ultra robust reliability at affordable costs. This mini-review discusses a few emerging CMOS+X technology advances addressing the performance and reliability challenges for advanced IC chips, including vertical magnetic-cored inductive devices for single-chip radio frequency IC integration, in the backend-of-the-line metal wall isolation to suppress flying noises in complex CMOS ICs, and nano crossbar array and graphene-based on-chip electrostatic discharge protection structures as design-for-reliability solutions for advanced chips. [ABSTRACT FROM AUTHOR]

A novel hybrid bandpass filter (BPF) with wideband and high selectivity is proposed in this paper. The hybrid BPF is composed of two film bulk acoustic resonator (FBAR) cells and three lumped component resonators realized by the integrated passive device (IPD) technology. The ABCD matrix to S-parameters matrix method is used to calculate the frequency response of the BPF. Moreover, the expressions of transmission zeros (TZs) have been extracted. In the design process, an iterative design approach is proposed to improve the circuit and layout of the hybrid filter based on the packaged acoustic-electric hybrid simulation effect. Finally, two parts of the filter are packaged based on the flip-chip method, and two prototypes for the BPF are measured. The measured results of two chips with 3 dB fractional bandwidth of 13.7% and 15.8% are designed and fabricated, which verifies the validity of the proposed design principle. [ABSTRACT FROM AUTHOR]

In this work, Sn-0.7Cu-WO3 nanomodified solders were electrodeposited from an aqueous acidic plating bath containing various fractions of WO3 nanoparticles (0.1, 0.25, 0.5 wt%) NPs for mini-light emitting diodes (mini-LEDs) packaging. The produced nanomodified solders were characterized for their morphology, microhardness, melting point, and electrical resistivity. Further, the nanomodified solder bumps were used to mount a 1608 mini-LED chip/ENIG (Electroless Nickel Immersion Gold) pad by reflowing at 240 °C in the air. High-temperature aging was done at 125 °C for 144, 256, and 400 h and joint shear tests were performed to examine the interfacial properties and growth kinetics of the soldered mini-LED/Sn-0.7Cu-WO3/ENIG joints. The results indicated the formation of (Ni,Cu)3Sn4 intermetallic compounds (IMCs) across the solder/ ENIG pad joint. The thickness of the IMC layer decreases showing the maximum rate of decrease when the composition is Sn-0.7Cu-0.25WO3. It was concluded that the optimal set of microstructure, melting point, electrical resistivity, and joint shear reliability could be achieved when the nanomodified solder is reinforced with 0.25 wt.% WO3 NPs into Sn-0.7Cu matrix and thus it can be a potential contestant for the upcoming applications in mini-LED packaging. [ABSTRACT FROM AUTHOR]

In the DC-6 GHz band, low-insertion-loss packaging materials were investigated to effectively reduce the heat generated during the working process of the attenuation chip. Based on the working principle of the attenuation chip, when the signal passes through the attenuation chip resistor network, it results in energy loss. This means that the insertion loss of the chip generates heat, which leads to an uneven heat dissipation of the chip and thus functional failure. The microwave characteristics of the packaged joints were investigated using different packaging techniques. The results show that the S21 and S11 of the attenuation chip after nano-silver and Au80Sn20 packaging are optimal in the frequency band of DC-6 GHz, and the insertion loss is low compared with the commonly used packaging materials Sn60Pb40 and Sn96.5Ag3.5, which reduces the heat loss and improves the reliability of the attenuation chip packaging. [ABSTRACT FROM AUTHOR]

This article investigates the failure mode and mechanism of copper pillar solder joints in temperature cycling experiments, focusing on a Cu/nano Ag/Cu solder joint structure. The hot pressing bonding condition at 300 °C with insulation for 10 s is chosen for the experiments. Based on the life test results, the thermal cycling fatigue life of the nanosilver solder joint is determined to be 2050 cycles. To gain further insights, finite element software ANSYS is employed to simulate nanosilver solder joints in flip chips, revealing the stress–strain distribution within the solder joints. The simulation utilizes the Anand viscoplastic constitutive model for the solder joint, providing a reasonable representation of the stress–strain behavior under thermal cycling load. Notably, the simulation highlights that the maximum stress and strain occur in the contact area between the solder joint and the copper column. To enhance accuracy, the calculation equation is refined using relevant experience, resulting in a prediction of the thermal fatigue life of nanosilver solder joints. This prediction aligns closely with the experimental results. The research outcomes not only contribute valuable insights into the behavior of nanosilver solder but also serve as a reference for its application in electronic packaging. [ABSTRACT FROM AUTHOR]

Recent years have witnessed significant advancements in deep learning-based 3D object detection, leading to its widespread adoption in numerous applications. As 3D object detectors become increasingly crucial for security-critical tasks, it is imperative to understand their robustness against adversarial attacks. This paper presents the first comprehensive evaluation and analysis of the robustness of LiDAR-based 3D detectors under adversarial attacks. Specifically, we extend three distinct adversarial attacks to the 3D object detection task, benchmarking the robustness of state-of-the-art LiDAR-based 3D object detectors against attacks on the KITTI and Waymo datasets. We further analyze the relationship between robustness and detector properties. Additionally, we explore the transferability of cross-model, cross-task, and cross-data attacks. Thorough experiments on defensive strategies for 3D detectors are conducted, demonstrating that simple transformations like flipping provide little help in improving robustness when the applied transformation strategy is exposed to attackers. Finally, we propose balanced adversarial focal training, based on conventional adversarial training, to strike a balance between accuracy and robustness. Our findings will facilitate investigations into understanding and defending against adversarial attacks on LiDAR-based 3D object detectors, thus advancing the field. The source code is publicly available at https://github.com/Eaphan/Robust3DOD. [ABSTRACT FROM AUTHOR]

A high gain D‐band hybrid integrated on‐chip antenna (OCA) based on a low‐cost printed circuit board (PCB) packaging technology is analyzed and designed in a standard 40‐nm CMOS process in this paper. The proposed OCA is a hybrid structure of a slotted patch OCA with off‐chip PCB ground and off‐chip dielectric resonator (DR). The proposed OCA exhibits a simulated gain of 3.5 dBi and 53% radiation efficiency at 150 GHz. The simulated impedance bandwidth is 20 GHz. The radiation performance and impedance bandwidth of the OCA are observably improved with the proposed techniques. The proposed OCA occupies 0.52 × 0.56 mm2, and addresses the highly desirable yet challenging overall design of future low‐cost integrated millimeter‐wave (mm‐Wave) and terahertz (THz) systems, which hit the mark on cost and compatibility. [ABSTRACT FROM AUTHOR]

The quick development of intelligent information technology in modern society has accelerated education informatisation. Accordingly, the traditional modes of instruction and methods of instruction are no longer able to satisfy the educational needs of modern society, so the flipped classroom teaching method emerges at the historic moment. While injecting fresh vitality into education, this model can also reflect good teaching effects, which is of enormous practical relevance to the development of education. Additionally, flipped classroom teaching is made possible by the online teaching resources offered by colleges and institutions. In view of the unreasonable distribution of curriculum resources in the current university network teaching platform, this study proposes a university network platform combining flipped classroom teaching mode and improved Apriori algorithm. First of all, to achieve the acceptable allocation and suggestion of learning materials in accordance with students' learning demands, the Apriori algorithm is introduced to address the university network teaching platform's lack of adequate planning and organisation. After that, the flipped classroom teaching mode is introduced into the online teaching platform for empirical research. According to the trial findings, more than 90.22 % of the students had improved their study habits. The network teaching platform proposed by the research institute can stimulate college students' learning interest and improve their learning ability to a certain extent. [ABSTRACT FROM AUTHOR]

A new type of copper (Cu)‑rhodium (Rh)‑alloy, Cu(Rh), films is developed by co‑sputtering copper and rhodium onto silicon (Si) substrates under an argon (Ar) atmosphere. The new films are next annealed at 600 and 670 °C, or alternatively at 100 and 450 °C, for 1 h. Longer annealing to the films, for up to 8 days, is also conducted to explore resistivity variation. The resistivity of the new 300‑nm‑thick film is 2.19 μΩ cm after annealing at 670 °C for 1 h and drifts to 2.26 and 2.14 μΩ after annealing at 400 and 450 °C, respectively, for 200 h. A 2.7‑μm‑thick Sn layer is then thermally evaporated atop the new film for stable flip‑chip solder joints; their metal and Cu‑Sn intermetallic compound (IMC) growth processes vs. various annealing periods are tested. After annealing at 670 °C, the new 300‑nm‑thick film’s adhesive strength reaches 44.2 ± 0.01 MPa, which is 11 ~ 12‑fold that of their pure Cu counterpart. Some key test results of the new film are disclosed herein, including its X‑ray diffraction (XRD) patterns, transmission electron microscopy (TEM) images, secondary‑ion mass spectrometry (SIMS), time‑dependent dielectric‑breakdown (TDDB) lifetime curves, and adhesive strength. The new film’s antibacterial efficacy arrives at an antibacterial ratio of approximately 100% against Staphylococcus aureus (S. aureus) BCRC 10451 for the 300‑nm‑thick film and approximately 99.82% for the 8 nm film, far superior to that of a pure Cu film, which is 0 with the same annealing temperature range. The new film, hence, seems to be a remarkable candidate material for various industrial applications, such as ultra‑large‑scale integrated circuits (ULSIC), micro‑electronic circuits, printed circuits, flip‑chip technology, medical care concerning antibacteria, and the like. [ABSTRACT FROM AUTHOR]

Purpose: Au stud bump bonding technology is an effective means to realize heterogeneous integration of commercial chips in the 2.5D electronic packaging. The purpose of this paper is to study the long-term reliability of the Au stud bump treated by four different high temperature storage times (200°C for 0, 100, 200 and 300 h). Design/methodology/approach: The bonding strength and the fracture behavior are investigated by chip shear test. The experiment is further studied by microstructural characterization approaches such as scanning electron microscope, energy dispersive spectrometer and so on. Findings: It is recognized that there were mainly three typical fracture models during the chip shear test among all the Au stud bump samples treated by high temperature storage. For solder bump before aging, the fracture occurred at the interface between the Cu pad and the Au stud bump. As the aging time increased, the fracture mainly occurred inside the Au stud bump at 200°C for 100 and 200 h. When aging time increased to 300 h, it is found that the fracture transferred to the interface between the Au stud bump and the Al Pad. Originality/value: In addition, the bonding strength also changed with the high temperature storage time increasing. The bonding strength does not change linearly with the high temperature storage time increasing but decreases first and then increases. The investigation shows that the formation of the intermetallic compounds because of the reaction between the Au and Al atoms plays a key role on the bonding strength and fracture behavior variation. [ABSTRACT FROM AUTHOR]

With the advancement of Moore's Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device's failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging. [ABSTRACT FROM AUTHOR]

Despite significant progress made over the past decade in thermally activated delayed fluorescence (TADF) molecules as a material paradigm for enhancing the performance of organic light-emitting diodes, the underlying spin-flip mechanism in these charge-transfer (CT)-type molecular systems remains an enigma, even since its initial report in 2012. While the initial and final electronic states involved in spin-flip between the lowest singlet and lowest triplet excited states are well understood, the exact dynamic processes and the role of intermediate high-lying triplet (T) states are still not fully comprehended. In this context, we propose a comprehensive model to describe the spin-flip processes applicable for a typical CT-type molecule, revealing the origin of the high-lying T state in a partial molecular framework in CT-type molecules. This work provides experimental and theoretical insights into the understanding of intersystem crossing for CT-type molecules, facilitating more precise control over spin-flip rates and thus advancing toward developing the next-generation platform for purely organic luminescent candidates. Kim et al. propose a model for the complex spin-flip process in charge-transfer-type thermally activated delayed fluorescence molecules, uncovering the origin of the high-lying triplet state, addressing a pressing issue discussed over the last decade. [ABSTRACT FROM AUTHOR]

This paper aims to develop a thermal fluid–structure interaction (FSI) methodology to study the effect of different Cu pillar bump diameters on thermal and mechanical performance during the reflow soldering process. The desktop reflow oven is modeled in ANSYS FLUENT, while the ball grid array (BGA) package assembly is modeled in ANSYS STATIC STRUCTURAL. The accuracy of the simulated reflow temperature profile has been verified by comparing it with the experimental temperature data, according to JEDEC standards. The temperature distributions of solder and Cu pillar bumps are compared. A parametric study has been conducted to analyze the effect of different Cu pillar diameters on the reflow soldering process. By coupling the thermal loads with the structural analysis using thermal FSI, Cu pillar bumps with a diameter of 0.20 mm are found to exhibit the lowest reflow temperature, minimum temperature difference, and minimum deformation and thermal stress, making them the most suitable interconnection joints for flip chip technology. The study also examines the effect of soldering materials on the Cu pillar bump. The findings of this research provide valuable insights into the effects of varying Cu pillar diameters on the reflow soldering process, which can help in the development of more reliable electronic assemblies. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of various copper (Cu) pillar bump heights on temperature distribution, deformation and thermal stress during reflow. The virtual reflow oven environment was simulated using the fluid domain of the oven model. The accuracy of the fluid analysis was verified by comparing the obtained results with experimental data, which was conducted based on the Joint Electron Device Engineering Council (JEDEC) Standard. In addition, a grid independence test was carried out on the fluid mesh to determine the optimal mesh size for the simulations. A thermal fluid–structure interaction (FSI) approach was employed to couple the thermal results from the fluid analysis with the solid assembly. The results of the coupling analysis revealed that Cu pillar bumps with a height of 0.09 mm exhibited the lowest reflow temperature, minimal maximum deformation, and thermal stress, indicating that it is the optimal potential height for forming a good joint. The study also examines the impact of soldering materials, such as tin-bismuth (SnBi) and tin-silver-copper solder alloys (SAC305 and SAC405), on the Cu pillar bump. This study enables a comprehensive analysis of the thermal and mechanical performance of different Cu pillar bump parameters during the reflow process. [ABSTRACT FROM AUTHOR]

This research focuses on developing high-fidelity experimental and numerical models to analyze microscale underfill dynamics and void formation in high-density flip-chip packaging. Three underfilling scenarios are investigated, namely, point type, I-shaped line type, and L-type line type. The point-type underfilling validates the numerical model against experimental results, while the I-shaped and L-type line-type underfilling explore grid independence, void formation, and critical parameters such as filling position, contact angle, and liquid viscosity. Results indicate that contact angle and viscosity significantly influence filling efficiency and interface evolution. A smaller contact angle accelerates the process, reducing interface jumping motions. Viscous effects are quantified, revealing dimensionless filling time convergence. The use of low-viscosity surrogate fluids enhances numerical simulation efficiency. Sub-bump-sized, bump-sized, and sup-bump-sized voids are observed, identifying three void formation scenarios representing different underfilling flow mechanisms. This study provides insight into microscale flip-chip underfill physics and establishes validated models for next-generation high-density flip-chip products. These models can be further refined and integrated into optimization tools for automated process design, contributing to improved assembly yield and reliability of emerging electronic packages through physics-based understanding and modeling. [ABSTRACT FROM AUTHOR]

The European Synchrotron Radiation Facility (ESRF) and other synchrotrons worldwide have seen an increase in industry use since the 1990s. To meet industry needs, synchrotrons have established industry liaison offices and collaborations with research organizations and science service companies. The ESRF has set an annual commercial income target and received external funding to develop new services for industry, such as high-throughput X-ray powder diffraction and elemental analysis. The new ESRF-EBS light source has improved data collection speed, and the STREAMLINE project has made it more accessible. The ESRF now offers opportunities for the industrial and academic sectors, particularly in mining, chemistry, and material discovery. The ESRF is also involved in projects to test electronic circuit sensitivity to radiation and measure residual stresses. Efforts have been made to engage with industry through outreach programs and collaborations with small and medium-sized enterprises (SMEs). The ESRF has partnered with the European Innovation Council to provide specialized services to deep tech companies. Collaboration between synchrotrons and industry is crucial for addressing global challenges and promoting research and innovation. [Extracted from the article]

In this study, we have fabricated a 368 nm LED with an epitaxial Indium Tin Oxide (ITO) contact layer. We analyze the thermal performance of the flip-chip LED with a symmetric electrode and metal reflective layer, applying ANSYS to build a coupled electro-thermal finite element model (FEM) of the temperature distribution in the multiple quantum wells (MQWs). We compare our system with the traditional Au-bump flip-chip LED and a flip-chip LED with a Distributed Bragg Reflector (DBR) layer. The simulation results have shown that the flip-chip LED with a metal reflective layer and symmetric electrode exhibits better heat dissipation performance, particularly at high input power. The influence of the insulating layer on the LED chip junction temperature is also examined. The simulation data establish an effect due to the thermal conductivity of the insulating layer in terms of heat dissipation, but this effect is negligible at an insulation layer thickness ≤1 µm. [ABSTRACT FROM AUTHOR]

The luminous characteristics of flip-chip type high-voltage (HV) blue mini-light-emitting diodes (LEDs), which consist of three serially connected sub-mesas, have been investigated for the first time. The cryogenic electroluminescence below 100 K partially originates from localized excitons. As the driving current reaches 1 μA, the contributions of Shockley–Read–Hall nonradiative recombination and radiative recombination exhibit a remarkably inverse temperature dependence, while the contributions of Auger recombination and carrier leakage are relatively negligible. The mesa corresponding to the anode of the HV blue mini-LED exhibits the lowest temperature among the three sub-mesas due to its smaller thermal resistance. To minimize the temperature-induced shift in chromaticity coordinates, it is necessary to adjust the driving current based on the operating temperature. [ABSTRACT FROM AUTHOR]

Gallium oxide (Ga2O3) devices have shown remarkable potential for high-voltage, high-power, and low-loss power applications. However, thermal management of packaging for Ga2O3 devices becomes challenging due to the significant self-heating effect. In this paper, an advanced double-sided cooling flip-chip packaging structure for Ga2O3 devices was proposed and the overall packaging of Ga2O3 chips was researched by simulation in detail. The advanced double-sided cooling flip-chip packaging structure was formed by adding a layer of diamond material on top of the device based on the single-sided flip-chip structure. With a power density of 3.2 W/mm, it was observed that the maximum temperature of the Ga2O3 chip with the advanced double-sided cooling flip-chip packaging structure was 103 °C. Compared with traditional wire bonding packaging and single-sided cooling flip-chip packaging, the maximum temperature was reduced by about 12 °C and 7 °C, respectively. When the maximum temperature of the chip was controlled at 200 °C, the Ga2O3 chip with double-sided cooling packaging could reach a power density of 6.8 W/mm. Finally, by equipping the top of the package with additional water-cooling equipment, the maximum temperature was reduced to 186 °C. These findings highlight the effectiveness of the proposed flip-chip design with double-sided cooling in enhancing the heat dissipation capability of Ga2O3 chips, suggesting promising prospects for this advanced packaging structure. [ABSTRACT FROM AUTHOR]

ChemElectroChem is celebrating its 10-year anniversary as a trusted forum for the electrochemistry community worldwide. The journal has undergone various changes, including rebranding, the introduction of special collections, and the transition to a fully open access publishing model. It has published 192 issues covering a wide range of topics in electrochemistry and has received recognition for its contributions to the field. ChemElectroChem aims to continue publishing excellent electrochemistry content and engaging with the scientific community in the future. [Extracted from the article]

In this work, unique properties and tremendous advantages for an omni-directional reflector (ODR) on an inclined sidewall for flip-chip AlGaN-based deep ultraviolet light-emitting diodes (DUV LEDs) are systematically investigated via a three-dimensional finite-difference time-domain method. It is found that although the reflectivity of Ag is far lower than that of Al, the light extraction efficiency for the inclined sidewall DUV LED with the Ag-based ODR is not always lower than that with Al-based one within certain incident angles. The reason is that the total internal reflection (TIR) of the ODR on the inclined sidewall plays an important role in extracting light. We also find that the reflectivity for TIR can be strongly suppressed if surface plasmon polaritons (SPPs) resonance absorption occurs. To avoid SPP resonance absorption, our studies in this work propose the design strategy for ODR on the inclined sidewall as follows: if the ODR structure of the DUV LED with an inclined sidewall adopts thin dielectric layers, the high-index material should be selected as the dielectric layer; if a thick dielectric layer is adopted for the ODR structure, the low-index material should be selected as the dielectric layer. [ABSTRACT FROM AUTHOR]

This document is an editorial for a special issue of the journal Micromachines focused on advanced interconnect and packaging technologies in the field of electronics. The editorial highlights the importance of these technologies in achieving high performance, miniaturization, and low power consumption in electronic devices. It introduces several research contributions included in the special issue, covering topics such as built-in packaging methods, bonding strength improvement, accurate characterization of interconnects, signal and power integrity analyses, crosstalk reduction, and reliability issues. The editorial acknowledges the challenges that remain in this field and expresses gratitude to the authors, editors, and reviewers involved in the special issue. [Extracted from the article]

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency. [ABSTRACT FROM AUTHOR]

Laminate substrates in advanced IC packages serve as not only the principal heat dissipation pathway but also the critical component governing the thermomechanical performance of advanced packaging technologies. A solid and profound grasp of their thermomechanical properties is of crucial importance to better understand IC packages' thermomechanical behavior. This study attempts to introduce a subregion homogenization modeling framework for effectively and efficiently modeling and characterizing the equivalent thermomechanical behavior of large-scale and high-density laminate substrates comprising the non-uniform distribution and non-unidirectional orientation of tiny metal traces. This framework incorporates subregion modeling, trace mapping and modeling, and finite element analysis (FEA)-based effective modeling. In addition, the laminates are macroscopically described as elastic orthotropic or elastic anisotropic material. This framework is first validated with simple uniaxial tensile and thermomechanical test simulations, and the calculation results associated with these two effective material models are compared with each other, as well as with those of two existing mixture models, and direct the detailed FEA. This framework is further tested on the prediction of the process-induced warpage of a flip chip chip-scale package, and the results are compared against the measurement data and the results of the whole-domain modeling-based effective approach and two existing mixture models. [ABSTRACT FROM AUTHOR]

Flip chip bonding technology on gold–tin (Au-Sn) microbumps for MEMS (Micro Electro Mechanical Systems) and 3D packaging is becoming increasingly important in the electronics industry. The main advantages of Au-Sn microbumps are a low electrical resistance, high electrical reliability, and fine pitch. However, the bonding temperature is relatively high, and the forming mechanism of an intermetallic compound (IMC) is complicated. In this study, Au-Sn solid-state diffusion (SSD) bonding is performed using the thermal gradient bonding (TGB) method, which lowers bonding temperature and gains high bonding strength in a short time. Firstly, Au-Sn microbumps with a low roughness are prepared by using an optimized process. Then, Au-Sn bonding parameters including bonding temperature, bonding time, and bonding pressure are optimized to obtain a higher bonding quality. The shear strength of 23.898 MPa is obtained when bonding in the HCOOH environment for 10 min at the gradient temperature of 150 °C/250 °C with a bonding pressure of more than 10 MPa. The IMC of Au-Sn is found to be Au-Sn and Au5Sn. The effect of annealing time on the IMC is also investigated. More and more Au5Sn is generated with an increase in annealing time, and Au5Sn is formed after Sn is depleted. Finally, the effect of annealing time on the IMC is verified by using finite element simulation, and the bonding strength of IMC was found to be higher when the bonding temperature is 150 °C at the cold side and 250 °C at the hot side. The temperature in the bonding area can reach 200 °C, which proves that the Au-Sn bonding process is solid-state diffusion because the temperature gradient reaches 2500 °C/cm. [ABSTRACT FROM AUTHOR]

The reliability of flip-chip packages is significantly impacted by the type of packaging materials, such as underfill, solder, flux, and solder mask. Underfill reduces the coefficient of thermal expansion (CTE) mismatch between the semiconductor chip and printed circuit board, thereby minimizing the chances of thermal fatigue failure of the package. There are a plethora of underfill suppliers and selecting the most suitable underfill for preparing a flip-chip package is critical as there are conflicting criteria. These criteria are limited to glass transition temperature (Tg), CTE, elastic modulus (E), coefficient of moisture expansion, fracture toughness (Kic), shear strength, and flowability. Choosing appropriate alternatives based on the above conflicting criteria is basically a multi-criteria problem. This research proposes a grey simplified best–worst method (GSBWM) to identify the criteria weight. The proposed method has less calculation complexity than the previous grey best–worst methods, and it does not need operations research and modeling knowledge, and optimization software to solve it. The accuracy of the GSBWM is investigated using three data sets. The results showed the high accuracy of the proposed method in all data sets. This study employed the combination of GSBWM and a grey possibility degree based method to select the most suitable underfill material for reliable flip-chip packages as a real-world problem. [ABSTRACT FROM AUTHOR]

This article presents the significance of using different sizes and positions of IC (Integrated Circuit) chips that are mounted on substrates of different materials. 1631The ICs are cooled by forced convection in a horizontal wind tunnel. COMSOL Multiphysics 5.4 solve the IC chip cooling problem by selecting a conjugate heat transfer module with laminar flow. FR4, ba-kelite, single and multi-layer copper clad boards are used as substrate materials. Numerical simulations are performed for FR4, bakelite with a constant heat flux of 5000 W/m², at 2.5 m/s air velocity. In contrast, single and multi-layer copper clad boards are studied for 10000 W/m² with 1.5 m/s air velocity. The prime objective of this research is to use adequate size and placement of chips generating high heat fluxes for enhanced heat transfer. Results showed that larger chips placed at bottom rows and sequentially decreasing sizes in the subsequent rows for the same overall input for high substrate thermal conductivity give more heat dissipation. Among all configurations A0 - F considered in the study, case E provides minimum tempera-ture using single and multi-layer copper clad boards. In addition to modification of chip sizes, geometric spacing of X1/X2 = 1.8 results in lower maximum temperature. [ABSTRACT FROM AUTHOR]

Semiconductor chips on a substrate have a wide range of applications in electronic devices. However, environmental temperature changes may cause mechanical buckling of the chips, resulting in an urgent demand to develop analytical models to study this issue with high efficiency and accuracy such that safety designs can be sought. In this paper, the thermal buckling of chips on a substrate is considered as that of plates on a Winkler elastic foundation and is studied by the symplectic superposition method (SSM) within the symplectic space-based Hamiltonian system. The solution procedure starts by converting the original problem into two subproblems, which are solved by using the separation of variables and the symplectic eigenvector expansion. Through the equivalence between the original problem and the superposition of subproblems, the final analytical thermal buckling solutions are obtained. The SSM does not require any assumptions of solution forms, which is a distinctive advantage compared with traditional analytical methods. Comprehensive numerical results by the SSM for both buckling temperatures and mode shapes are presented and are well validated through comparison with those using the finite element method. With the solutions obtained, the effects of the moduli of elastic foundations and geometric parameters on critical buckling temperatures and buckling mode shapes are investigated. [ABSTRACT FROM AUTHOR]

Flexible and stretchable materials have attracted significant interest in wearable electronics and bioengineering fields. Recent developments also incorporate embedded microwave circuits and systems with engineered flexible materials that operate over a broad frequency range (≈1–100 GHz). Herein, a simple flip‐chip technique is used to evaluate frequency‐dependent electromagnetic properties of flexible materials and applied to evaluate engineered microwave absorbers based on self‐biased barium hexaferrite composites. On‐wafer error correction and de‐embedding techniques are applied to determine broadband electromagnetic properties of the material‐loaded transmission lines by placing the materials on top of coplanar waveguide transmission lines. Finite‐element simulations along with broadband measurements were employed to estimate the electromagnetic material properties. To demonstrate, flexible polydimethylsiloxane (PDMS) composites are fabricated with barium hexaferrite nanoparticles and complex permittivity and permeability of the composites are quantified under zero magnetic field bias up to 110 GHz. Frequency‐dependent composite permeability is fitted to models describing the ferromagnetic resonance of the self‐biased barium hexaferrite nanoparticles in polydimethylsiloxane, and constituent nanoparticle properties are estimated using the Maxwell–Garnett mixing model. This study paves the way to exploit a wide range of engineered materials in flexible, wearable, and biomedical electronics applications and presents a convenient methodology to extract important broadband electromagnetic properties of nanoparticles for customized electromagnetic applications. [ABSTRACT FROM AUTHOR]

Shortwave infrared (SWIR) imaging devices have gained increasing importance in various fields, including security monitoring, biomedical imaging, advanced driver assistance, and semiconductor industry. However, complex technological processes of epitaxial growth and flip‐chip bonding hinder the development of high‐performance and low‐cost SWIR imaging devices. Herein, a novel organic–inorganic hybrid optical up‐conversion (OUC) imaging device by stacking a phosphorescent organic light‐emitting diode (OLED) with a NiSix/Si Schottky barrier diode (SBD) is developed. The pyramidal microstructures of silicon are utilized to greatly enhance light absorption of the NiSix/Si SBD, enabling the device to respond to a broadband SWIR light of 1064, 1310, and 1550 nm that are beyond the bandgap limit of silicon. Significantly, the device demonstrates excellent up‐conversion imaging behaviors at SWIR light with an ultra‐fast refresh rate of over 3000 Hz and a high‐resolution imaging capability of 508 ppi. This work paves the way toward the fabrication of high‐performance, low‐cost silicon‐based OUC devices for SWIR imaging applications. [ABSTRACT FROM AUTHOR]

Cryogenic microsystems that utilize different 3D integration techniques are being actively developed, e.g., for the needs of quantum technologies. 3D integration can introduce opportunities and challenges to the thermal management of low temperature devices. In this work, we investigate sub-1 K inter-chip thermal resistance of a flip-chip bonded assembly, where two silicon chips are interconnected by compression bonding via indium bumps. The total thermal contact area between the chips is 0.306 mm2, and we find that the temperature dependence of the inter-chip thermal resistance follows the power law of α T − 3 , with α = 7.7 – 15.4 K4μm2/nW. The T − 3 relation indicates phononic interfacial thermal resistance, which is supported by the vanishing contribution of the electrons to the thermal conduction, due to the superconducting interconnections. Such a thermal resistance value can introduce a thermalization bottleneck in particular at cryogenic temperatures. This can be detrimental for some applications, yet it can also be harnessed. We provide an example of both cases by estimating the parasitic overheating of a cryogenic flip-chip assembly operated under various heat loads as well as simulate the performance of solid-state junction microrefrigerators utilizing the observed thermal isolation. [ABSTRACT FROM AUTHOR]