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Singe-Electron Transistor (SET) is considered as a promising candidate of low-power devices for replacement or co-existence with Complementary Metal-Oxide-Semiconductor (CMOS) transistors/circuits. In this work, we propose a diagnosis approach for SET array under a more generalized defect model. With the more generalized defect model, the diagnosis approach will become more practical but complicated. We conducted experiments on a set of SET arrays with different dimensions and defect rates. The experimental results show that our approach only has 3.8% false-negative rate and 0.7% misjudged-category rate on average without reporting any false-positive edge when the defect rate is 4%. Therefore, the proposed diagnosis approach can diagnose the defective SET arrays and elevate the reliability of the SET arrays in the synthesis flow. [ABSTRACT FROM AUTHOR]

Background: Pneumocystis jiroveci pneumonia (PJP) in non-HIV patients is still a challenge for intensivists. The aim of our study was to evaluate mortality predictors of PJP patients requiring Intensive care unit (ICU) admission. Methods: Retrospectively review medical records of patients with diagnosis of PJP admitted to four ICUs of two academic medical centers from October 2012 to October 2015. Results: Eighty-two patients were enrolled in the study. Overall hospital mortality was 75.6 %. Compared with survivors, the non-survivors had older age (55 ± 16 vs. 45 ± 17, p = 0.014), higher APACHE II score (20 ± 5 vs. 17 ± 5, p = 0.01), lower white blood cell count (7.68 ± 3.44 vs. 10.48 ± 4.62, p = 0.005), less fever (80.6%vs. 100 %, p = 0.033), more hypotension (58.1 % vs. 20 %, p = 0.003), more pneumomediastinum (29 % vs. 5 %, p = 0.027). Logistic regression analysis demonstrated that age [odds ratio (OR)1.051; 95 % CI 1.007-1.097; p = 0.022], white blood cell count [OR 0.802; 95 % CI 0.670-0.960; p = 0.016], and pneumomediastinum [OR 16.514; 95 % CI 1.330-205.027; p = 0. 029] were independently associated with hospital mortality. Conclusions: Mortality rate for non-HIV PJP patients requiring ICU admission was still high. Poor prognostic factors included age, white blood cell count and pneumomediastinum. [ABSTRACT FROM AUTHOR]

Projected Sum of Products (P-SOP) is a bounded multi-level representation. The synthesis of P-SOP representation is based on decomposing the input space with respect to the orthogonal basis x'i ⊕p(X(i)) and xi⊕p(X(i)) where xi is an input variable and p(X(i)) is a function of all variables except xi . Different p(X(i)) may result in different areas after synthesis. Therefore, to obtain a minimal P-SOP circuit, it is important to select an appropriate variable xi and function p(X(i)). In this paper, we propose a Genetic Algorithm to efficiently determine xi and p(X(i)). Experimental results show that the proposed approach saves 81% CPU time in searching such a pair as compared to an exhaustive method without sacrificing the optimality. [ABSTRACT FROM AUTHOR]

Reducing power consumption has become one of the primary challenges in chip design, and therefore significant efforts are being devoted to find holistic solutions on power reduction from the device level up to the system level. Among a plethora of low power devices that are being explored, single-electron transistors (SETs) at room temperature are particularly attractive. Although prior work has proposed a binary decision diagram-based reconfigurable logic architecture using SETs, it lacks an automatic synthesis algorithm for the architecture. Consequently, in this work, we develop a product-term-based approach that synthesizes a logic circuit by mapping all its product terms into the SET architecture. The experimental results show the effectiveness and efficiency of the proposed approach on a set of MCNC benchmarks. [ABSTRACT FROM AUTHOR]

The large number of latches in current digital designs increases the complexity of formal verification and logic synthesis, since an increase in latch numbers leads to an exponential expansion of the state space. One solution to this problem is to find the functional dependences among these latches. With the information of functional dependences, these latches can be identified as dependent or essential latches, and the state space can be constructed using only the essential latches. Although much research has been devoted to exploring the functional dependences among latches using binary-decision-diagram (BDD)-based symbolic algorithms, this issue is still unresolved for large sequential circuits. In this paper, we propose a heuristic to identify the dependent latches based on the state-of-the-art work. In addition, our proposed approach detects sequential functional dependences existing in the reachable state space only. The sequential functional dependences can identify additional dependent latches after a specific time frame in order to achieve additional reduction of the state space. Experimental results show that this approach can deal with large sequential circuits with up to 9000 latches in a reasonable time while simultaneously identifying their combinational and sequential dependent latches. For instance, with s13207 in ISCAS'89, 23% of the latches are identified as combinational dependent latches, and an additional 13% of the latches are identified as sequential dependent latches. For the reachability analysis of s13207, with the benefits of dependent-latch identification, 70.70% of the BDD size and 73.32% of the CPU time can be reduced within the same time frame. Furthermore, 2890.76% more states can be reached under the 600 000-s run-time limit. [ABSTRACT FROM AUTHOR]

Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous approaches use the binary decision duigrain (BDD) technique to compute the range of one circuit and then reconstruct the circuit using the computed range. Although the size of the new circuit is significantly reduced due to the range rearrangement, this method suffers from the BDD blowup problems for large circuits since performing range computation using BDD is memory intensive. Thus, in this paper, we propose a new method for simplifying combinational circuits without explicit range computation. We first introduce a new concept of a stuck-at fault test for a circuit's range, showing that a range untestable stuck-at fault on a primary input (PI) indicates that this PI is range redundant, i.e., it can be removed without affecting the circuit's range. We then present a procedure to determine if a given range stuck-at fault on a PI is untestable. Our method iteratively identifies and removes range-redundant PIs to simplify a combinational circuit without performing range computation. Accordingly, large circuits that BDD-based methods cannot deal with can be handled using our method. We conduct experiments on a set of ISCAS'85 and MCNC benchmarks, and the experimental results show that our approach can minimize circuits such that fewer PIs are left. On average, our approach gets 37.06% reduction in terms of the number of PIs and 36.31% reduction in terms of the node counts. [ABSTRACT FROM AUTHOR]

The article presents a connection model and a corresponding error model for pin-accurate port connections, along with an algorithm for generating the minimum pattern set, a methodology for diagnosing errors, and a port connection verification flow. The model verifies the correctness of interconnections for all components in a design coded with a hardware description language.

The fluctuation in the minority carrier lifetime (MCLT) measurement is observed when monitoring the metal contamination for the furnace performing denuded zone formation, and the mechanism responsible for this phenomenon is examined in this paper. Among various possible causes, the oxygen precipitates are found to be the main contributor for this MCLT fluctuation because the amount of oxygen precipitates after denuded zone formation is strongly related to the initial oxygen concentration in the wafer and this makes the MCLT value liable to be affected even for tiny initial oxygen difference. A gate oxide recipe is suggested to be adopted for MCLT monitoring in furnace performing denuded zone formation to circumvent the problem. For the gate oxide recipe, not only is the monitoring result stable but it is feasible to produce MCLT test wafers with real products without sacrificing tool productivity. [ABSTRACT FROM AUTHOR]

Exact approaches to combinational equivalence checking, such as automatic test pattern generation-based, binary decision diagrams (BDD)-based, satisfiability-based, and hybrid approaches, have been proposed over the last two decades. Recently, we proposed another exact approach using signal probability. This probability-based approach assigns probability values. to the primary inputs and compares the corresponding output probability of two networks via a probability calculation process to assert if they are equivalent. The shortcoming of all these exact approaches is that if two networks are too complex to be handled, their equivalence cannot be determined, even with tolerance. An approximate approach, named the probabilistic approach, is a suitable way to give such an answer for those large circuits. How- ever, despite generally being more efficient than exact approaches, the probabilistic approach faces a major concern of a non zero aliasing rate, which is the possibility that two different networks have the same output probability/signatures. Thus, minimizing aliasing rate is substantial in this area. In this paper, we propose a novel probabilistic approach based on the exact probability-based approach. Our approach exploits proposed probabilistic equivalence checking architecture to efficiently calculate the signature of network with virtually zero aliasing rate. We conduct experiments on a set of benchmark circuits, including large and complex circuits, with our probabilistic approach. Experimental results show that the aliasing rate is virtually-zero, e.g., 10-6013. Also, to demonstrate the effectiveness of our approach on error detection, we randomly inject errors into networks for comparison. As a result, our approach more efficiently detects the error than a commercial tool, Cadence LEC, does. Although our approach is not exact, it is practically useful. Thus, it can effectively complement exact methods to improve the efficiency and effectiveness of combination equivalence checking algorithms. [ABSTRACT FROM AUTHOR]

This paper is concerned with organic contamination from a partially fluorinated o-ring used in a furnace for a high-temperature process. The organic outgas was confirmed by Fourier transform infrared analysis of the furnace exhaust gas. Experiments from practical trench dynamic random access memory disclosed that outgassed organic contaminants from the nitride process would severely worsen the tunneling leakage current performance of the storage dielectric and lead to fatal yield loss even though the cell capacitance was almost uninfluenced. To eliminate this yield detractor requires several test runs prior to real production after installation of the partially fluorinated o-ring; otherwise, a fully fluorinated o-ring is needed. From a cost viewpoint, the latter is highly suggested. [ABSTRACT FROM AUTHOR]

A crosstalk effect leads to increases in delay and power consumption and, in the worst-case scenario, to inaccurate results. With the scale down of technology to deep-submicrometer level, the crosstalk effect between adjacent wires becomes more and more serious, particularly between long on-chip buses. In this paper, we propose a deassembler/ assembler technique to eliminate undesirable crosstalk effects on bus transmission. By taking advantage of the prefetch process, where the instruction/data fetch rate is always higher than the instruction/data commit rate, the proposed method incurs almost no penalty in terms of dynamic instruction count. In addition, when the bus width is 128 b, the required number of extra bus wires is only 7 as compared to the 85 extra bus wires needed in the work of Victor and Keutzer. [ABSTRACT FROM AUTHOR]

Embedded cores are being increasingly used in large system-on-a-chip (SoC) designs. The high complexity of SoC designs lead the design verification to be a challenge for system integrators. This paper presents an automatic interconnection rectification (AIR) technique based on the port order fault model to detect, diagnose, and correct the misplacements of interconnection that occurred in the integration of a SoC design automatically. The experiments are conducted on combinational and sequential benchmarks. Experimental results show that the AIR can correct the misplaced interconnection exactly within reasonable efforts and, therefore, accelerates the integration verification of SoC designs. [ABSTRACT FROM AUTHOR]

Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model was proposed. It has been used for verifying core-based designs and the corresponding verification pattern generation has been developed. Here, the authors present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC design verification based on the POF model. On average, the size of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45% smaller and the run time decreases 16% as compared with the previous results of AVPG. [ABSTRACT FROM AUTHOR]

Presents an automatic-verification pattern generation (AVPG) for system-on-a-chip design verification based on the port-order fault (POF) model. Details of experiments on combinational and sequential benchmarks; Mechanism of conducting POF verification; Description of a verification pattern generation algorithm; Discussion on the combinational AVPG.

Owing to the delayed introduction of high-k storage dielectric for trench DRAM, a new technology to extend the existing NO storage dielectric becomes a prerequisite. For trench DRAM, the nitride film of NO-based storage dielectric has been proved to possess higher quality by proper N2O treatment, which enables further reduction in nitride thickness and extension of scaling limit for the existing storage dielectric. A 164% leakage current improvement without sacrificing the cell capacitance can be achieved through this process, while keeping the outstanding reliability performance of less than 438 ppm failure rate after a ten-year operation. Most importantly, this new process can be fully integrated into incumbent furnace process, which means that no additional tool investment is required, and it is crucial for trench DRAM manufacturers to maintain their competitive advantage before the high-k material prevails at 65 nm technology node. [ABSTRACT FROM AUTHOR]

A simplified and integrated technique has been proposed to form an oxide/nitride storage dielectric in a single-furnace process by low-pressure oxidation and nitride film deposition with an extra N2O treatment for the trench dynamic random access memory (DRAM). Compared to the conventional nitride/oxide dielectric, this newly developed dielectric enjoys cell-capacitance-enhancement factor as high as 12.5% without degrading the leakage current and electron-trapping property. From the reliability test, the qualification for the DRAM application is also proven by the dielectric lifetime longer than 10-years. Most importantly, this technique can reduce the production cycle time without an additional equipment investment, which is essential in the cost-competitive DRAM arena. [ABSTRACT FROM AUTHOR]