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In this paper, a series of Low Voltage Triggering Silicon-Controlled Rectifier (LVTSCR)-based devices were designed and fabricated in a 0.25 μm Bipolar-CMOS-DMOS (BCD) process. Two distinct methods, the integration of additional doping regions and current paths, are investigated to improve the proposed devices' holding voltage (V h). Two-dimensional device simulation is employed to elucidate the working mechanism of these ESD protection devices, complemented by the introduction of a transmission line pulse (TLP) measuring system to assess their ESD protection capabilities. Comparative analysis of TLP results reveals that both methods contribute significantly to the augmentation of holding voltage in LVTSCR ESD protection devices. The refined structure, LVTSCR_BN, with two additional current paths, surface and buried, demonstrated a noticeable increment in holding voltage. With its holding voltage of 7.619 V and trigger voltage of 10.61 V, LVTSCR_BN is proved suitable for the ESD protection of circuits operating at the voltage of 5 V. [ABSTRACT FROM AUTHOR]

Continuously scaling down ICs result in more stringent electrostatic discharge (ESD) protection design requirements. Compared with other devices, silicon-controlled rectifier (SCR) has become the first choice for its area efficiency and robustness. In order to improve the latch-up issue of SCR, various schemes have been proposed. A simple method is to extend the SCR path length, which will result in the enlarged ON resistance. Segment technology is also used to improve the holding voltage of SCR, but it will shrink the effective emitter area and lead to the serious degradation of ESD robustness. MS-LVTSCR is used to protect CMOS input ports. The circuit operating voltage is 3.3V and the gate oxide DC breakdown voltage is 19V so that considering the safety margin, the ESD window is from 3.63V to 17.1V. This work proposes a novel MOS shunt low-voltage trigger silicon-controlled rectifier (MS-LVTSCR) electrostatic discharge protection device by inserting an embedded PMOS structure. Compared with the conventional LVTSCR, the proposed MS-LVTSCR achieves 53% improvement in the holding voltage and still maintains high ESD robustness with a current level of 31.5 mA/ μ m without more device area consumption. In addition, both the TCAD simulation and theoretical analysis were carried out to explore the principle of current shunt effect to improve holding voltage. The extra shunt paths will weaken the conductance modulation effect of the main drift region in the main SCR path and its holding voltage can be further raised by reducing the proportion of main drift region current in the total current. We also conducted detailed studies on the mechanisms and geometry effects of this newly proposed structure via experimental validations. • A MOS shunt LVTSCR has excellent holding voltage for 3.3V application. • The effect of current shunt on holding voltage is studied in detail. • The design principle of the current-shunt device is presented. [ABSTRACT FROM AUTHOR]

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18- $\mu \text{m}$ BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current (${I}_{\text {t2}}{)}$ of 1.59 A at a finger width of 50 $\mu \text{m}$. Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

For robust high-voltage (HV) electrostatic discharge (ESD) protection engineering, such as 8-KV or 15-KV ESD target, the silicon-controlled rectifiers (SCRs) with high holding voltage are needed to mitigate latch-up risk. However, when implemented in the multifinger layout configuration for satisfying high robust ESD requirement, these devices may encounter holding voltage deterioration problems. In this article, such holding voltage deterioration has been explored by theoretical analysis and experimental verification. The transmission line pulsing (TLP) results indicate that the sharing of adjacent WELL pickup and removing of inner guard ring in the typical multifinger layout (TMF) are the root causes for holding voltage deterioration. Through the appropriate test-key design, both of these culprits have been identified independently. Finally, by keeping the average WELL pickup length and average number of parasitic paths of each SCR finger in the multifinger layout constant, such holding voltage deterioration can be restrained effectively, achieving a stable holding voltage regardless of the number of fingers. Therefore, this article offers very useful work for HV ESD engineering. [ABSTRACT FROM AUTHOR]

The negative holding voltage of high-voltage (HV) dual-directional silicon-controlled rectifier (DDSCR) is usually attenuated to a very low level due to the grounded guard ring, which has been ignored by many researchers nowadays. In this brief, a novel symmetrical DDSCR (SDDSCR) is proposed to suppress the deterioration of DDSCR’s negative holding voltage. By introducing a diffusion resistor into the p-type guard ring (PGR), experimental results indicated that the reverse parasitic SCR path associated with PGR is suppressed effectively. Thus, a symmetric high holding voltage characteristic is implemented for SDDSCR without increasing any silicon footprint. Moreover, the PGR resistor technology presented in this brief can be extended to various existing HV DDSCRs, which could improve their negative holding voltage deteriorated by guard ring. [ABSTRACT FROM AUTHOR]

Transient voltage suppressor (TVS) has been widely used on the printed circuit board (PCB) to protect the microelectronics system against the system-level electrostatic discharge (ESD) and electrical fast transient/burst (EFT/B) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD and EFT/B immunity test, if the TVS were designed with a holding voltage of lower than the operating voltage of the CMOS ICs equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD and EFT/B immunity test. By monitoring the transient voltage waveforms in the time domain during system-level ESD and EFT/B immunity test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of the TVS must be greater than the system operating voltage to maintain the signal integrity in the field applications. [ABSTRACT FROM AUTHOR]

Terrestrial neutron and alpha particle irradiation data for a 7-nm bulk FinFET technology reveal the persisting reliability threat single-event latchup (SEL) poses to advanced technology nodes. SEL is characterized over a wide range of supply voltages and temperatures for this technology node. SEL data is analyzed to determine the holding voltage ($V_{\mathrm {HOLD}}$) required to sustain SEL, which can be as low as 0.85 V at elevated temperatures. Such low SEL holding voltage within 100 mV of nominal supply voltage poses a major reliability threat. [ABSTRACT FROM AUTHOR]

This article proposes a dual-directional silicon-controlled rectifier (SCR) with a novel structure and high holding voltage to improve the electrostatic discharge (ESD) design area efficiency in high-voltage environments. In terms of structure, by decreasing the emitter injection efficiency of the p-n-p parasitic bipolar transistor formed at the bottom of the gate region, the SCR positive feedback gain is reduced, which endows the proposed device with improved snapback characteristics compared with the conventional low-voltage triggering SCR (LVTSCR) and low-trigger dual directional SCR (LTDDSCR). This article conducted 2-D and mixed-mode simulations to compare and analyze the operating principles of the proposed and traditional devices. Additionally, experimental devices were fabricated under the same conditions using the 0.13-μm process to verify their electrical properties and latch-up immunity by measuring the transmission line pulse (TLP) and transient latch-up (TLU). This article also conducted a detailed analysis on the optimization of electrical properties for the ESD design window of the proposed device according to the design variables and application of segment topology, and also analyzed the temperature reliability using a hot chuck control system. The measurement results reveal that the proposed device is highly suitable for the 12-V-class ESD design window, has improved reliability, and can provide excellent area efficiency in related applications. [ABSTRACT FROM AUTHOR]

This article concerns experimental and simulation results on nonstable latchups (SLs) in CMOS integrated circuits (ICs) under pulsed laser irradiation. Different transient responses in elements of the p-n-p-n structure and irregular ionization distribution on the IC surface are the main reasons for non-SLs. Radiation experimental test results are presented as well as a discussion of non-SL mechanisms. [ABSTRACT FROM AUTHOR]

This article proposes a new silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection device suitable for 5-V applications. The proposed ESD protection device has an additional n-p-n parasitic bipolar transistor that provides an extremely short ESD discharge path. Compared with the conventional Low-Voltage-Trigger SCR (LVTSCR) and Low-Ron SCR (LRSCR), it has excellent ON-resistance and improved reverse characteristics. Furthermore, it has structurally enhanced trigger voltage and holding voltage characteristics. A conventional LVTSCR, LRSCR, and the proposed ESD protection device were fabricated with the same width using a 0.18-μ bipolar CMOS DMOS (BCD) process to verify the improvement in electrical characteristics and current driving capability of the new device. Transmission line pulsing (TLP) and a hot chuck control system were used to measure and compare the latch-up, electrical characteristics, and temperature reliability of the three devices. The measurements demonstrate that the proposed ESD protection device provides improved reliability and higher area efficiency for 5 V or similar applications. [ABSTRACT FROM AUTHOR]

The diode-triggered silicon-controlled rectifier (DTSCR) is an important device for the electrostatic discharge (ESD) protection of low-voltage integrated circuits, and its trigger voltage is determined by the forward turn-on voltage of diode string and the voltage drops on the parasitic resistors of metal interconnects. For the conventional DTSCR, the voltage drops on the parasitic resistors are often negligible so its triggering voltage is mainly determined by the forward turn-on voltage of diode string, which decreases with increasing temperature due to the inherited negative temperature coefficient. In this paper, an improved and novel device called thermal-stable DTSCR (TSDTSCR) is proposed to offer an improved ESD protection stability at elevated temperatures. This is done by changing and optimizing the 3-D layout. In particular, the experimental results show that the trigger voltage drop of the TSDTSCR can be reduced to 13.5% at 125 °C, comparing to 27.18% of the DTSCR. The holding voltage of the TSDTSCR is also more stable than that of the DTSCR over a wide range of temperatures. [ABSTRACT FROM AUTHOR]

• This paper proposes a novel SCR with high robustness and latch-up immunity. • By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. • Through 2D device simulation, the ESD characteristics of three SCRs are compared. • Vt1 (22.9 V), Vh (13.64 V) and It2 (18.49 A) of the PGSCR meet the requirements of the target chip. In an industry-level bus, strong electrostatic interference seriously threatens the reliability of chips. However, the holding voltage (Vh) and robustness of traditional silicon-controlled rectifier (SCR) cannot meet the electrostatic discharge (ESD) window of industry-level applications. To better cope with extreme environments, this paper proposes a novel SCR with high robustness and latch-up immunity for on-chip ESD protection of the industry-level RS485 bus. By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. Through two-dimensional device simulation, the ESD characteristics of traditional SCR, proposed P-Well Floating SCR (PFSCR) and proposed P-Well Grounded SCR (PGSCR) are compared, with a focus on exploring the role of surface discharge path. Three types of SCR are realized based on the 0.18 μm BCD process. The transmission line pulse (TLP) test results show that PGSCR (13.64 V) has a higher Vh and higher robustness than traditional SCR (2.13 V) and PFSCR (4.39 V). In addition, the trigger voltage (Vt1:22.9 V) and failure current (It2:18.49A) of the PGSCR fully meet the ESD window of the target chip. [ABSTRACT FROM AUTHOR]

The low-voltage triggering silicon-controlled rectifier (LVTSCR) device is widely used in on-chip electrostatic discharge (ESD) protection owing to its low trigger voltage and strong current-tolerating capability per area. In this paper, an improved LVTSCR by adding a narrow NWell (NW2) under the source region of NMOS is discussed, which is realized in a 0.5-μm CMOS process. A 2-dimension (2D) device simulation platform and a transmission line pulse (TLP) testing system are used to predict and characterize the proposed ESD protection devices. According to the measurement results, compared with the preliminary LVTSCR, the improved LVTSCR elevates the second breakdown current ( I t 2 ) from 2.39 A to 5.54 A and increases the holding voltage ( V h ) from 3.04 V to 4.09 V without expanding device area or sacrificing any ESD performances. Furthermore, the influence of the size of the narrow NWell under the source region of NMOS on holding voltage is also discussed. [ABSTRACT FROM AUTHOR]

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard. [ABSTRACT FROM AUTHOR]

Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current–voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a 0.11~\mu \textm 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure. [ABSTRACT FROM PUBLISHER]

In order to improve the holding voltage and keep the trigger voltage of the silicon controlled rectifier (SCR) devices, a new self-triggered stacked SCR structure (STSSCR) is proposed for on–chip electrostatic discharge (ESD) protection. The STSSCR structure consists of a modified lateral SCR (MLSCR) and multiple double trigger SCRs (DTSCRs). The trigger voltage of the structure is decided by the trigger voltage of the MLSCR. And the holding voltage is decided by the holding voltage of the SCRs and the number of the DTSCR in the STSSCR structure. The simulation and experimental results show that STSSCR has a stable trigger voltage, a small trigger current and an adjustable high holding voltage. [ABSTRACT FROM AUTHOR]

This paper develops optimization between electrostatic discharge (ESD) and latchup characteristics for a silicon-controlled rectifier (SCR)-incorporated Bipolar Junction Transistor (BJT) in a 0.18- \mu \textm , 3.3 V process. This device is composed of a floating pMOSFET embedded in a parasitic n-well/p-sub/n+ region BJT structure. The floating pMOS gate is further coupled with an RC network for controlling its switching. The floating pMOS could increase the effective width of its floating p+ region to enhance ESD robustness during ESD zapping events, whereas maintain its floating p+ region narrower during IC operation situation. With the optimized structure dimensions, this device can reach transmission-line pulse second breakdown current 6 A, ESD/ human-body model over 8 kV, which are the same as those of an SCR, and its latchup trigger current is at least 1.9 times greater. [ABSTRACT FROM PUBLISHER]

For high-voltage (HV) applications, the electrostatic discharge (ESD) protection design using a traditional HV device, such as laterally diffused MOSFETs, usually consumes large silicon area to meet sufficient ESD specification. In this paper, an area-efficient ESD protection design with stacked high-holding-voltage silicon-controlled rectifier (HHVSCR) is proposed and verified in a 0.25- \mu \textm 5/60 V Bipolar-CMOS-DMOS process. The proposed HHVSCR is fabricated in low-voltage wells and has the characteristics of HHV and high failure current with the same silicon area as the traditional SCR. From the experimental results, the proposed HHVSCR stacking structure can fit the desired ESD protection design window for the 60 V pins of a battery-monitoring IC and successfully protect these 60 V pins against 7-kV human-body-mode ESD stress. [ABSTRACT FROM AUTHOR]

In this Letter, an enhanced bidirectional modified lateral silicon‐controlled rectifier (EBMLSCR) is proposed for advanced dual‐directional electrostatic discharge (ESD) protection applications. The ESD characteristics of the novel EBMLSCR and conventional bidirectional modified lateral silicon‐controlled rectifier (BMLSCR) are measured using the transmission line pulsing tester. Compared with the BMLSCR, the EBMLSCR owns a lower trigger voltage down to 7.7 V, a higher failure current up to 6.5 A, a suitable holding voltage as well as the same superior leakage current. Based on these advantages, the proposed EBMLSCR can provide an effective ESD protection for the advanced 2.5 V/3.3 V input/output circuits, while the traditional BMLSCR becomes invalid for these applications due to its high trigger voltage and low robustness. In addition, the impact of some critical dimensions of the EBMLSCR has also been evaluated to further optimise the device performances. [ABSTRACT FROM AUTHOR]

• The holding voltage of the ADDSCR is increased by inserting floating heavy doping in the base region NW of the parasitic transistor PNP and PW of the parasitic transistor NPN under the condition that the device dimension and other factors remain the same. • The effects of various floating heavy doping combinations on the current path and lattice temperature of the device are analyzed through two-dimensional device simulation. • TLP test data were used to compare various floating heavy doping combinations, and the DC characteristics and capacitance of the devices were tested. • Five types of ADDSCR devices were fabricated in 0.18 μm BCD process with high failure current and high hold voltage, which can be applied to ESD protection between CAN pins and GND in automotive chips. In the ESD protection design work, the most effective way to improve the holding voltage of bidirectional silicon-controlled rectifier or SCR device is to increase the distance between the cathode and anode of it. However, for DDSCR devices with multi-finger layouts, increasing this distance will result in a decrease in failure current and require a larger layout area. In this work, five types of asymmetric dual direction silicon-controlled rectifier devices with different floating heavy doping combinations are designed based on the traditional ADDSCR structure. Meanwhile, the dimensions, number of fingers, metal layout and number of CONT holes of the five ADDSCR structures are strictly kept the same, aiming at studying the influence of different floating heavy doping combinations on the performance of SCR devices and find the optimal floating heavy doping combination. Their ESD performances are predicted and verified through the two-dimensional device simulations and transmission line pulse (TLP) test results. All the five types of ADDSCR structures are designed to improve the holding voltage. From the results, the forward and reverse holding voltage of ADDSCR_PP, which is inserted floating P+ in NW and PW, are increased to 20.4 V and 17.6 V respectively, compared with the traditional devices without floating heavy doping at 14.2 V and 8.7 V. At the same time, the physical mechanism for the effect of floating heavy doping insert into NW and PW separately were investigated. Finally, the one that best meets the ESD window of automotive application is found. [ABSTRACT FROM AUTHOR]

A MOS–IGBT–SCR component that was proposed in a previous paper to increase the device robustness and the cost of ESD protection circuit is optimized in this paper. In order to improve its latch-up immunity, several variations of geometrical parameters that have been simulated using TCAD Sentaurus Device in another previous paper have been implemented and compared in this work. The drift area, the form factor, and the proportion of P + sections inserted into the drain are the main parameters, which have a significant impact on the latch-up immunity. TLP characterization, and curve tracer measurements have been carried out to evaluate the proposed solution. Holding current increases up to 70 mA and holding voltage up to 10 V. [ABSTRACT FROM AUTHOR]

The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.1 8um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated. [ABSTRACT FROM AUTHOR]

Abstract: The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8V and a high trigger current of greater than 120mA. The robustness has measured to HBM 8kV (HBM: human body model) and MM 400V (MM: machine model). The proposed device has a high-level It2 of 52mA/μm approximately. [Copyright &y& Elsevier]

Robust and novel devices called high-holding low- voltage trigger silicon controlled rectifiers (HH-LVTSCRs) for electrostatic discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current- voltage (l-V) characteristics of the HH-LVTSCRs are adjustable to different operating conditions by changing the device dimensions and terminal interconnections. Comparison between complementary n- and p-type HH-LVTSCR devices shows that n-type devices perform better than p-type devices when a low holding voltage (VH) is allowed during the on-state of the ESD protection structure, but when a relatively high holding voltage is required, p-type devices perform better. Results further demonstrate that HH-LVTSCRs with a multiple-finger layout render high levels of ESD protection per unit area, applicable in the design of ICs with stringent ESD protection requirements of over 15 kV IEC. [ABSTRACT FROM AUTHOR]

The physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific "sweep-back" current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated by 0.25-μm CMOS technology. [ABSTRACT FROM AUTHOR]

A modified lateral-diffusion metal-oxide-semiconductor (MLDMOS) device with improved electrostatic discharge (ESD) protection performance is proposed for high-voltage ESD protection. In comparison with the traditional LDMOS and the LDMOS with an embedded silicon-controlled rectifier (LDMOS-SCR), the proposed device has better ESD robustness and higher holding voltage. By optimizing key parameters, such as the spacing between the drain and the poly gate, the effective channel length, and the number of fingers, the MLDMOS can achieve a maximum failure current over 80 mA/µm, which is larger than that of LDMOS-SCR. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. [ABSTRACT FROM AUTHOR]

Abstract: This paper introduces a novel silicon controlled rectifier (SCR)-based circuit. The proposed device using 70nm DRAM process obtained the high holding and low triggering voltages by using variable IR drop. These characteristics enable to discharge electrostatic discharge (ESD) current and ensure latch-up immunity for normal operations. Also, the proposed scheme is easily implemented through the modification of the metal connection compare to the conventional SCR-based device. We investigated electrical characteristics by both measurements and TCAD simulations. Measurement results showed the proposed SCR had triggering voltage of 6.2V, holding voltage of 3.3V, and the second breakdown current of 58mA/μm. [Copyright &y& Elsevier]

• A cascade-MOS-triggered SCR with high holding voltage for HV ESD protection is proposed. • TCAD simulation and TLP test results verify the device's characteristics. • The cascade-MOS-triggered SCR shows good temperature stability. A parallel-MOS-triggered silicon-controlled rectifier (PMTSCR) is firstly proposed and verified in a 0.25-μm Bipolar-CMOS-DMOS process, aiming to prevent the latch-up effect of SCR in the electrostatic discharge (ESD) protection. Comparing to the conventional SCR, the trigger voltage (V t 1) of the PMTSCR decreases because of the effect of PMOS embedded in the N-well, and the holding voltage (V h) increases because of the attribution of the NMOS embedded in the P-well. By shortening the SCR current conduction path and designing a special metal connection, the modified-PMTSCR (M-PMTSCR) is obtained. The failure current of the M-PMTSCR remarkably increases from 1.8 to 4.8 A. However, M-PMTSCR exhibits a lower V h and a higher V t 1. By further optimizing the location and connection of the embedded PMOS and NMOS, the obtained cascade-MOS-triggered SCR (CMTSCR) possesses a high V h of 8.4 V and a strong ESD robustness of 6000 V in a small chip area. Meanwhile, the operation mechanism simulated by Sentaurus was consistent with the theoretical circuit analysis and transmission line pulse measurements. Thus the proposed CMTSCR with the good latch up immunity and temperature stability is a promising device to meet the requirements of high voltage ESD protection. [ABSTRACT FROM AUTHOR]

• The Asymmetrical dual-direction SCRs are fabricated in 0.18 µm BCD process. • By adding a floating P+ at PWell to improve the device's holding voltage. • TCAD simulation and TLP measurement results verify the device's characteristics. • Compare the traditional device and the improved device on characteristics. The dual directional silicon-controlled rectifier (DDSCR) device is widely used in on-chip electrostatic discharge (ESD) protection owing to its bi-directional ESD protection and strong current-tolerating capability per area. In this paper, an asymmetrical dual directional ESD protection device for automotive application was developed in a 0.18-µm Bipolar CMOS DMOS (BCD) technology. In order to verify and predict the proposed ESD protection device's characteristics, a transmission line pulse (TLP) testing system and a 2-dimension device simulation platform have been used in this work. According to the measurement results, the asymmetrical dual directional silicon-controlled rectifier with a floating P+ region (ADDSCR_FP+) increases the forward holding voltage (Vh) from 3.89 V to 19.7 V and increases the reverse holding voltage from 3.62 V to 19.5 V which only slightly decrease the failure current compared with the traditional asymmetrical dual directional silicon-controlled rectifier (ADDSCR). The ADDSCR_FP+ has the features of symmetrical forward and reverse I-V curves, high holding voltage and high failure current. [ABSTRACT FROM AUTHOR]