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Focuses on optimal approach to fault tolerant software system design.

This article reports that the Cypak company has developed a disposable paper computer that can collect, process, encrypt, and store up to 32 kilobytes of data. The Cypak's system contains printable sensors and a small multipurpose application-specific integrated circuit with a radio-frequency identification interface. It detects events or accepts input via graphite-ink circuits. Thus, if a user breaks a seal to remove a product or presses a surface to answer a question, the system recognizes whether the circuit is opened or closed and records the information.

This paper presents the extension of framework for automatic design space exploration (FADSE) tool using a meta-optimization approach, which is used to improve the performance of design space exploration algorithms, by driving two different multiobjective meta-heuristics concurrently. More precisely, we selected two genetic multiobjective algorithms: 1) non-dominated sorting genetic algorithm-II and 2) strength Pareto evolutionary algorithm 2, that work together in order to improve both the solutions’ quality and the convergence speed. With the proposed improvements, we ran FADSE in order to optimize the hardware parameters’ values of the grid ALU processor (GAP) micro-architecture from a bi-objective point of view (performance and hardware complexity). Using our developed approach we obtained better GAP instances (a configuration has for almost the same cycles per instruction – 1.00, the hardware complexity 38% smaller/better – 35.81 versus 58.61) in half of the time compared to a classical sequential optimization approach (5 days versus 10 days). [ABSTRACT FROM PUBLISHER]

Analysis and monitoring of traffic measurements can provide a useful tool for diagnostics, troubleshooting, and performance analysis in networks. This paper presents a method for traffic analysis based on the theory of extreme values. Numerical time series obtained from traffic measurements are processed to compute statistical indicators and analyze them to detect significant local features, which may point to some critical network behavior. [ABSTRACT FROM AUTHOR]

This article discusses diagnosis of complex systems along with the methodologies of the FDI and DX communities. The proliferation of new technologies has significantly increased the complexity of human designed systems. Typical examples are controlled systems, such as manufacturing plants, aircraft, and spacecraft. Maintaining safety, reliability, and uninterrupted operation of these systems have become very important issues. Given the importance of this problem for safety-critical systems, a broad spectrum of approaches has been developed to cope with the diversity and complexity of the diagnosis task.

The interpretations of logical expressions found in most introductory textbooks are not suitable for use in software engineering applications because they do not deal with partial functions. More advanced papers and texts deal with partial functions in a variety of complex ways. This paper proposes a very simple change to the classic interpretation of predicate expressions, one that defines their value for all values of all variables, yet is almost identical to the standard definitions. It then illustrates the application of this interpretation in software documentation. [ABSTRACT FROM AUTHOR]

When fuzzy production rules are used to approximate reasoning, interaction exists among rules that have the same consequent. Due to this interaction, the weighted average model frequently used in approximate reasoning does not work well in many real-world problems. In order to model and handle this interaction, this paper proposes to use a nonadditive nonnegative set function to replace the weights assigned to rules having the same consequent, and to draw the reasoning conclusion based on an integral with respect to the nonadditive nonnegative set function, rather than on the weighted average model. Handling interaction in fuzzy production rule reasoning hi this way can lead to a good understanding of the rules base and an improvement of reasoning accuracy. This paper also investigates how to determine from data the nonadditive set function that cannot be specified by a domain expert. [ABSTRACT FROM AUTHOR]

Information about upcoming events of interest to Computer Society members. [ABSTRACT FROM PUBLISHER]

Reconfigurable architectures are a distinct point in the larger design space that includes programmable processors and nonprogrammable fixed-function devices. In this paper, we identify the major parameters that distinguish architectures in this design space and draw connections between these parameters and physical requirements (e.g., energy, delay, and area) and application characteristics (e.g., word width, locality). Building on these connections, we identify the fundamental advantages that reconfigurable architectures can offer. [ABSTRACT FROM PUBLISHER]

Many pervasive computing courses don't require a textbook. Instead, a variety of papers are given as assigned reading. Although there are advantages to using papers for reading assignments, there are disadvantages as well. With each course, instructors must curate their own list of important papers, and students don't have the benefit of a well-planned book, which ties together topics systematically. In light of this, Andrew Kun reviews nine books that might be a good match for pervasive computing courses. [ABSTRACT FROM PUBLISHER]

This paper proposes a domain corpus independent vocabulary generation algorithm in order to improve the coverage of vocabulary for embedded Continuous Speech Recognition (CSR). A vocabulary in CSR is normally derived from a word frequency list. Therefore, the vocabulary coverage is dependent on a domain corpus. We present an improved way of vocabulary generation using Part-Of-Speech (POS) tagged corpus and knowledge base. We investigate 152 POS tags defined in a POS tagged corpus and word-POS tag pairs. We analyze all words paired with 101 among 152 POS tags and decide on a set of words which have to be included in vocabularies of any size. The other 51 POS tags are mainly categorized with noun-related, Named Entity (NE)-related and verb-related POSs. We introduce a domain corpus independent word inclusion method for noun-, verb-, and NE-related POS tags using knowledge base. For noun-related POS tags, we generate synonym groups and analyze their relative importance using Google search. Then, we categorize verbs by lemma and analyze relative importance of each lemma from a pre-analyzed statistic for verbs. We determine the inclusion order of NEs through Google search. The proposed method shows at least 28.6% relative improvement of coverage for a SMS text corpus when the sizes of vocabulary are 5K, 10K, 15K and 20K In particular, the coverage of 15K size vocabulary generated by the proposed method reaches up to 97.8% with the relative improvement of 44.2%. [ABSTRACT FROM AUTHOR]

In the complex software systems, software agents always need to negotiate with other agents within their physical and social contexts when they execute tasks. Obviously, the capacity of a software agent to execute tasks is determined by not only itself but also its contextual agents; thus, the number of tasks allocated on an agent should be directly proportional to its self-owned resources as well as its contextual agents' resources. This paper presents a novel task allocation model based on the contextual resource negotiation. In the presented task allocation model, while a task comes to the software system, it is first assigned to a principal agent that has high contextual enrichment factor for the required resources; then, the principal agent will negotiate with its contextual agents to execute the assigned task. However, while multiple tasks come to the software system, it is necessary to make load balancing to avoid overconvergence of tasks at certain agents that are rich of contextual resources. Thus, this paper also presents a novel load balancing method: if there are overlarge number of tasks queued for a certain agent, the capacities of both the agent itself and its contextual agents to accept new tasks will be reduced. Therefore, in this paper, the task allocation and load balancing are implemented according to the contextual resource distribution of agents, which can be well suited for the characteristics of complex software systems; and the presented model can reduce more communication costs between allocated agents than the previous methods based on self-owned resource distribution of agents. [ABSTRACT FROM AUTHOR]

Web engineering is a new research line in software engineering that covers the definition of processes, techniques, and models suitable tot Web environments in order to guarantee the quality of results. The research community is working in this area and, as a very recent line, they are assuming the Model-Driven paradigm to support and solve some classic problems detected in Web developments. However, there is a lack in Web requirements treatment. This paper presents a general vision of Navigational Development Techniques (NDT), which is an approach to deal with requirements in Web systems. It is based on conclusions obtained in several comparative studies and it tries to fill some gaps detected by the research community. This paper presents its scope, its most important contributions, and offers a global vision of its associated tool: NDT-Tool. Furthermore, it analyzes how Web Engineering can be applied in the enterprise environment. NDT is being applied in real projects and has been adopted by several companies as a requirements methodology. The approach offers a Web requirements solution based on a Model-Driven paradigm that follows the most accepted tendencies by Web engineering. [ABSTRACT FROM AUTHOR]

Multiple combinations of hardware and network components can be selected to design an information technology (IT) infrastructure that satisfies requirements. The professional criterion to deal with these degrees of freedom is cost minimization. However, a scientific approach has been rarely applied to cost minimization, particularly for the joint optimization of hardware and network systems. This paper provides an overall methodology for combining hardware and network designs in a single cost minimization problem for multisite computer systems. Costs are minimized by applying a heuristic optimization approach to a sound decomposition of the problem. We consider most of the design alternatives that are enabled by current hardware and network technologies, including server sizing, localization of multitier applications, and reuse of legacy systems. The methodology is empirically verified with a database of costs that has also been built as part of this paper. Verifications consider several test cases with different computing and communication requirements. Cost reductions are evaluated by comparing the cost of methodological results with those of architectural solutions that are obtained by applying professional design guidelines. The quality of heuristic optimization results is evaluated through comparison with lower bounds. [ABSTRACT FROM AUTHOR]

This paper presents a tool to measure the power consumption of software programs running on computers with multiple input and output (I/O) components, such as disks and network-interface cards. The tool consists of two parts: 1) a monitor measuring the power of hardware components of the monitored computer and 2) a modified operating-system (OS) kernel in the monitored computer for information of software activities. The information is sent to the monitor for reconstructing the energy consumption of individual programs. This paper focuses on the software problem: How do we accurately assign the power samples to the software processes? A measurement-based method is used to synchronize the monitor and the monitored computer and a set of componentwise techniques to keep track of the programs' usage of each hardware component. Based on our experimental evaluation and comparison with the existing solutions, our tool raises the accuracy of energy assignment by up to 40% for programs with short CPU time slices and up to 90% for programs with 110 activities. This measurement tool can help the developers to analyze the software's energy characteristics more accurately and locate the energy-consuming spots more efficiently. [ABSTRACT FROM AUTHOR]

A critical component of an advanced-gas cooled reactor (AGR) station is the graphite core. As a station ages, the graphite bricks that comprise the core can distort and may eventually crack. As the core cannot be replaced the core integrity ultimately determines the station life. Monitoring these distortions is usually restricted to the routine outages, which occur every few years, as this is the only time that the reactor core can be accessed by external sensing equipment. However, during weekly refueling activities measurements are taken from the core for protection and control purposes. It is shown in this paper that these measurements may be interpreted for condition monitoring purposes, thus potentially providing information relating to core condition on a more frequent basis. This paper describes the data-mining approach adopted to analyze this data and also describes a software system designed and implemented to support this process. The use of this software to develop a model of expected behavior based on historical data, which may highlight events containing unusual features possibly indicative of brick cracking, is also described. Finally, the implementation of this newly acquired understanding in an automated analysis system is described. [ABSTRACT FROM AUTHOR]

This article assesses several ubiquitous computing systems. One of the hardest problems that application developers face is evaluating ubiquitous computing applications, such as those that adjust output on the basis of complicated contextual cues on that use natural input technologies such as gesture and speech. Ubiquitous computing researchers are beginning to explore evaluation techniques including field studies that drive invention, early-stage requirements gathering and prototype iteration.

Experimental research in computer science is a relatively new, yet fast developing area. It is encouraging to that there is substantial research going on in this important area. A study on experimental evaluation of a reusability-oriented parallel programming environment is given. There is a significant amount of experimental research in the area of computer dependability.

Information about upcoming events of interest to Computer Society members. [ABSTRACT FROM PUBLISHER]

A new approach for checkpointing and rollback recovery in a distributed computing system using a common time base is proposed in this paper. First, a common time base is established in the system using a hardware clock synchronization algorithm. This common time base is coupled with the idea of pseudo-recovery points to develop a checkpointing algorithm that has the following advantages: 1) reduced wait for commitment for establishing recovery lines, 2) fewer messages to be exchanged, and 3) less memory requirement. These advantages are assessed quantitatively by developing a probabilistic model. [ABSTRACT FROM AUTHOR]

This paper is concerned with the problem of ensuring the integrity of database systems that are accessed concurrently by a number of independent asynchronously running transactions. It is assumed that the database system is partitioned into small units that are referred to as the database entities. The relation between the entities is represented by a directed acyclic graph in which the vertices correspond to the database entities and the arcs correspond to certain access rights. We develop a family of non-two-phase locking protocols for such systems that will be shown to ensure serializability and deadlock-freedom. This family is sufficiently general to encompass all the previously developed non-two-phase locking protocols as well as a number of new protocols. One of these new protocols that seems to be particularly useful is also presented in this paper. [ABSTRACT FROM AUTHOR]

DIRECT is a multiprocessor database machine designed and implemented at the University of Wisconsin. This paper describes our experiences with the implementation of DIRECT. We start with a brief overview of the original machine proposal and how it differs from what was actually implemented. We then describe the structure of the DIRECT software. This includes software on host computers that interfaces with the database machine; software on the back-end controller of DIRECT; and software executed by the query processors. In addition to describing the structure of the software we will attempt to motivate and justify its design and implementation. We also discuss a number of implementation issues (e.g., debugging of the code across several machines). We conclude the paper with a list of the "lessons" we have learned from this experience. [ABSTRACT FROM AUTHOR]

This paper describes weapon system software life cycle management from a contractor perspective. Four procurement strategies—each requiring two or more contracts—are examined and their impact on the contractor and the software process are described. [ABSTRACT FROM AUTHOR]

One of the well-known problems in response verification is aliasing, i.e., the event that a series of responses containing errors results in a signature equal to that of the error-free response sequence. In this paper, we propose a scheme to reduce aliasing in accumulator-based response verification. The proposed scheme is based on monitoring the value of the carry output of the accumulator. Experimental study indicates that the proposed scheme achieves significantly less hardware overhead for the same reduction in the aliasing probability than previously proposed schemes. [ABSTRACT FROM AUTHOR]

Presents a reply to an article on a method for representing data items of unlimited length in computer memory.

Requirements elicitation and analysis is intended to gain knowledge about customers' needs and the environment of a software system. Requirements not only commonly deal with business processes and their data but also with the motivation behind these activities, the social structures that forge them, and previous design decisions. Recent studies show that the intentional and social concepts of agent-oriented software engineering (AOSE) could be used for the analysis of these aspects. Nevertheless, even having specialized modeling primitives for these requirements is not sufficient for their elicitation. Specialized analysis techniques are also required, but this is commonly overlooked by agent-oriented methodologies. This paper aims to provide the needed modeling primitives and support by means of the theoretical and methodological foundation of a social sciences framework, the activity theory, and its activity checklist. They inspire our Requirements Elicitation Guide (REG) for AOSE. The REG contains the expert knowledge that developers need to grasp information about their multiagent systems, human environments, and their mutual influences. This knowledge takes the form of requirements described as diagrams in a proper modeling language. The REG is applied in a process with the corresponding support tool. In this way, the REG guides requirements elicitation and increases the productivity with the use of templates for a wide range of requirements. These elements have been validated with several case studies. Two of them appear as part of this paper. [ABSTRACT FROM AUTHOR]

Shrinking technology nodes combined with the need for higher clock speeds have made it increasingly difficult to distribute a single global clock across a chip while meeting the power requirements of the design. Globally asynchronous locally synchronous (GALS) design style can help achieve low power consumption and modularity of a design while greatly reducing the number of global interconnects. Such multiple clock domain architectures can benefit from having frequency/voltage values assigned to each domain based on workload requirements. The work presented in this paper proposes a new hardware-based approach to dynamically change the frequencies and potentially voltages of a voltage-frequency island (VFI) system driven by a dynamic workload. This technique tries to change the frequency of a synchronous island such that it will have efficient power utilization while satisfying performance constraints. In recent years, there have been major developments, both in industry and academia, in the field of multiprocessor systems. Such multiprocessor systems are very good candidates for VFI design style implementation, where one or more processors can be part of a single VFI. To demonstrate the feasibility, of our proposed method, we have implemented a multiprocessor system for a field-programmable gate array (FPGA) platform that uses independently generated clocks for each processor. The results from the FPGA platform confirm the claim that the power consumption of a system can potentially be reduced while maintaining the performance of many applications. Our work concentrates primarily on embedded systems, but the idea can be explored for general-purpose computing as well. [ABSTRACT FROM AUTHOR]

Currently, the problem size that can be solved in reasonable time using the Method of Moments is limited by the amount of memory installed in the computer. This paper offers a new development that not only breaks this memory constraint, but also maintains the efficiency of running the problem in-core. In this paper, highly efficient parallel matrix-filling schemes are presented for parallel in-core and parallel out-of-core integral-equation solvers with subdomain RWG basis functions. The parallel methodology for matrix filling is quite different when using a subdomain basis as opposed to using a higher-order basis. The parallel in-core solver uses memory, which is often expensive and limited in size. The parallel out-of-core solver is introduced to extend the capability of MoM to solve larger problems that can be as large as the amount of storage on the hard disk. Numerical results on several typical computer platforms show that the parallel matrix-filling schemes and matrix-equation solvers introduced here are highly efficient and achieve theoretical predictions. The implementation of these advancements with the widely used RWG basis functions creates a powerful tool for efficient computational electromagnetics solution of complex real-world problems. [ABSTRACT FROM AUTHOR]

In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low, power consumption and enhanced timing margin without the degradation of the divider sensitivity. A horizontal eye opening is 71 .3%, and a vertical eye opening is 52%. The test chip fabricated in a 0.13 μm process consumes 210 mW from 1.2 V logic supply. [ABSTRACT FROM AUTHOR]

Deeds is a simulation environment for e-learning in digital electronics. The simulators cover combinational and sequential logic networks, finite state-machine design, and microcomputer interfacing and programming. They are integrated together, and therefore allow the design and test of embedded digital systems. The environment guides students' activities by delivering learning materials through specialized browsers. An extensive collection of learning materials is available. This paper includes an example of activity on a problem assignment. [ABSTRACT FROM AUTHOR]

This paper is about the development of systems whose end users are professional people working in a specific domain (e.g., medicine, geology, mechanical engineering); they are expert in that domain, but not necessarily expert in nor even conversant with computer science. In several work organizations, end users need to tailor their software systems to better adapt them to their requirements and even to create or modify software artifacts. These are end-user development activities and are the focus of this paper. A model of the interaction between users and systems, which also takes into account their reciprocal coevolution during system usage, is discussed. This model is used to define a methodology aimed at designing software environments that allow end users to become designers of their own tools. The methodology is illustrated by discussing two experimental cases. [ABSTRACT FROM AUTHOR]

In this paper a robust timing and frequency synchronization algorithm for DTMB system is developed. A two-step frequency offset estimation and compensation process is proposed to perform carrier recovery. Firstly coarse frequency estimation is achieved by utilizing the shift- and-add property of m-sequence. The second step finds the frame start position and the remaining frequency offset simultaneously. Meanwhile a timing tracking strategy is proposed to effectively track the dynamic changes in mobile environment. Thus the proposed scheme can resist large frequency offset and achieve accurate timing and frequency estimation. Simulation results under different channel situations verify the performance of the proposed scheme. [ABSTRACT FROM AUTHOR]

This paper presents the scheme and evaluation of a robust audio-visual digit-and-speaker-recognition system using lip motion and speech biometrics. Moreover, a liveness verification barrier based on a person's lip movement is added to the system to guard against advanced spoofing attempts such as replayed videos. The acoustic and visual features are integrated at the feature level and evaluated first by a Support Vector Machine for digit and speaker identification and, then, by a Gaussian Mixture Model for speaker verification. Based on 300 different personal identities, this paper represents, to our knowledge, the first extensive study investigating the added value of lip motion features for speaker and speech-recognition applications. Digit recognition and person-identification and verification experiments are conducted on the publicly available XM2VTS database showing favorable results (speaker verification is 98 percent, speaker identification is 100 percent, and digit identification is 83 percent to 100 percent). [ABSTRACT FROM AUTHOR]

This paper presents a sensorless neural-network-based induction motor control scheme, developed by following a holistic approach to electronic system modeling and controller design. The method uses Very-high-speed integrated circuits Hardware Description Language (VHDL), allowing the engineering system's functional description to be combined with a detailed digital controller design, which is then implemented into a field-programmable gate array (FPGA). The VHDL description of the hardware-implemented neural networks is automatically generated by C++ programs, in an adaptable architecture, appropriate to low-dynamic systems such as fans and pumps. The complete system performance is investigated by simulation and validated experimentally. This approach provides advantages such as a unique modeling and evaluation environment for complete power electronic systems, the same environment is used for the digital controller design and compact FPGA rapid prototyping, fast design development, short time to market, a CAD platform independent model, and reusability of the model/design. [ABSTRACT FROM AUTHOR]

AVS-P7 is the recent mobile video coding standard of China. Currently, ARM cores are widely used in mobile applications because of their low power consumption. In this paper a scheme of the AVS-P7decoder real-time implementation on 32 bit MCU RISC processor ARM920T (S3C2440) is presented. The algorithm, redundancy, structure and memorp optimization methods to implement AVS-P7 real-time are discussed in detail. The experiment results demonstrate the success of our optimization techniques and the real-time implementation. The ADS, MCPS, PSNR and simulation results show that the proposed AVS-P7 decoder can decode the QVGA image sequence in real-time with high image quality and has low complexity and less memory requirement. AVS conformance test result confirms the proposed AVS-P7 decoder full compliance with AVS. The proposed AVS-P 7 decoder can be applied in many real-time applications like Mobile phone and IPTV in the third generation communication. [ABSTRACT FROM AUTHOR]

In this paper, we classify the dynamic distributed load balancing algorithms for heterogenous distributed computer systems into three policies: Queue Adjustment Policy (QAP), Rate Adjustment Policy (RAP), and Queue and Rate Adjustment Policy (QRAP). We propose two efficient algorithms, referred to as Rate-based Load Balancing via Virtual Routing (RLBVR) and Queue-based Load Balancing via Virtual Routing (QLBVR), which belong to the above RAP and QRAP policies, respectively. We also consider algorithms Estimated Load Information Scheduling Algorithm (ELISA) and Perfect Information Algorithm, which were introduced in the literature, to implement QAP policy. Our focus is to analyze and understand the behaviors of these algorithms in terms of their load balancing abilities under varying load conditions (light, moderate, or high) and the minimization of the mean response time of jobs. We compare the above classes of algorithms by a number of rigorous simulation experiments to elicit their behaviors under some influencing parameters, such as load on the system and status exchange intervals. We also extend our experimental verification to large scale cluster systems such as a Mesh architecture, which is widely used in real-life situations. From these experiments, recommendations are drawn to prescribe the suitability of the algorithms under various situations. [ABSTRACT FROM AUTHOR]

This paper models and analyzes subthreshold and gate leakage currents in different double-gate (DG) devices, namely, a doped body symmetric device with polysilicon gates, an intrinsic body symmetric device with metal gates, and an intrinsic body asymmetric device with different front and back gate materials. The effect of variations in device parameters on the leakage components is also analyzed. Using the developed models, digital circuits (logic gates and static random access memory cells) designed with different DG structures are also analyzed. The analysis shows that the use of (near mid-gap) metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG devices and circuits. [ABSTRACT FROM AUTHOR]

Enhanced tornado detection and tracking can prevent loss of life and property damage. The research weather surveillance radar (WSR)-88D locally operated by the National Severe Storms Laboratory (NSSL) in Norman, OK, has the unique capability of collecting massive volumes of time-series data over many hours, which provides a rich environment for evaluating our new postprocessing algorithms. With the advent of more memory and computing power, new state-of-the-art algorithms can be explored. In this paper, an approach of identifying tornado vortices in Doppler spectra is proposed and investigated through the use of neural networks. Once the coordinate of the tornado has been established, the research question becomes the following: Can we apply target tracking algorithms to a volume of radar data to make estimations about where the tornado is going? In recent years, particle filters have attracted great attention in several research communities. These filters are used in problems where time-varying signals must be processed in real time, and the objective is to estimate various unknowns of the signals and to detect events described by the signals. The standard solutions of such problems in many applications are based on the Kalman or extended Kalman filters. In situations when the models that describe the behavior of the system are highly nonlinear and/or the noise that distorts the signals is non-Gaussian, the Kalman-filter-based algorithms provide solutions that may be far from optimal. Here, the path of the tornado follows a path that may be described by a set of nonlinear equations. To estimate the path, the particle filter will provide the better estimates. In addition to the single WSR-88D sensor designs, data fusion and tracing designs are also given for a four-node remote sensor network in central Oklahoma. By incorporating the data from each of the sensors, improvements in tracking are illustrated. The particle-filtering algorithms are especially effective in a networked system of sensors when they are in a data-fusion setting. [ABSTRACT FROM AUTHOR]

This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay. [ABSTRACT FROM AUTHOR]

In multiprocessor-based system-on-chips (SOCs), optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time; at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation-level concurrency maps to the microarchitectural-level concurrency. This paper presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication subsystem through a rigorous modeling approach based on a formal concurrency model, the operation state machine (OSM). Our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multiprocessing-element SOC prototypes. We show that, by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design. [ABSTRACT FROM AUTHOR]

In the presence of radiation, particle strikes can cause temporary signal errors in ICs. Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic and spread to memory are called single event transients (SETs). In this paper, we propose two novel approaches to hardening integrated circuits against SEUs and SETs. The proposed approaches are fully-differential dual-interlocked storage cell (DICE) and triple path DICE (TPDICE). The fully-differential DICE and TPDICE approaches are compared against two existing approaches, which are triple modular redundancy (TMR) and basic SET-tolerant DICE. All approaches except for the basic SET-tolerant DICE scheme share a common theme, which is the ability to bypass SEUs and SETs. This is critical for performance, as it allows the system to proceed with subsequent operations while a cell is recovering from the effects of a particle strike. SET pulse widths can be substantial (up to 2 ns), and so high-performance systems cannot afford to pause operations while these pulses are present. The minimum clock periods obtained for the basic SET-tolerant approach were 515 Ps with no SET, and 1310 Ps with a 500 ps SET (in 0.18 μm CMOS). In contrast, the clock periods for the bypass-capable approaches with no SET/500 PS SET were 628/749 PS for TMR, 348/480 ps for fully-differential DICE, and 434/552 PS for TPDICE. Among the approaches that bypass transient pulses, TPDICE is the most balanced. TMR suffers from overhead due to its need for external voting circuitry. In addition to this, fully-differential DICE cannot be used with combinational logic, while TPDICE can. [ABSTRACT FROM AUTHOR]

In the Data Acquisition System (DAQ) of modern high energy physics experiments, the read out system which takes data from and transfers commands to the front-end electronic systems must be capable to meet the need of high-speed and real-time. In the DAQ of the Beijing Spectrometer III (BES III) project, the read out system is designed to be based on an embedded and real-time computer system. To define and construct such real-time systems, using statecharts is an effective approach. It is introduced to build the read out system in the cosmic ray test experiment of BES III Main Drifted Chamber (MDC). This paper presents an introduction of statecharts and illustrates several methods to implement statecharts. [ABSTRACT FROM AUTHOR]

A single-board computer system created specifically to meet the demands of a new generation of small satellite missions has been designed, built and tested at Surrey Satellite Technology Limited (SSTL). The satellite onboard computer is an MPC8260 based system that was originally developed for use onboard the first Algerian satellite (Alsat-1). For the secure transaction of data between the central processing unit (CPU) of the onboard computer and its local random access memory (RAM), the program memory has been designed with triple modular redundancy (TMR), which is a hardware implementation that includes replicated memory circuits and voting logic to detect and correct a faulty value. TMR error correction technique allows single correction of one error bit per stored word. For computers on board a satellite, there is however a definite risk of two error bits occurring within one byte of stored data. In this paper, a real time low complexity codec for use in low earth orbit small satellite missions is presented and implemented in field programmable gate array (FPGA) technology. The proposed device is transparent to the routine transfer of data between the CPU and its local RAM. A simple method of decoding is adopted that allows considerable simplification of the codec with a low complexity. [ABSTRACT FROM AUTHOR]

We investigate the maximum increase in number of phrases that results from changing k consecutive symbols in a string x having length n parsed using an LZ'77-like algorithm. We consider a class of compression algorithms that partition a sequence into a collection y of nonoverlapping, variable-length phrases and encode them. Each phrase either is a singleton or matches a substring that starts to its left. We show that changing a single symbol of x in position i can yield an expansion that is of order O(n - i)2/3 as (n - i) → ∞. Our lower bound requires an alphabet size of O(n - i)1/3. We also show that changing k consecutive symbols starting from position i can yield an expansion having a similar but somewhat more involved form. The paper contains both analytically derived upper and lower bounds, and algorithms for numerically computing tighter bounds. While deriving the bounds, we provide a detailed analysis of how expansion can arise when changing consecutive symbols. This problem is motivated by management policies for computer systems, such as the IBM Memory eXpansion Technology (MXT) or the IBM iSeries compressed disks, that use LZ'77-like coding on small compression units, such as 1-4 kbyte, and store the compressed data in memory or on disk tracks. Here, when a change of a portion of the compression unit occurs, for example, an L2 cache line, or a 512-byte disk sector, the data is recompressed and potentially stored in a different location. Knowing the maximum expansion, rather than the average expansion, is an important factor for designing policies for allocation and management of memory or disk space. [ABSTRACT FROM AUTHOR]

Angular radial transform (ART), which is the region-based shape descriptor of MPEG-7, has desirable properties for representing shape information in a small number of features with no redundancy. However, in order for ART to be useful, especially in limited computing environments, the computational cost of ART must be greatly reduced. In this paper, we derive symmetric/antisymmetric properties from the bails functions of ART and present a fast and efficient method to compute the ART coefficients using these properties. The proposed method significantly reduces the number of sinusoidal operations and multiplications in computing the coefficients of ART. Moreover, the memory requirements needed to store the ART basis functions in lookup tables are only 25% of the conventional method. The experimental results are presented to show the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Effectiveness of previous SRAM leakage reduction techniques vary significantly as the leakage variation gets worse with process and temperature fluctuation. This paper proposes a simple circuit technique that adaptively trades off overhead energy for maximum leakage savings under severe leakage variations. The proposed run-time leakage reduction technique for on-die SRAM caches considers architectural access behavior to determine how often the SRAM blocks should enter a sleep mode. A self-decay circuit generates a periodic sleep pulse with an adaptive pulse period, which puts the SRAM array into a sleep mode more frequently at high leakage conditions (fast process, high temperature) and vice versa. An 0.18-μm 1.8-V 16-kbyte SRAM testchip shows 94.2% reduction in SRAM cell leakage at a performance penalty less than 2%. Measurement results also indicate that our proposed memory cell improves SRAM static noise margin by 25%. [ABSTRACT FROM AUTHOR]

This paper presents event stream-based online algorithms that fuse the data reported from processes to detect causality-based predicates of interest. The proposed algorithms have the following features. 1) The algorithms are based on logical time, which is useful to detect "cause and effect" relationships in an execution. 2) The algorithms detect properties that can be specified using predicates under a rich palette of time modalities. Specifically, for a conjunctive predicate ø, the algorithms can detect the exact fine-grained time modalities between each pair of intervals, one interval at each process, with low space, time, and message complexities. The main idea used to design the algorithms is that any "cause and effect" interaction can be decomposed as a collection of interactions between pairs of system components. The detection algorithms, which leverage the pairwise interaction among the processes, incur a low overhead and are, hence, highly scalable. The paper then shows how the algorithms can deal with mobility in mobile ad hoc networks. [ABSTRACT FROM AUTHOR]

In this paper an innovative fault tolerant solid state mass memory (FTSSMM) architecture is described. Solid state mass memories (SSMMs) are particularly suitable for space applications and more in general for harsh environments such us, for example, nuclear accelerators or avionics. The presented FTSSMM design has been entirely based on commercial off the shelf (COTS) components. In fact, cost competitive and very high performance SSMMs cannot be easily implemented by using space qualified components, due the technological gap and very high cost characterizing these components. In order to match the severe reliability requirements of space applications a COTS-based apparatus must be designed by using suitable system level methodologies [1, 2]. In the proposed architecture error-correcting codes are used to strengthen the commercial dynamic random access memory (DRAM) chips, while the system controller has been designed by applying suitable fault tolerant design techniques. Different from other proposed solutions, our architecture fully exploits the reconfiguration capabilities of Reed-Solomon (RS) codes, discriminates between permanent and transient faults reducing the use of spare elements, and provides dynamic reconfiguration and graceful degradation capability, i.e., the FTSSMM performances are gracefully reduced in case of permanent faults, maintaining part of the system functionality. The papers shows the FTSSMM design methodology, the architecture, the reliability analysis, some simulation results, and a description of its implementation based on fast prototyping techniques. [ABSTRACT FROM AUTHOR]

In this paper, we study diagnosabilities of multiprocessor systems under two diagnosis models: the PMC model and the comparison model. In each model, we further consider two different diagnosis strategies: the precise diagnosis strategy proposed by Preparata et al. [28] and the pessimistic diagnosis strategy proposed by Friedman [18]. The main result of this paper is to determine diagnosabilities of regular networks with certain conditions, which include several widely used multiprocessor systems such as variants of hypercubes and many others. [ABSTRACT FROM AUTHOR]

This paper describes and empirically evaluates the middleware platform of a new network architecture called the Bio-Networking Architecture. The Bio-Networking Architecture is inspired by the observation that the biological systems (e.g., bee colonies) have already developed mechanisms necessary to achieve future network requirements such as autonomy, scalability, adaptability, and simplicity. In the Bio-Networking Architecture, a network application is implemented as a group of distributed, autonomous and diverse objects called cyber-entities (CEs) (analogous to a bee colony consisting of multiple bees). Each CE implements a functional service related to the application and follows simple behaviors similar to biological entities (e.g., reproduction and migration). In the Bio-Networking Architecture, beneficial application characteristics (e.g., autonomy, scalability, adaptability, and simplicity) arise from the autonomous interaction of CEs. The middleware platform in the Bio-Networking Architecture, the bionet platform, provides reusable software components for developing, deploying, and executing CEs. The components abstract low-level operating and networking details, and implement high-level runtime services that CEs use to perform their services and behaviors. The components in the bionet platform are designed based on several biological concepts (e.g., energy exchange and pheromone emission). This paper describes key designs of the bionet platform and empirically demonstrates that the bionet platform is efficient, scalable, reusable, and significantly simplifies development of network applications. [ABSTRACT FROM AUTHOR]