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Aliasing Reduction in Accumulator-Based Response Verification.
- Source :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; Nov2014, Vol. 33 Issue 11, p1746-1750, 5p
- Publication Year :
- 2014
-
Abstract
- One of the well-known problems in response verification is aliasing, i.e., the event that a series of responses containing errors results in a signature equal to that of the error-free response sequence. In this paper, we propose a scheme to reduce aliasing in accumulator-based response verification. The proposed scheme is based on monitoring the value of the carry output of the accumulator. Experimental study indicates that the proposed scheme achieves significantly less hardware overhead for the same reduction in the aliasing probability than previously proposed schemes. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 02780070
- Volume :
- 33
- Issue :
- 11
- Database :
- Complementary Index
- Journal :
- IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
- Publication Type :
- Academic Journal
- Accession number :
- 99041720
- Full Text :
- https://doi.org/10.1109/TCAD.2014.2351582