Search

Blind source separation (BSS) is the process of extracting sources from mixed data without or with limited awareness of the sources. This paper uses field programmable gate array (FPGA) to create an effective version of the Blind source separation algorithm (ICA) with a single Multiply Accumulate (MAC) adaptive filter and to optimize it. Recently, space research has paid a lot of attention to this technique. We address this problem in two sections. The first approach is ICA, which seeks a linear revolution that can enhance the mutual independence of the mixture to distinguish the source signals from mixed signals. The second is a powerful flexible finite impulse response (FIR) filter construction that makes use of a MAC core and is adaptable. The adjustable coefficient filters have been used in the proposed study to determine the undiscovered system utilizing an optimal least mean square (LMS) technique. The filter tap under consideration in this paper includes 32 taps, and hardware description language (HDL) and FPGA devices were used to carry out the analysis and synthesis of it. When compared to the described architecture, the executed filter architecture uses 80% fewer resources and increases clock frequency by nearly five times, and speed is increased up to 32%. [ABSTRACT FROM AUTHOR]

Feature extraction and matching are the basic procedures of the so-called Visual Odometer (VO), Simultaneous Localization and Mapping (SLAM) and many other image processing algorithms. Oriented features from accelerated segment test (FAST) and rotated binary robust independent elementary features (ORB) algorithm are widely used since they are computationally faster. In this paper, we proposed a method to generate a value for a feature, the value is called signature. In the matching step, we only compute Hamming distances of descriptors with the same signatures. Hence, the matching time is shortened. Compared with the original ORB algorithm, features to be matched dropped 69.63% on TUM datasets and 85.7% on VGG datasets by adopting our strategy. In addition, the precision is above 85% on both VGG and TUM datasets. We design a customized hardware architecture for ORB feature extraction and matching based on the proposed method. The hardware structure is implemented on Xilinx ZCU102 evaluation board. The clock frequency is set to 150 MHz. Our Field Programmable Gate Arrays (FPGA) system achieves 193 fps on 1 2 8 0 × 7 2 0 images with 1984 features on average and 314 fps on 6 4 0 × 4 8 0 images with 700 features on average, which is more efficient compared to the state-of-the-art works. [ABSTRACT FROM AUTHOR]

Heart failure is one of the major diseases endangering human life. As a transitional support treatment before heart transplantation, the left ventricular assist device (LVAD) has significantly improved the quality of life and survival rate of patients with end-stage heart failure. In the automatic detection of electrocardiogram (ECG), the detection of QRS wave groups is the most critical aspect, which affects the correctness and accuracy of subsequent data analysis and processing. The paper used the data from the MIT-BIH database and the data collected from human ECG as the original number of samples for further processing. It processed the data through a high-order finite impulse response (FIR) low-pass filter and Shannon energy algorithm, and added the use of a high-order adaptive median filter algorithm on a field programmable gate array (FPGA) to minimize the noise of the processed real-time data. Finally, the tested ECG R-wave was used to drive the LVAD. After successful simulation by MATLAB and Modelsim software, the scheme of the real-time ECG signal controlling blood pump system was realized on the FPGA platform. The experiment showed that the method proposed could accurately extract the R-wave and control the LVAD to pump blood simultaneously. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable image confusion scheme, which uses Linear Congruential Generators (LCGs)-based Pseudorandom Bits Generator (PRBG). The PRBG is based on the variable input-coupled LCG with a reconfigurable clock divider. The proposed algorithm encrypts the input image up to four times successively using different random sequences in every attempt. This new scheme aims to efficiently extract statistically strong pseudorandom sequences from a proposed PRBG with a large keyspace and simultaneously increase the security level of the encrypted image. This PRBG was initially designed on Virtex-5 (XC5VLX110T), Virtex-7 (XC7VX330T) and Artix-7 (XC7A100T) Field Programmable Gate Arrays (FPGAs). The statistical properties of the proposed PRBG for four different configurations are verified by the National Institute of Standards and Technology (NIST) tests. Thereafter, a reconfigurable encryption/decryption algorithm that uses the proposed PRBG is developed for secure image encryption. The encryption process was accomplished using the MATLAB tool after obtaining the PRBG keys from the FPGA. To show the quality and strength of the encryption process, security analysis [correlations and Number of Pixels Change Rate (NPCR)] is performed. Security analysis results are compared with the conventional encryption algorithm to show that the developed reconfigurable encryption scheme provides better results in security tests. [ABSTRACT FROM AUTHOR]

Custom computing architectures on field programmable gate array (FPGA) platforms are a viable solution to further accelerate convolutional neural network (CNN) inference. However, due to the large size feature map matrix data, the optimization of CNN feature maps storage computing on FPGA remains a challenge. To overcome these challenges, a FPGA-oriented memory access optimization method for CNN is proposed. Firstly, the feature map partition strategy is used to group the feature map efficiently. Second, the input and the output caching rotation methods are employed in adaptive memory access mode. Third, a caching hybrid rotation method is proposed to optimize memory access performance and can effectively reduce the access time of the CNN feature map. Experimental results based on SkyNet and VGG16 show that the inference speed of the proposed model is accelerated by 7.1 times compared with the previous conventional memory access optimization for CNN on FPGA. Through the evaluation of computational energy efficiency, our method can be improved by 6.4 times compared to the current typical accelerators. [ABSTRACT FROM AUTHOR]

This paper focuses on the design of multi-structure controllers (MSCs) for KY negative output boost converter (KYNOBC) functioned in continuous current mode (CCM) for low-power source applications. KYNOBC is one of the topologies of DC–DC converter that performs the positive DC input supply voltage into a negative output voltage. Dynamic behavior of KYNOBC is nonlinear in nature because of its time-changing operation. The single loop control does not regulate the multi-parameters of KYNOBC during the line and load variations owing to that it produces poor transient and dynamic analyses. With the aim of controlling the multi-parameters of KYNOBC such as inductor current and output voltage, enriching the transient and dynamic analysis, the MSCs are recommended in this paper. In our study, MSCs for KYNOBC consist of two loops such as inner proportional (P) controller inductor current loop for modulating the converter current and outer fuzzy logic controller (FLC)/proportional integral (PI) controller voltage loop for regulating the output voltage. The P and PI values are determined from the mathematical modeling of KYNOBC and the fuzzy rules are framed based on its performance without modeling equations. The behaviors of the KYNOBC with MSCs are validated at various zones by making the MATLAB/Simulink simulations and prototype model. The controller parameters are realized in prototype field programmable gate array (FPGA). The responses are recorded to indicate the dexterous of the MSCs for it. [ABSTRACT FROM AUTHOR]

Recently, there have been continuous rising interests of multi-bit error correction codes (ECCs) for protecting memory cells from soft errors which may also enhance the reliability of memory systems. The single error correction and double error detection (SEC-DED) codes are generally employed in many high-speed memory systems. In this paper, Hsiao-based SEC-DED codes are optimized based on two proposed optimization algorithms employed in parity check matrix and error correction logic. Theoretical area complexity of SEC-DED codecs require maximum 49.29%, 18.64% and 49.21% lesser compared to the Hsiao codes [M. Y. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBM J. Res. Dev.14 (1970) 395–401], Reviriego et al. codes [P. Reviriego, S. Pontarelli, J. A. Maestro and M. Ottavi, A method to construct low delay single error correction codes for protecting data bits only, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.32 (2013) 479–483] and Liu et al. codes [S. Liu, P. Reviriego, L. Xiao and J. A. Maestro, A method to recover critical bits under a double error in SEC-DED protected memories, Microelectron. Reliab.73 (2017) 92–96], respectively. Proposed codec is designed and implemented both in field programmable gate array (FPGA) and ASIC platforms. The synthesized SEC-DED codecs need 31.14% lesser LUTs than the original Hsiao code. Optimized codec is faster than the existing related codec without affecting its power consumption. These compact and faster SEC-DED codecs are employed in cache memory to enhance the reliability. [ABSTRACT FROM AUTHOR]

March algorithms are widely used in Memory Built-In Self-Test (MBIST) on-chip memory testing, providing linear test complexities that reduce the test time and cost. However, studies show that March algorithms with complexities lower than 18N have poor coverages of faults that have emerged with the advent of the nanometer process technologies and are more relevant to nowadays memories. New March AZ1 and March AZ2 algorithms, with 13N and 14N complexities, respectively, were introduced to provide optimum coverage of those faults and to produce a shorter test than an 18N-complexity test algorithm with a lesser area overhead, thus reducing chip manufacturing costs. This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. The FPGA experimental tests demonstrated that they function correctly as the expected test sequences were observed. In addition, their fault detection abilities were also validated through tests on a fault-injected memory model, which shows that the implemented March AZ1 and March AZ2 provide 80.6% and 83.3% coverage of the intended faults, respectively, which outperform any other existing 14N-complexity March algorithms. [ABSTRACT FROM AUTHOR]

Field Programmable Gate Arrays (FPGAs) are often used in space, military, and commercial applications due to their re-programmable feature. FPGAs are semiconductor components susceptible to soft errors due to radiation effects. Fault tolerance is a critical feature for improving the reliability of electronic and computational components in high-safety applications. Triple Modular Redundancy (TMR) is electronic systems' most commonly used fault-tolerant technique. TMR is reliable and efficient to recover the single-event upsets. However, the limitation of this technique is the area overhead. Prior work has proposed many conventional fault-tolerant approaches that have been unable to avoid area overhead. This paper introduces a novel work related to an error analysis-based technique. This technique works with an error percentage, and a preferential algorithm, which is also proposed to reduce the hardware complexity in the existing works. This technique can be applied on various types of arithmetic circuits. The proposed technique is applied to the adder circuit to verify the hardware usage, power consumption, and delay; it has been implemented on the Proasic3e 3000 FPGA. The simulated results were observed as 39.89% fewer IO cells, 47.10% fewer core cells, and 5.32% less power as compared to the TMR-based adder. [ABSTRACT FROM AUTHOR]

Recently, there is increasing interest in impedance sensors for various applications. Direct digital synthesis (DDS) circuits are commonly used in such sensor circuits for generating stimulus signals, due to advantages of accurate frequency control, drift-free performance, etc. Previously reported DDS circuits for sensor applications typically maintain superb frequency accuracy within relatively small frequency ranges. This paper investigates techniques to improve frequency accuracy over wide frequency ranges. In addition, it presents an analytical framework to estimate the signal to noise ratio (SNR) of the generated signal and derives guidelines for optimizing DDS circuit configurations. Both simulation and hardware measurement results are presented to validate the derived SNR estimation equation as well as the developed frequency accuracy enhancement techniques. [ABSTRACT FROM AUTHOR]

The aim of this paper is to develop and test the features of reconfigurable architecture for its suitability for a secured medical image encryption. The image security has been ensured using three-level zigzag confusion, bit-level confusion, self-invertible matrix and DNA diffusion. The zigzag pixel-level and circular shift-based bit-level confusion offer a good scrambling to overcome the correlation among the pixels whereas the self-invertible matrix is used to have a better substitution effect. The DNA operations are performed to get new random-valued sequence for diffusion thereby the encryption process has been designed to get good protection with simple and effective coding. The concept of secured medical image encryption has been designed using verilog HDL and implemented using field programmable gate array (FPGA) with an intention to create a standalone embedded hardware for encryption. The analysis of the encryption includes correlation coefficient, entropy, Chi-square analysis, NPCR and UACI and so on, which gives a better result and conveysto us that it can resist the statistical and differential attacks. The synthesis report of the embedded hardware has been presented to understand the utilization of the FPGA. [ABSTRACT FROM AUTHOR]

Electrocardiogram (ECG) is considered as the important diagnostic tests in medical field for detecting the cardiac anomalies. But, the ECG signals are polluted with numerous noise from power line intrusion, muscle noise, baseline wander, motion artifacts, low frequency noise signals, high frequency noise signals and T-wave, which automatically affects the QRS profile. The existing method provides the result in lesser accuracy with higher rate of error detection. To overcome these issues, QRS detector using modified maximum mean minimum (MoMaMeMi) filter optimized with mayfly optimization algorithm (QRS-MoMaMeMi-MOA) is proposed in this paper for less computational cost along with resource requirements. The proposed filter design consists of two phases for detecting QRS detector, such as filtering process associated to the enhancement and detection phase. Initially, the ECG data are taken from MIT/BIH arrhythmia dataset (MIT-AD). For eradicating the baseline wander in ECG data, MaMeMi filter is used. For expanding the performance of the modified MaMeMi filter, filter parameters, such as σ and Δ are optimized by MOA to accomplish the best values and measure the performance of the whole QRS detector. For high frequency noise suppression in ECG data, the range function, noise subtractors, modified triangular detector are used. Then, heart beat detection can be done with the help of adaptive thresholding technique. The proposed filter design is carried out in MATLAB and implemented on field programmable gate arrays (FPGAs). The proposed QRS-MoMaMeMi-MOA filter design had 0.93%, 0.12% and 0.19% higher accuracy and 89.32%, 50% and 62% low detection error rate, compared to the existing filters, like Kalman filtering based adaptive threshold algorithm for QRS complex detection (QRS-KF-ATA), QRS detection of ECG signal utilizing hybrid derivative with MaMeMi filter by efficiently removing the baseline wander (QRS-HD-MaMeMi), and knowledge-based QRS detection operated by cascade of moving average filters (QRS-CAF). Then, the device utilization of the proposed FPGA implementation of the QRS-MoMaMeMi-MOA filter provides 95.556% and 71.428% lower power usage compared with the existing algorithms, like Kalman filtering based adaptive threshold algorithm for QRS complex detection in FPGA (FPGA-QRS-KF-ATA), and efficient architecture for QRS detection in FPGA utilizing integer Haar wavelet transform (FPGA-QRS-IHWT). [ABSTRACT FROM AUTHOR]

Nowadays, a computer-aided diagnosis system is required to monitor the cardiac patients continuously and detecting the heart diseases automatically. In this paper, a new field programmable gate array-based morphological feature extraction approach is proposed for electrocardiogram signal analysis. The proposed architecture is mainly based on the Generalized Synchrosqueezing transform but a detrended fluctuation analyzer is applied in the reconstruction stage for capturing the maximum information of QRS complexes and P-waves by eliminating a set of noisy intrinsic modes. Then, a correntropy envelope is determined from the QRS enhanced signal for localizing the QRS region accurately. Also, an adaptive heuristic framework is introduced to detect the true P-wave from the P-wave enhanced reconstructed signal by analyzing both the positive and negative amplitudes. In addition, a root mean square Error estimation-based adaptive thresholding approach is used to estimate the T-wave after removing the P-QRS complexes. The proposed architecture has been implemented on field programmable gate array using the Xilinx Vertex 7 platform. The performance of the proposed architecture is validated by performing a comparative study between the resultant performances and those attained with state-of-the-art feature descriptors, in terms of Sensitivity, accuracy, positive prediction, error rate and field programmable gate array resources estimation. The proposed sensitivity, accuracy and positive prediction are 99.84%, 99.85% and 99.86% for QRS detection approach. The proposed sensitivity, accuracy and positive prediction are 99.45%, 99.23% and 99.78% for P-wave detection approach. The proposed sensitivity, accuracy and positive prediction are 99.58%, 99.65% and 100% for T-wave detection approach. The simulation results show that the proposed architecture overtakes existing designs and minimizes hardware complexity, which proves the suitability of this approach on real-time applications of electrocardiogram signals. [ABSTRACT FROM AUTHOR]

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software-Defined Radio (SDR) in a reasonable area. New issues can arise due to usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. Also, the Clock Domain Crossing (CDC) verification of the dynamically reconfigurable systems is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. This paper summarizes our previous work to address these verification challenges for DPR. The approaches are demonstrated on a SDR system to show the effectiveness of applying these approaches in the design cycle. [ABSTRACT FROM AUTHOR]

The paper presents a complete approach to the multithreaded execution of a control program prepared according to IEC61131-3 standard. The program is mapped to a dedicated multiple-core CPU unit. The CPU consists of multiple independent bit and word CPUs. The computation synchronization mechanism is based on memory cells with semaphored access, which enable hardware-level synchronization. The paper presents in detail the architecture, results of implementation and the achieved performance. The custom-developed compiler translates standard programming languages into a multithreaded executable form. It utilizes an original intermediate data flow graph to optimize and recognize program parallelisms. The program is automatically partitioned and mapped to the available computing resources. The paper is concluded with a performance comparison of program executions using the standard single-threaded and proposed approaches. [ABSTRACT FROM AUTHOR]

In this paper, time-frequency distributions (TFDs) and their hardware implementation on FPGA are presented. TFDs are evolved due to disadvantage of Fourier Transform (FT), which cannot provide time information in spectrum representation. Time-Frequency Representations (TFRs) are helpful in providing simultaneous information about spectral contents of a signal with respect to time period axis. The major problem associated with hardware implementation of TFDs is limited on-board memory. Forward and backward register allocation method (FBRA) is employed to obtain the optimum register occupation. A register of length 32-bit is considered for the input signal representation. The stored register values are applied to the proposed TFDs and computed using real-time hardware. FBRA is implemented during the computation of FFT in all TFDs. All the transforms are modeled using Verilog code and implemented on SPARTA-6 FPGA. A real-time ECG, earthquake and a quad chirp signals are taken as input to test the designed TFDs. Finally, a comparison of different hardware resources utilized on FPGA with earlier conventional methods for better real-time applications was made. [ABSTRACT FROM AUTHOR]

Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available memories. Our paper includes a new replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on our methodology. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a novel integer-order memristor-modified Shinriki circuit (MMSC). We investigate the dynamic properties of the MMSC system and the existence of chaos is proved with positive largest Lyapunov exponent. Bifurcation plots are derived to analyze the parameter dependence of the MMSC system. The fractional-order model of the MMSC system (FOMMSC) is derived and the bifurcation analysis of the FOMMSC system with the fractional orders is carried out. Fractional-order adaptive sliding-mode controllers (FOASMCs) and genetically optimized PID controllers are designed to synchronize identical FOMMSC systems with unknown parameters. Numerical simulations are conducted to validate the theoretical results. FPGA implementation of the FOASMC controllers is presented to show that the proposed control algorithm is hardware realizable. MMSC has trigonometric functions which make the system more complex and the optimization and synchronization of such systems in the integer order itself are harder, so the paper does the same in fractional order. The proposed system is a memristive circuit which can show special features such as multistability, hyperchaos, and multiscroll attractor. Such a system with these features is very rare in the literature. [ABSTRACT FROM AUTHOR]

In this paper, we present an efficient and fast system-level power estimation model for the FPGA-based designs. To estimate the dynamic power early, first time, LLVM IR code analysis is employed at the C-level designs and then the neural network-based estimation model is built from the information obtained from this high-level profiling. The model accuracy is validated through designs of heterogeneous domains from the CHStone and MachSuite benchmarks. An insignificant relative error of 0.21–3.6% is observed for the analyzed benchmark designs with the exceptional increase in the estimation speed by 63 times of magnitude as compared to the Xilinx Vivado Design Suite. Moreover, the model eliminates the need for synthesis-based exploration. In addition, the effectiveness of proposed approach is also verified through a comparison with the other reported works. [ABSTRACT FROM AUTHOR]

FPGA (Field Programmable Gate Array) has the advantages of parallelism and reconfigurability, therefore, it is widely used in areas such as image processing, robotics and artificial intelligence. However, the development of FPGA currently involves too many hardware details, so it lacks extensibility for different platforms and flexibility for system level management and scheduling. In this paper, we propose an FPGA Virtualization Mechanism (FVM), which divides physical resources into pages (virtual resources). We use the technology of PR (Partial Reconfiguration) and the method of intermediate form to lift the extensibility and performance. We implement FVM in our platform VSC (Vary Super Computer System). Experiment results show that FVM can solve the problem of extensibility and flexibility, with high performance. [ABSTRACT FROM AUTHOR]

Data security, privacy and authenticity are crucial in wireless data transmission. Low power consumption is the main requirement for any chip design targeting the Internet of Things (IoT) applications. In this research paper, a comparative study of eight authenticated encryption and decryption algorithms, selected from the "Competition for Authenticated Encryption: Security, Applicability and Robustness" (CAESAR), namely, ACORN, ASCON, CLOC, JOLTIK, MORUS, PRIMATEs, SCREAM and SILC, is presented. The FPGA and ASIC implementations of these eight algorithms are synthesized, placed and routed. Power, area, latency and throughput are measured for all algorithms. All results are analyzed to determine the most suitable algorithm for IoT applications. These results show that ACORN algorithm exhibits the lowest power consumption of the eight studied at the expense of lower throughput and higher latency. MORUS algorithm gives the highest throughput among the eight selected algorithms at the expense of large area utilization. [ABSTRACT FROM AUTHOR]

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models. [ABSTRACT FROM AUTHOR]

In this paper, a high speed elliptic curve cryptographic (ECC) processor for National Institute of Standards and Technology (NIST) recommended prime P − 2 5 6 is proposed. The modular arithmetic components in the proposed ECC processor are highly optimized at both architectural level and circuit level. Redundant-signed-digit (RSD) arithmetic is adopted in the modular arithmetic components to avoid lengthy carry propagation delay. A high speed modular multiplier is designed based on an efficient segmentation and pipelining strategy. The clock cycle count is reduced as result of the segmentation, whereas operating frequency and throughput are significantly increased due to the pipelining. An optimized pipelined architecture for modular division is also presented which is suitable for the design of ECC processor using projective coordinates. The Joye's double and add (DAA) algorithm based on X Y -only common Z (co- Z) coordinate is adopted at the system level for its regular and efficient behavior. The proposed ECC processor is flexible and can be implemented using any field programmable gate array (FPGA) family or standard cell libraries. The proposed ECC processor executes a single elliptic curve (EC) point multiplication (PM) operation in 0.47 ms at a maximum frequency of 327 MHz on Virtex-6 FPGA. The implementation results demonstrate that the proposed ECC processor outperforms the other contemporary designs reported in the literature in terms of speed and area × time metrics. [ABSTRACT FROM AUTHOR]

Due to their structure and complexity, chaotic systems have been introduced in several domains such as electronic circuits, commerce domain, encryption and network security. In this paper, we propose a novel multidimensional chaotic system with multiple parameters and nonlinear terms. Then, a two-phase algorithm is presented for investigating the chaotic behavior using bifurcation and Lyapunov exponent (LE) theories. Finally, we illustrate the performances of our proposal by constructing three (03) chaotic maps (3-D, 4-D and 5-D) and implementing the 3-D map on Field-Programmable-Gate-Array (FPGA) boards to generate random keys for securing a client–server communication purpose. Based on the achieved results, the proposed scheme is considered an ideal candidate for numerous resource-constrained devices and internet of the things (IoT) applications. [ABSTRACT FROM AUTHOR]

This paper exposes circuit design of linear congruential generator (LCG) and implementation in FPGA based on block reduction technique. The circuit is derived from LCG algorithm proposed by Lehmer. Block reduction technique has been used to simplify the circuit. Several net connections among the blocks of the circuit are ignored or disconnected and the multiplier is replaced by a shifter. Simulations of both behavior and timing have been done and the results confirm its algorithm. The Cyclone II EP2C8Q208C8N and Cyclone IV E EP4CE115F29C7N of Altera have been chosen to extract comparison data of speed and occupied area. Further comparison of shift technique and the wordlengths reduction technique has been made. In general, the proposed design is far simpler than the previous published LCG circuit. [ABSTRACT FROM AUTHOR]

Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01ns can detect more than 80% of Trojans. [ABSTRACT FROM AUTHOR]

With the increasing requirements of transmitting larger amounts of diverse video and image data, the PCI express (PCIe) interface has been extensively used in high-speed digital systems for multimedia processing and communication. However, the existing PCIe transmission methods are not efficient to transmit multi-channel videos on FPGA processors, as they waste PCIe bandwidth and hardware resources. In this paper, an efficient PCIe transmission method for multi-channel video is presented on an FPGA processor. First, to reduce the programmed I/O (PIO) write latency, the command caching method is adopted. The traditional DMA descriptors are transformed into DMA commands, which are smaller, and the command buffer is used to store these commands. Second, a dynamic splicing mechanism is proposed for data transmission and commands the scheduling separately. The multi-type data is transmitted concurrently in this dynamic splicing mechanism. Moreover, the adjacent commands are spliced into one command, which reduces the DMA initiation times. Finally, the direct kernel memory access technique and timer self-feedback monitor technique are applied to improve the transmission efficiency and enhance the system reliability. The experimental results show that the transmission efficiency of the proposed method is increased by nearly 30% compared with other conventional methods, and the highest measured transfer rate is 1631 Mbytes/s on write and 1582 Mbytes/s on read, which reaches 84.4% of the theoretical maximum. [ABSTRACT FROM AUTHOR]

Fixed-point multiplication is an important operation that is frequently used in many digital signal processing (DSP) applications. The operation is computationally intense and very often the performance of multiplier determines the overall performance of DSP system. Evidently, a wide range of approaches have been proposed for efficient implementation of fixed-point multipliers on different hardware platforms. In this paper, we use Coordinate Rotation DIgital Computer (CORDIC) algorithm to perform fixed-point multiplication operation. The motivation for our approach is based on the fact that CORDIC is a hardware-efficient algorithm, wherein accuracy can be traded-off for performance. Our implementation targets field programmable gate arrays (FPGAs) and focuses on exploiting the underlying general and specialized fabric to the fullest. Performance comparisons against various traditional and recent approaches show that a substantial improvement is achievable by using CORDIC-based multipliers. We have also implemented a recently proposed convolution architecture using CORDIC-based multipliers. The results show that a proper choice of CORDIC architecture can result in an improvement of performance parameters like resource utilization, throughput and dynamic power. This, however, is achieved in lieu of a small cost in accuracy. Our analysis of an 8-stage CORDIC multiplier reports a mean absolute percentage error (MAPE) of 6.032 — a factor that reduces exponentially with increasing number of stages. [ABSTRACT FROM AUTHOR]

Applying unified formula while computing point addition and doubling provides immunity to Elliptic Curve Cryptography (ECC) against power analysis attacks (a type of side channel attack). One of the popular techniques providing this unifiedness is the Binary Huff Curves (BHC) which got attention in 2011. In this paper we are presenting highly optimized architectures to implement point multiplication (PM) on the standard NIST curves over and using BHC. To achieve a high throughput over area ratio, first of all, we have used a simplified arithmetic and logic unit. Secondly, we have reduced the time to compute PM through Double and Add algorithm. This is achieved by increasing the frequency of operation through a 2-stage pipelined architecture. The increase in clock cycles caused by consequent pipeline hazards is controlled through optimal scheduling of computations involved in PM. The synthesis results show that our designs can work up to a frequency of 377MHz on Xilinx Virtex 7 FPGA. Moreover, the overall throughput/area ratio achieved through the adopted approach is up to 20% higher while comparing with available state-of-the-art solutions. [ABSTRACT FROM AUTHOR]

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing satellites and space systems. Unfortunately, these devices are extremely sensitive to various kinds of unwanted effects induced by space radiations especially single-event upsets (SEUs) as soft errors in configuration memory. To face this challenge, a variety of soft error mitigation techniques have been adopted in literature. In this paper, we describe an area-efficient multiplier architecture based on SRAM-FPGA that provides the self-checking capa-bility against SEU faults. The proposed design approach, which is based on parity prediction, is able to concurrently detect the SEU faults. The implementation results of the proposed ar-chitecture reveal that the average area and delay overheads are respectively 25% and 34% in comparison with the plain version while the conventional duplication with comparison (DWC) architecture imposes 117% and 22% overheads. Moreover, the single and multi-upset fault injection experiments reveal that the proposed architecture averagely provides the failure coverage of 83% and 79% while the failure coverage of the duplicated structure is 85% and 84%, respectively for SEU and MEU faults. [ABSTRACT FROM AUTHOR]

Field programmable gate array (FPGA) implemented array of Duffing oscillators for weak signal detection in noisy environments is presented in this paper. The array of Duffing oscillators is an efficient method for detecting weak signals with unknown exact frequency and phase delay. Because of the high computation resource requirement, especially for online weak signal detection, hardware implementation is a proper solution. In this FPGA implementation, the array was constructed using multiprocessor Nios II system. In the proposed multiprocessor system, each oscillator was implemented by a separate Nios II processor. Also, a separate Nios II processor was dedicated to control and detect the state of other oscillators. The proposed system was implemented using one of the Altera's Cyclone IV GX FPGAs. In this paper, beside the structure and resource utilization of the array of oscillators, an experimental result was also presented in order to show effectiveness of the implementation. [ABSTRACT FROM AUTHOR]

This paper deals about the development of intelligent controllers (ICs) for load voltage regulation of a double switch noninverting buck-boost DSNIBBC operated in pseudo continuous coil current (PCCC). The DSNIBBC is a kind of DC-DC converter, which converts the positive DC source voltage into the positive DC load voltage (buck to boost mode and boost to buck mode). Due to the time changing, ON/OFF characteristics along with its transient and dynamic characteristics of DSNIBBC have become nonlinear. Since the classical linear controllers are inappropriate to enhance the transient and dynamic performances of DSNIBBC, ICs are designed to improve the load control of the same DSNIBBC operated in transient and dynamic regions. In this paper, two ICs, namely, fuzzy logic controller (FLC) and neuro controller (NC) incorporated in the load voltage regulation loop are utilized. The performance comparison between the ICs and the classical proportional integral (PI) controller is discussed and validated at various regions through both software and prototype field programmable gate array [FPGA] plants. The responses are depicted to support the designed ICs. [ABSTRACT FROM AUTHOR]

Today, field programmable gate array (FPGA) is becoming widely used as computational accelerators in many application domains such as image/video processing, machine learning, and data mining. The inherent tolerance to the imprecise computation in such domains potentially provides an opportunity to trade quality of the results for higher energy efficiency. Therefore, this paper proposes a systematic methodology aiming to find the optimal energy saving corresponding to different quality bound, by approximating register-transfer level (RTL) designs on FPGA. As a case study, first, we investigate imprecise design on two submodules — adders and multipliers. By integrating the two combinational submodules with finite state machines (FSMs), several designs on a sequential circuit — color-to-grayscale converter — are further presented to offer a diverse range of energy consumption related to different quality constrains. Through this, we are able to set energy–quality (E–Q) parameters of our proposed methodology and configure the approximation knobs, capable of maximizing energy savings within different application-based quality margins. Experimental result demonstrates that leveraging E–Q leads to an average 1. 3 7 – 2. 1 6 × savings in energy for modest loss in application output quality (< 3 %), and 2. 3 1 – 2. 5 0 × energy savings for impact on relaxed quality constraints (3–7.5%). [ABSTRACT FROM AUTHOR]

Digital Cryptosystems play an inevitable part in modern-day communication. Due to the complexity involved in the execution of crypto algorithms, it is realized as modular arithmetic modules. Generally, multipliers are the most time-consuming data path elements which influence the performance of modular arithmetic implementations. In this paper, the design of a hierarchy-based parallel signed multiplier without sign extension is presented. A mathematical model of the algorithm, two VLSI architectures, namely, Carry Save Adder (CSA)-based design and Parallel Prefix-based architecture are proposed. Mathematical equations of the multiplier are verified using MATLAB tool and the architectures are coded in Verilog HDL. The functionality of the same is tested using a Zynq Field Programmable Gate Array (FPGA) (XC7Z020CLG484-1), and the synthesized results are presented. Parameters, such as area, power, delay, Power Delay Product (PDP) and Area Delay Product (ADP), are compared by synthesizing the designs in Cadence RTL compiler with 180 nm, 90 nm and 45 nm TSMC CMOS technologies. The results show that CSA-based multiplier architecture has achieved an improved PDP performance of 20% with an optimum area compared to recent work. It also shows that the parallel prefix architecture has made a 27% improvement in speed with a better PDP. By using the proposed signed multiplier, modulo 2 n − 1 and 2 n + 1 signed arithmetic modules are implemented. [ABSTRACT FROM AUTHOR]

The evolvable hardware (EHW) is widely used in the design of fault-tolerant system. Fault-tolerant system is really a real-time system, and the recovery time is necessary in fault detection and recovery. However, when applying EHW, real-time characteristic is usually ignored. In this paper, a fault-tolerant strategy based on EHW is proposed. The recovery time, predicted by the fault tree analysis (FTA), is considered as a constraint condition. A configuration library is set up in the design phase to accelerate the repair process of the anticipated faults. An evolvable algorithm (EA) based on similarity is applied to evolve the repair circuit for the unanticipated faults. When the library reaches the upper, the target system is reconfigured by the EA-repair technology. Extensive experiments are conducted to show that our method can improve the fault-tolerance of the system while satisfying the real-time requirement on FPGA platform. In a long run system, our method can keep a higher fault recovery rate. [ABSTRACT FROM AUTHOR]

In this paper, an area competent field-programmable gate array (FPGA) execution scheme of elliptic curve cryptography (ECC) is depicted. There are numerous limitations in traditional encryption algorithms such us Rivest Shamir Adleman (RSA), Advanced Encryption Standard (AES) in respect of security, power, and resources at the real-time performance. The ECC is mounting as an imperative cryptography, and gives you an idea about a promise to be the substitute of RSA. In this paper, ECC processor architecture over Galois Fields (GFs) with the multitalented bit serial multiplier is depicted which accomplishes the greatest area and power performance over traditional digit-serial multiplier. In addition, the vigilant scheduling operation was employed to diminish the involvedness of logic unit operations in ECC processor. The anticipated architecture is executed on vertex4 FPGA expertise in Xilinx software. We demonstrate that results perk up the performance of the enhanced design by contrasting with the traditional design. [ABSTRACT FROM AUTHOR]

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given. [ABSTRACT FROM AUTHOR]

Boolean Satisfiability (SAT)-based channel routing with via-aware pin doglegging is presented in this paper. The effect of the pin dogleg layout of connecting wires has been tested separately for input-output pins and output pins only with controlled use of vias for dogleg during detailed routing. Dogleg may reduce the channel width required for laying down all nets and hence decrease the total chip area. However, invalid selection of dogleg may increase the channel width or may identify a routable circuit as unroutable. Unwanted dogleg may also increase the use of vias (switches) required for changing the track from one to another and may create a congested area with vias. Congested via may introduce lithographic printing problem during manufacturing and power leakage problem. The proposed technique considers all these constraints to provide an optimal result and gives a compact layout for a circuit with controlled via for doglegging. The results obtained show that pin dogleg layout produces a more compact layout for connecting wires with supervised via when compared to dogleg-free routing or doglegged routing with unsupervised via for some standard benchmark circuits. It yields optimal results with reduced number of tracks in a channel and smaller chip size. [ABSTRACT FROM AUTHOR]

The conventional direct torque control (DTC), based on the hysteresis controllers and the switching table, operates with a variable switching frequency, which decreases the conventional DTC performances, like the torque and flux ripples. Thus, the space vector modulation (SVM), used in the DTC, ensures a constant switching frequency and improves the DTC performances. The first aim of this paper is to present a comparison study between the DTC with an SVM (DTC-SVM) based on the Proportional Integral regulators (DTC-SVM-PI) and the DTC-SVM based on the sliding mode controllers (DTC-SVM-SMC). These two approaches are complex control algorithms which require faster micro-controllers; therefore the second objective of this paper is to present the implementation of the DTC-SVM-PI and the DTC-SVM-SMC on the Field Programmable Gate Array (FPGA), due to the parallel processing capability of the FPGAs. The two approaches are designed and simulated using the Xilinx System Generator (XSG) and implemented using an FPGA Virtex 5. The simulation results in the transient behavior and the steady state of the induction motor controlled by these two approaches are compared and discussed. The hardware FPGA implementation results show the effectiveness of the FPGA relative to the digital signal processor in terms of execution time. [ABSTRACT FROM AUTHOR]

In this paper, a timing error predictor (TEP) for adaptive frequency scaling (AFS) is proposed on a field-programmable gate array (FPGA). The use of TEP-based AFS can minimize large timing margin which is added to a clock cycle time for tolerating process, voltage, and temperature (PVT) variations. On an FPGA, in general, the typical dynamic frequency scaling has used the feature of dynamic frequency synthesis (DFS) in a digital clock manager (DCM). However, it has a long locking time. Moreover, during the DCM reconfiguration for generating a new frequency, the lock signal of the DCM can be lost and it leads to possible glitches or spikes at the output. In this work, a variable-length ring oscillator (VLRO), which employs a high-speed carry chain in an FPGA, is proposed to replace the DCM for changing the frequency within one clock cycle without introducing any glitches. Furthermore, an in-situ TEP, which detects timing errors, is combined with VLRO to further reduce the timing margin of a target system. Our proposed in-situ TEP-based AFS scheme is applied to a 1 6 × 1 6 -bit multiplier and implemented on a Spartan-6 FPGA device (XFC6SLX45). The functional correctness of the TEP is verified under various DC supply voltages and operating frequencies. The experimental results show that the proposed TEP-based AFS system switches the clock frequency correctly within two clock cycles and improves circuit performance up to 1. 6 2 × at the nominal operating condition by minimizing the timing margin. [ABSTRACT FROM AUTHOR]

In this paper, we present a new generic architectural approach of a Self-Organizing Map (SOM). The proposed architecture, called the Diagonal-SOM (D-SOM), is described as an Hardware–Description-Language as an intellectual property kernel with easily adjustable parameters.The D-SOM architecture is based on a generic formalism that exploits two levels of the nested parallelism of neurons and connections. This solution is therefore considered as a system based on the cooperation of a distributed set of independent computations. The organization and structure of these calculations process an oriented data flow in order to find a better treatment distribution between different neuroprocessors. To validate the D-SOM architecture, we evaluate the performance of several SOM network architectures after their integration on a Xilinx Virtex-7 Field Programmable Gate Array support. The proposed solution allows the easy adaptation of learning to a large number of SOM topologies without any considerable design effort. 1 6 × 1 6 SOM hardware is validated through FPGA implementation, where temporal performance is almost twice as fast as that obtained in the recent literature. The suggested D-SOM architecture is also validated through simulation on variable-sized SOM networks applied to color vector quantization. [ABSTRACT FROM AUTHOR]

Network flow classification is a key function in high-speed switches and routers. It directly determines the performance of network devices. With the development of the Internet and various kinds of applications, the flow classification needs to support multi-dimensional fields, large rule sets, and sustain a high throughput. Software-based classification cannot meet the performance requirement as high as 100 Gbps. FPGA-based flow classification methods can achieve a very high throughput. However, the range matching is still challenging. For this, this paper proposes a range supported bit vector (RSBV) method. First, the characteristic of range matching is analyzed, then the rules are pre-encoded and stored in memory. Second, the fields of an input packet header are used as addresses to read the memory, and the result of range matching is derived through pipelined Boolean operations. On this basis, bit vector for any types of fields (AFBV) is further proposed, which supports the flow classification for multi-dimensional fields efficiently, including exact matching, longest prefix matching, range matching, and arbitrary wildcard matching. The proposed methods are implemented in FPGA platform. Through a two-dimensional pipeline architecture, the AFBV can operate at a high clock frequency and can achieve a processing speed of more than 100 Gbps. Simulation results show that for a rule set of 512-bit width and 1 k rules, the AFBV can achieve a throughput of 520 million packets per second (MPPS). The performance is improved by 44% compared with FSBV and 30% compared with Stride BV. The power consumption is reduced by about 43% compared with TCAM solution. [ABSTRACT FROM AUTHOR]

Detecting epileptic seizure is a very time consuming and costly task if a support vector machine (SVM) hardware processor is used. In this paper, an automated seizure detection scheme is developed by combining discrete wavelet transform (DWT), sample entropy (SampEn) and a novel classification algorithm based on each wavelet coefficient and voting strategy. In order to save circuit area, a Daubechies order 4 (db4) filter of lattice structure is introduced in DWT, only half elements of the symmetric distance matrix in the SampEn are stored and module reusing strategy is used. To speed up the detection, intermediate results are reused by reasonably organizing the SampEn calculation procedures. The seizure detection scheme is implemented in a field-programmable gate array (FPGA) and its classification performance is tested with publicly available epilepsy dataset. [ABSTRACT FROM AUTHOR]

This paper describes the architecture design of novel massively parallel self-organizing map (SOM) neural networks. The proposed architecture, referred to as the planar SOM (PSOM), is described as a soft IP core synthesized in VHDL. The SOM neural network's size and the input data vectors' dimension are adjustable parameters. In this work, several SOM architectures are synthesized and their performance is evaluated for Xilinx Virtex-7 FPGAs. The presented hardware architecture allows online learning and can be easily adapted to a large variety of SOM topologies without a considerable design effort. A 1 6 × 1 6 SOM hardware is validated through the FPGA implementation and its performances with an estimated working frequency of 297 MHz for a 23-element input vector will reach 21,970 MCUPS in the learning phase and 35,902 MCPS in the recall one. [ABSTRACT FROM AUTHOR]

A factor graph (FG) can be considered as a unified model combining a Bayesian network (BN) and a Markov random field (MRF). The inference mechanism of a FG can be used to perform reasoning under incompleteness and uncertainty, which is a challenging task in many intelligent systems and robotics. Unfortunately, a complete inference mechanism requires intense computations that introduces a long delay for the reasoning process to complete. Furthermore, in an energy-constrained system such as a mobile robot, it is required to have a very efficient inference process. In this paper, we present an embedded FG inference engine that employs a neural-inspired discretization mechanism. The engine runs on a system-on-chip (SoC) and is accelerated by its FPGA. We optimized our design to balance the trade-off between speed and hardware resource utilization. In our fully-optimized design, it can accelerate the inference process eight times faster than the normal execution, which is twice the speed-up gain achieved by a parallelized FG running on a PC. The experiments demonstrate that our design can be extended into an efficient reconfigurable computing machine. [ABSTRACT FROM AUTHOR]

In a typical smart home scenario, various household appliances of a residential user such as washing machine and plug-in hybrid electric vehicle (PHEV) are connected via a home area network. Household appliances can be automatically scheduled by a central controller for satisfying the timing and energy constraints. It enables the reduction of monetary cost of electricity consumption and the peak energy load of the home system. On the other hand, the prevailing household appliances usually offer multiple discrete power levels. However, the existing smart home scheduling controllers can only handle the continuous power levels, while makes them unsuitable for prevailing household appliances. In this paper, a dynamic programming-based scheduling technique is proposed and implemented on FPGA to schedule household appliances with discrete power levels. It features a solution pruning technique, which can largely improve the time complexity. A case study which constitutes ten household appliances is performed. The experimental results demonstrate that our technique can reduce the monetary cost by 39.3% on weekday and 27.2% on weekend, respectively, comparing to the traditional scheduling. For energy consumption balancing, it shows that the peak to average ratio (PAR) of the energy consumption is reduced by 43.6% on weekday and 24.0% on weekend, respectively. [ABSTRACT FROM AUTHOR]

The process to locate objects in an image passes through different phases. At the forefront of these phases, and most importantly, is the edge detection. If edges in an image are identified accurately, all of the objects will be located correctly for further processing phases. Noisy images contain high-frequency contents which might be interfered with image edges that makes edge detection more difficult. In this paper, a software comparative analysis of the performance of three different edge detectors, namely, Roberts, Prewitt and Sobel, is presented. The comparative analysis is performed to check the performance robustness of the edge detectors when noise level fluctuates in the image. In addition, an embedded hardware (HW) system is developed to implement the three detectors on the Zedboard FPGA prototyping board. The purpose of this implementation is to have an embedded system for on-the-move applications where portability is desired. To exploit the new features of the Xilinx Zynq-7000 series, we partition the implementation into (1) hardware part (running on logic gates of FPGA) and (2) software (SW) part (running on ARM processor of FPGA). This heterogeneous HW/SW implementation allows for high accurate results with high speed and efficient area. Furthermore, a hardware comparative analysis of the speed and area of the detectors is presented. The evaluation is performed by using different images (with their ground truths) downloaded from the BSDS500 dataset. The tools used for FPGA implementation are MATLAB and Microsoft Visual Studio (as software tools), Vivado High-level synthesis (HLS) and Software Development Kit (SDK) (as hardware tools). The experimental results show that the Roberts detector achieves better edge detection when the noise level is higher than 40%. It is also faster and requires less capacity of logic gates among the other detectors employed in this study. [ABSTRACT FROM AUTHOR]

Field programmable gate arrays (FPGAs) have become very widely used devices in space applications, and their runtime reconfigurable architecture allows for the area and power acceleration for complex applications. However, FPGAs are increasingly susceptible to aging effects and failures due to harsh space environments and long operation cycles, which reduce the reliability and lifetime of such devices. Although offline aging-aware layout-based methods are effective in aging mitigation, existing studies ignore the fault tolerance needs of the task and the layout strategy will completely fail after a hard failure occurs. This paper presents a reliability framework AM&FT for SRAM-based FPGAs in space applications to support on-chip aging mitigation and fault tolerance. We use an Integer Linear Programming (ILP) model to solve mapping relationships between tasks and reconfigurable blocks (Rbs) in the offline phase to achieve the aging and reliability-aware layout strategy. Second, the ILP model is incorporated into the Design Space Exploration (DSE) to generate a set of layout strategies to tolerate hard faults. Moreover, the state model is used for runtime fault management to handle the impact of different types of faults on the device. Experimental results demonstrate that our framework achieves FPGA on-chip aging mitigation and fault tolerance. Compared with the existing methods, AM&FT can guarantee the fault tolerance requirements of tasks and give priority to guarantee the Quality of Service (QoS) of critical tasks under the condition of hard faults accumulation. In addition, our framework delivers up to 6. 5 × higher mean time to failure (MTTF) than the baseline. [ABSTRACT FROM AUTHOR]

This paper introduces a charge-controlled memristor based on the classical Chuas circuit. It also designs a novel four-dimensional chaotic system and investigates its complex dynamics, including phase portrait, Lyapunov exponent spectrum, bifurcation diagram, equilibrium point, dissipation and stability. The system appears as single-wing, double-wings chaotic attractors and the Lyapunov exponent spectrum of the system is symmetric with respect to the initial value. In addition, symmetric and asymmetric coexisting attractors are generated by changing the initial value and parameters. The findings indicate that the circuit system is equipped with excellent multi-stability. Finally, the circuit is implemented in Field Programmable Gate Array (FPGA) and analog circuits. [ABSTRACT FROM AUTHOR]

In the literature, the parabolic function of the Izhikevich Neuron Model (IzNM) is transformed to the Piecewise Linear (PWL) functions in order to make digital hardware implementations easier. The coefficients in this PWL functions are identified by utilizing the error-prone classical step size method. In this paper, it is aimed to determine the coefficients of the PWL functions in the modified IzNM by using the stochastic optimization methods. In order to obtain more accurate results, Genetic Algorithm and Artificial Bee Colony Algorithm (GA and ABC) are used as alternative estimation methods, and amplitude and phase errors between the original and the modified IzNMs are specified with a newly introduced error minimization algorithm, which is based on the exponential forms of the complex numbers. In accordance with this purpose, GA and ABC algorithms are run 30 times for each of the 20 behaviors of a neuron. The statistical results of these runs are given in the tables in order to compare the performance of three parameter-search methods and especially to see the effectiveness of the newly introduced error minimization algorithm. Additionally, two basic dynamical neuronal behaviors of the original and the modified IzNMs are realized with a digital programmable device, namely FPGA, by using new coefficients identified by GA and ABC algorithms. Thus, the efficiency of the GA and ABC algorithm for determining the nonlinear function parameters of the modified IzNM are also verified experimentally. [ABSTRACT FROM AUTHOR]