FPGA Implementation of Linear Congruential Generator Based on Block Reduction Technique.

This paper exposes circuit design of linear congruential generator (LCG) and implementation in FPGA based on block reduction technique. The circuit is derived from LCG algorithm proposed by Lehmer. Block reduction technique has been used to simplify the circuit. Several net connections among the blocks of the circuit are ignored or disconnected and the multiplier is replaced by a shifter. Simulations of both behavior and timing have been done and the results confirm its algorithm. The Cyclone II EP2C8Q208C8N and Cyclone IV E EP4CE115F29C7N of Altera have been chosen to extract comparison data of speed and occupied area. Further comparison of shift technique and the wordlengths reduction technique has been made. In general, the proposed design is far simpler than the previous published LCG circuit. [ABSTRACT FROM AUTHOR]