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This study investigates the effects of negative bias temperature (NBT) stress and irradiation on the threshold voltage (VT) of p-channel VDMOS transistors, focusing on degradation, recovery after each type of stress, and operational behavior under varying conditions. Shifts in VT (ΔVT) were analyzed under different stress orders, showing distinct influence mechanisms, including defects creation and their removal and electrochemical reactions. Recovery data after each type of stress indicated ongoing electrochemical processes, influencing subsequent stress responses. Although the ΔVT is not particularly pronounced during the recovery after irradiation, changes in subthreshold characteristics indicate the changes in defect densities that affect the behavior of the components during further application. Additionally, the findings show that the ΔVT during the NBT stress after irradiation (up to certain doses and conditions) remains relatively stable, but this is the result of a balance of competing mechanisms. A subthreshold characteristic analysis provided a further insight into the degradation dynamics. A particular attention was paid to analyzing ΔVT with a focus on predicting the lifetime. In practical applications, especially under pulsed operation, prior stresses altered the device’s thermal and electrical performance. It was shown that self-heating effects were more pronounced in pre-stressed components, increasing the power dissipation and thermal instability. These insights additionally highlight the importance of understanding stress-induced degradation and recovery mechanisms for optimizing VDMOS transistor reliability in advanced electronic systems.

This paper presents an extensive comparative analysis of the experimental results of chemical stabilisation of clayey soil in laboratory conditions by comparing the effects of adding conventional stabilisers (lime, cement binder), stabilisers that can be considered as waste material (fly ash, rock flour), as well as alternative chloride-based materials (ferric chloride, calcium chloride, potassium chloride) on the geomechanical properties of the soil. With the aim of determining the stabiliser optimal content in the mixture with the soil, in the first part of the research, the effects of stabilisation of clayey soil of medium plasticity using the considered stabilisers with different percentage share on the change in uniaxial compressive strength (UCS) and pH value of the soil at different time intervals after the treatment were analysed. In the second part of the research, additional tests were conducted on soil samples with optimal content for each of the considered stabilisers by monitoring changes in the physical and mechanical properties of the soil. These include Atterberg’s limits (liquid limit and plasticity limit), modulus of compressibility in the oedometer, California bearing ratio (CBR), and swelling potential at different time intervals after the chemical treatment to determine the durability of stabilisation effects. The results of the conducted research reveal that each of the conventional, waste, and alternative materials considered as chemical stabilisers contributes to the improvement of the geomechanical properties of the clayey soil, primarily in terms of increasing the bearing capacity and reducing the swelling of the treated soil.

This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors.

This study investigates the effects of negative bias temperature (NBT) stress and irradiation on the threshold voltage (VT) of p-channel VDMOS transistors, focusing on degradation, recovery after each type of stress, and operational behavior under varying conditions. Shifts in VT (ΔVT) were analyzed under different stress orders, showing distinct influence mechanisms, including defects creation and their removal and electrochemical reactions. Recovery data after each type of stress indicated ongoing electrochemical processes, influencing subsequent stress responses. Although the ΔVT is not particularly pronounced during the recovery after irradiation, changes in subthreshold characteristics indicate the changes in defect densities that affect the behavior of the components during further application. Additionally, the findings show that the ΔVT during the NBT stress after irradiation (up to certain doses and conditions) remains relatively stable, but this is the result of a balance of competing mechanisms. A subthreshold characteristic analysis provided a further insight into the degradation dynamics. A particular attention was paid to analyzing ΔVT with a focus on predicting the lifetime. In practical applications, especially under pulsed operation, prior stresses altered the device's thermal and electrical performance. It was shown that self-heating effects were more pronounced in pre-stressed components, increasing the power dissipation and thermal instability. These insights additionally highlight the importance of understanding stress-induced degradation and recovery mechanisms for optimizing VDMOS transistor reliability in advanced electronic systems. [ABSTRACT FROM AUTHOR]

This paper presents an extensive comparative analysis of the experimental results of chemical stabilisation of clayey soil in laboratory conditions by comparing the effects of adding conventional stabilisers (lime, cement binder), stabilisers that can be considered as waste material (fly ash, rock flour), as well as alternative chloride-based materials (ferric chloride, calcium chloride, potassium chloride) on the geomechanical properties of the soil. With the aim of determining the stabiliser optimal content in the mixture with the soil, in the first part of the research, the effects of stabilisation of clayey soil of medium plasticity using the considered stabilisers with different percentage share on the change in uniaxial compressive strength (UCS) and pH value of the soil at different time intervals after the treatment were analysed. In the second part of the research, additional tests were conducted on soil samples with optimal content for each of the considered stabilisers by monitoring changes in the physical and mechanical properties of the soil. These include Atterberg's limits (liquid limit and plasticity limit), modulus of compressibility in the oedometer, California bearing ratio (CBR), and swelling potential at different time intervals after the chemical treatment to determine the durability of stabilisation effects. The results of the conducted research reveal that each of the conventional, waste, and alternative materials considered as chemical stabilisers contributes to the improvement of the geomechanical properties of the clayey soil, primarily in terms of increasing the bearing capacity and reducing the swelling of the treated soil. [ABSTRACT FROM AUTHOR]

The mechanisms responsible for the effects of consecutive irradiation and negative bias temperature (NBT) stress in p-channel power vertical double-diffused MOS (VDMOS) transistors are presented in this paper. The investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation. [ABSTRACT FROM AUTHOR]

This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors. [ABSTRACT FROM AUTHOR]

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits. [ABSTRACT FROM AUTHOR]

In this study, which is aimed at assessing a possible relationship between the recoverable and permanent components of negative bias temperature instability (NBTI) degradation, we investigate NBTI in commercial IRF9520 p-channel VDMOSFETs (vertical double diffused MOSFETs) stressed under particular pulsed bias conditions by varying the pulse on-time while keeping the off-time constant and vice versa. The stress-induced threshold voltage shifts are found to be practically independent of duty cycle when the pulse on-time is kept short or the off-time is kept long, and are found to start increasing with duty cycle only when the on-time is increased or the off-time is decreased beyond specific values. These results, which are discussed in terms of dynamic recovery effects and the mechanisms leading to NBTI degradation, point to the existence of an important correlation between the recoverable and permanent components of degradation. [ABSTRACT FROM AUTHOR]

The effect of annealing on the recovery of electrically stressed power vertical double-diffused metal oxide semiconductor (VDMOS) transistors has been investigated. Behaviors of device threshold voltage and channel carrier mobility have been analyzed in terms of underlying changes in the densities of gate oxide charges and interface traps. The mechanisms responsible for the above-mentioned changes during the recovery of stressed devices have been analyzed as well. The annealing resulted in achieving stable threshold voltage and mobility, but did not ensure full recovery, as part of the stress-induced degradation remained permanent and could not be annealed. Namely, the annealing was found to enhance the neutralization of stress-induced oxide charges and the passivation of stress-induced interface traps, while the stability upon its completion resulted from the significantly decreased density of gate oxide charges and the possible balance between the processes of trap passivation and creation at the SiO2–Si interface. [ABSTRACT FROM AUTHOR]

In this paper, the effects of successively applied static/pulsed negative bias temperature (NBT) stress and irradiation on commercial p-channel power vertical double-diffused metal-oxide semiconductor (VDMOS) transistors are investigated. To further illustrate the impacts of these stresses on the power devices, the relative contributions of gate oxide charge ( N ot ) and interface traps ( N it ) to threshold voltage shifts are shown and studied. It was shown that when irradiation without gate voltage is used, the duration of the pre-irradiation static NBT stress has a slightly larger effect on the radiation response of power VDMOS transistors. Regarding the fact that the investigated components are more likely to function in the dynamic mode than the static mode in practice, additional analysis was focused on the results obtained during the pulsed NBT stress after irradiation. For the components subjected to the pulsed NBT stress after the irradiation, the effects of N ot neutralization and N it passivation (usually related to annealing) are more enhanced than the components subjected to the static NBT stress, because only a high temperature is applied during the pulse-off state. It was observed that in devices previously irradiated with gate voltage applied, the decrease of threshold voltage shift is significantly greater during the pulsed NBT stress than during the static NBT stress. [ABSTRACT FROM AUTHOR]

High-k dielectric stacks are regarded as a promising information storage media in the Charge Trapping Non-Volatile Memories, which are the most viable alternative to the standard floating gate memory technology. The implementation of high-k materials in real devices requires (among the other investigations) estimation of their radiation hardness. Here we report the effect of gamma radiation (60Co source, doses of 10 and 10 kGy) on dielectric properties, memory windows, leakage currents and retention characteristics of nanolaminated HfO2/Al2O3 stacks obtained by atomic layer deposition and its relationship with post-deposition annealing in oxygen and nitrogen ambient. The results reveal that depending on the dose, either increase or reduction of all kinds of electrically active defects (i.e., initial oxide charge, fast and slow interface states) can be observed. Radiation generates oxide charges with a different sign in O2 and N2 annealed stacks. The results clearly demonstrate a substantial increase in memory windows of the as-grown and oxygen treated stacks resulting from enhancement of the electron trapping. The leakage currents and the retention times of O2 annealed stacks are not deteriorated by irradiation, hence these stacks have high radiation tolerance. [ABSTRACT FROM AUTHOR]