78 results on '"van Meer H"'
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2. Yield and growth features of Panicum maximum (Jacq.) var Trichoglume cv Petrie (Green Panic) under woody cover, Chaco region, Argentina
3. De zorg voor ouderen in de huisartsenpraktijk
4. Low-frequency gate current noise of InP based HEMTs
5. Comprehensive study of Ga activation in Si, SiGe and Ge with 5 × 10−10 Ω·cm2 contact resistivity achieved on Ga doped Ge using nanosecond laser activation
6. Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures
7. Sub-10−9 Ω·cm2 contact resistivity on p-SiGe achieved by Ga doping and nanosecond laser activation
8. Revitalisation of the Ruins of the Abbey-Tower at Sint-Truiden
9. Advanced TCAD for predictive FinFETs Vth mismatch using full 3D process/device simulation
10. USJ engineering impacts on FinFETs and RDF investigation using full 3D process/device simulation
11. Yield and growth features of Panicum maximum (Jacq.) var Trichoglume cv Petrie (Green Panic) under woody cover, Chaco region, Argentina
12. Strain mapping of Si devices with stress memorization processing
13. Influence of device engineering on the analog and RF performances of SOI MOSFETs
14. Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
15. High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography
16. Low-frequency noise overshoot in ultrathin gate oxide silicon-on-insulator metal–oxide–semiconductor field-effect transistors
17. Influence of device engineering on the analog and RF performances of SOI MOSFETs
18. CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design.
19. Low temperature operation of 0.13 μm Partially-Depleted SOI nMOSFETs with floating body
20. On the Origin of the 1/f
21. Low temperature operation of 0.13 /spl mu/m partially-depleted SOI nMOSFETs with floating body
22. The spacer/replacer concept: a viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS
23. A 2-D analytical threshold voltage model for fully-depleted SOI MOSFETs with Halos or pockets
24. Low temperature operation of 0.13 μm partially-depleted SOI nMOSFETs with floating body.
25. Raised source/drains with disposable spacers for sub 100 nm CMOS technologies.
26. New Shift-&-Ratio Leff extraction algorithm for Fully-Depleted SOI CMOS transistors.
27. Limitations of shift-and-ratio based L/sub eff/ extraction techniques for MOS transistors with halo or pocket implants
28. New Shift-&-Ratio Leff extraction algorithm for Fully-Depleted SOI CMOS transistors
29. Power Amplifier Linearisation Using a Straightforward Technology Independent Method Based on Vectorial Large-Signal Measurements
30. IM3 Suppression Using a Technology Independent Method Based on Vectorial Large-Signal Measurements
31. Effect of Schottky barrier alteration on the low-frequency noise of InP-based HEMTs
32. Improved HEMT model for low phase-noise InP-based MMIC oscillators
33. Low-frequency drain current noise behavior of InP based MODFET's in the linear and saturation regime
34. Strain mapping of Si devices with stress memorization processing.
35. Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides.
36. On the difference in threshold voltage dependence on channel length for boron and indium channel nMOS transistors.
37. High performance raised Gate/Source/Drain transistors for sub-0.15 um CMOS technologies.
38. Versatile RF Measurement System to Thoroughly Evaluate the Non-linear Behaviour of SOI versus Bulk CMOS Technologies.
39. Investigation of the Threshold Voltage Difference between Partially-Depleted SOI and bulk CMOS transistors.
40. Power Amplifier Linearisation Using a Straightforward Technology Independent Method Based on Vectorial Large-Signal Measurements.
41. Empirical Modeling of the Low-Frequency Noise Behaviour of InP-Based HEMTs.
42. Optimization of nMOS high-frequency transistor characteristics for application in MMICs.
43. Scaleable non-linear and bias-dependent low-frequency noise model for improved InP HEMT based MMIC oscillator design.
44. Limitations of shift-and-ratio based Leff extraction techniques for MOS transistors with halo or pocket implants.
45. Raised source/drains with disposable spacers for sub 100 nm CMOS technologies
46. 70 nm fully-depleted SOI CMOS using a new fabrication scheme: the spacer/replacer scheme
47. Optimization of nMOS high-frequency transistor characteristics for application in MMICs
48. Scaleable non-linear and bias-dependent low-frequency noise model for improved InP HEMT based MMIC oscillator design
49. Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications
50. Process and local layout effect interaction on a high performance planar 20nm CMOS.
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