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This paper comprehensively investigates how the control voltage settles in Voltage Controlled Oscillators (VCO) by considering all non-ideal factors in phase lock loop circuits. Also, the different structures of the phase detector and their effect on the locking speed of the phase-locking loop circuit, the control voltage ripple and the locking frequency range will be compared. Three phase locked loop circuits with XOR detector, RS-FF detector and dynamic phase detector were investigated in this paper. The simulations were performed on 0.18 µm-CMOS technology with a 1.8V power supply. The simulation results show that the operating range of the phase-locked loop circuit including dynamic phase detector with charge pump circuit has less ripple for the non-ideal effects compared to the phase-locked loop circuit including XOR phase detector and the phase-locked loop circuit including RS-FF phase detector. of the phase-locked loop circuit including dynamic phase detector is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, frequency range is 0.284-3.33GHz, power consumption is 2.86mW and phase noise is -118.8dBc/Hz.

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit ( F o M j i t t e r ) ~−236 dB. [ABSTRACT FROM AUTHOR]

An autocorrelation technique, which involves the correlation of a signal with its delayed version, could be used to demodulate the FM (Frequency Modulation) and PM (Phase Modulation) signals in a simple cost-effective manner. In this paper, an attempt has been made to understand the working principle of the autocorrelation technique for FM and PM demodulations. From the working principle, several design equations have been derived and these equations have been verified with the experimental results obtained from a 70 MHz autocorrelation-type FM receiver designed and developed indigenously. The demodulation of FM signal directly at RF (radio frequency) level has also been demonstrated using an autocorrelation-type C-band FM receiver at 4180 MHz. [ABSTRACT FROM AUTHOR]

The effectiveness of the use of optical calibration in high-precision phase laser rangefinders has been evaluated. In order to ensure the specified accuracy of distance determination in order to establish the optimal frequency of distance measurement modes and optical calibration, an appropriate formula is recommended for estimating the switching frequency of signals at the input of the range finder measuring channel. It has been established that even when using optical calibration, the accuracy of distance measurement is affected by the error of the phase detector, which is part of the rangefinder. To minimize the influence of this error, a new method for the direct measurement of the phase shift in a range finder is proposed, as well as the use of a compensation method for measuring the phase shift. The corresponding block diagrams of rangefinders are considered, in which the proposed methods for measuring phase landslides are implemented, and analytical modeling of the processes that transform them is carried out. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Data Acquisition & Processing / Shu Ju Cai Ji Yu Chu Li is the property of Editorial Department of Journal of Nanjing University of Aeronautics & Astronautics and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the phase detection gain by ~100× compared to the Phase-Frequency Detectors (PFDs) used in conventional PLLs. Using this high detection gain, the noise contribution of the PFD and Charge Pump (CP), reference clock, and dividers on the PLL output is minimized, enabling low output jitter at low power, even when using low-frequency reference clocks. To provide a sufficient frequency locking range, an auxiliary frequency-locked loop (AFLL) is embedded within the INPLL. An integrated Lock Detector (LD) helps detect the INPLL locked state and disables the AFLL to save on power consumption and minimize its impact on the INPLL jitter. The proposed INPLL layout measures 700 µm × 350 µm, consumes 350 µW, and exhibits an integrated phase noise (IPN) of −37 dBc (from 10 kHz to 10 MHz), equivalent to 2.9 ps rms jitter, while keeping the spur level 64 dBc lower, resulting in jitter figure of Merit (FoMjitter) ~−236 dB.

Phase measurement system (PMS)s are playing the major role in real time communication applications. The digital PMS measures the exact value of phase compare to the analog PMS devices. However, the conventional digital PMSs failed to measure the accurate phase value and consumed the higher hardware resources like area, delay and power. Therefore, this work is focused on implementation of Hybrid Digital-PMS (HD-PMS) module for efficient phase value estimation. Initially, Hybrid Dual Data-First-In-First-Out-Flip Flop (D-FIFO-FF) synchronizer is introduced to improve the synthesis the data inputs, which synchronizes the data inputs with variable clock frequencies. Then, Phase Detector (PD) is used to identify the phase difference between data input1, data input 2. The PD is developed using XOR logical operation, which is high speed and area efficient. Then, data input1, data input 2 frequencies are changed by modifying the duty cycles through Pulse Width Modulation (PWM) controller. Here, PWM is used to change the duty cycles of data inputs using phase difference generated from PD. Finally, Phase Value Computation (PVC) module is introduced to estimate the digital phase levels using arithmetical operations using duty cycle levels. The simulations conducted using XILINX-ISE 14.7 reveled that, the proposed HD-PMS consumed lower hardware resources like look-up-tables (LUT), LUT-FFs, slice registers, path delays and power consumptions as compared to other PMS approaches.

A 16-Gb/s edge-based sub-baud-rate digital clock and data recovery (CDR) circuit is presented. By using the proposed edge-based sub-baud-rate technique and a passive high-pass filter, the complementary clocks are used to save the power. To improve the jitter tolerance, the intrinsic delay of the high-pass filter is compensated by using compensation delay cells. The proposed sub-baud-rate CDR circuit is fabricated in 40-nm CMOS technology. Its active area is 0.0376mm2 and the power is 23.2mW for a supply of 1.2V at the data rate of 16 Gb/s. The calculated energy efficiency of this CDR circuit is 1.45 pJ/b. [ABSTRACT FROM AUTHOR]

Recently, a Rydberg atom-based mixer was developed to measure the phase of a radio frequency (RF) field. The phase of the signal RF (SIG RF) field is down-converted directly to the phase of a beat signal created by the presence of a local RF (LO RF) field. In this study, we propose that the Rydberg atom-based mixer can be converted to an all-optical phase detector by amplitude modulation (AM) of the LO RF field; that is, the phase of the SIG RF field is related to both the amplitude and phase of the beat signal. When the AM frequency of the LO RF field is the same as the frequency of the beat signal, the beat signal will further interfere with the AM of the LO RF field inside the atom, and then the amplitude of the beat signal is related to the phase of the SIG RF field. The amplitude of the beat signal and the phase of the SIG RF field show a linear relationship within the range of 0 to π /2 when the phase of the AM is set with a difference π /4 from the phase of the LO RF field. The minimum phase resolution can be as small as 0.6° by optimizing the experimental conditions according to a simple theoretical model. This study will expand and contribute to the development of RF measurement devices based on Rydberg atoms. [ABSTRACT FROM AUTHOR]

The aim of this study was to obtain accurate angular positions and velocities from resolver signals; resolver-to-digital conversion (RDC) often adopts a phase-locked loop (PLL) as a demodulation algorithm. However, resolver signals often come with quadrature errors and harmonics, which lead to a severe reduction in PLL accuracy. The conventional PLL does not consider the impact of the quadrature error, and the bandwidth of the PLL is much larger than the fundamental frequency of resolver signals for pursuing a low dynamic error. These reasons render the retention of resolver harmonics in the demodulation results. In this paper, a disturbance-compensated PLL (DC-PLL) is proposed, which consists of a phase detector for suppressing quadrature error and harmonics (SQEH-PD) and a second-order observer. Firstly, since the quadrature error does not change with the angle velocity, the pre-estimated quadrature error is used in the SQEH-PD to compensate for the quadrature error in resolver signals. Secondly, although the frequency of the harmonics changes with the velocity, the amplitudes of the harmonics do not change. Therefore, the pre-estimated amplitudes of harmonics and estimated angular position are used in the SQEH-PD to compensate for the harmonics in resolver signals. Thirdly, a second-order observer is designed to estimate the angular position and velocity by regulating the phase detector error. Compared with the conventional PLL, the proposed DC-PLL has a stronger anti-disturbance ability against the quadrature error and harmonics by configurating the phase detector error and the estimated position error, which have a linear relation. Simulation and experimental results prove the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures tVCDL more accurately; thus, it can always generate the correct up/down (UP/DN) pulses. The proposed technique prevents becoming stuck in the fastest operation, in which UP pulses continue to appear even when tVCDL < tREF, where tREF is the reference time, which is an input of the DLL. In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL > tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation. The proposed phase detection scheme was verified under various conditions, including process corners, temperature variations, and abrupt changes in tREF. The proposed 1.2 V, 20~200 MHz DLL with the PD-MDV was designed using the 65 nm process, with a power consumption of 0.4 mW at 200 MHz. [ABSTRACT FROM AUTHOR]

In this paper, we propose a low-jitter reference-less clock and data recovery (CDR) circuit with a speed range of 9.8–12.5 Gb/s. The proposed CDR uses a multi-stage half-rate bang-bang phase detector (ML-HR-BBPD) to maximize the quantization of the phase difference. In addition, a unit interval adjuster (UIA) is added to the CDR circuit. So that the circuit can minimize the phase detector's phase error before the output clock frequency is locked. Finally, the loop filter (LF) is improved to realize the coarse and fine adjustment of the phase error over a wide range of phase differences. The CDR circuit's total power consumption is reduced by using a half-rate phase detector. The CDR circuit was fabricated in TSMC 40 nm CMOS process. The measured results are obtained in the proposed CDR circuit at a data rate of 12.5 Gb/s. With a pseudo-random bit sequence (PRBS) of 2 3 1 − 1 , the measured result shows that the bit error rate (BER) is < 1 0 − 1 2 , and the root mean square jitter recovered in the output is 0.302 p s rms . The circuit's jitter tolerance (JTOL) is 0.46 UIpp, and its total power consumption is 74.8 mW with a 5.98 pJ/bit energy efficiency. [ABSTRACT FROM AUTHOR]

This paper proposes a nonlinear MIMO scheme named as halved-phase only MIMO (HPO-MIMO), whose base station (BS) is equipped with multiple HPO radio-frequency (RF) chains extracting $\pi $ -periodic phase measurements from RF signals directly by phase detectors, and single classical RF chain sampling the combination of all the RF signals from HPO-RF chains. Compared to MIMO, HPO-RF receivers are simplified significantly, and have much lower power consumption and fabrication cost. Two types of channel estimators and multiuser detectors are developed for HPO-MIMO from the perspectives of numerical optimization and Bayesian inference. Firstly, because $\pi $ -periodic phases provide tan-relationships between the Inphase (I) and Quadrature (Q) components, the channel estimation (CE) and multiuser detection (MUD) problems are resolved by minimizing $l_{2}$ -norm cost functions with unit-norm constraint on the recovered vector. Their solutions are obtained by deriving the eigenvector corresponding to the minimum eigenvalue through shifted power method (SPW). Secondly, the CE and MUD problems are categorized as generalized linear mixing problems under (un-)quantized $\pi $ -periodic phase measurements, and then handled by generalized approximate message passing (GAMP), where closed-form solutions for mean-and-variance messages involving $\pi $ -periodic phases are derived. Finally, magnitude and $\pi $ -phase ambiguities persisting in signal recovery are removed based on the complex-valued full measurements from the single classical RF chain. Simulation results show that GAMP-type algorithms outperform SPW-type ones, and handle nonlinear phase quantization losses. 16-sector quantized HPO-MIMO could work as well as its un-quantized correspondence. HPO-MIMO reserves the MIMO advantages, but is more energy-efficient than the latter. [ABSTRACT FROM AUTHOR]

A new techniqueto detect the phase difference of two high-frequency RF signals is presented. It is based on downconverting the two high-frequency input RF signals into two low-frequency signals via Serrodyne optical frequency translation and optical frequency downconversion. The phase difference of the two low-frequency downconverted signals is the same as the two high-frequency input RF signal phase difference. Hence a low-cost low-frequency electronic phase detector can be used after photodetection to generate a DC voltage with a value depending on the two input RF signal phase difference. The technique is simple, novel, and innovative. It utilises the advantage of ultra-wide operating frequency range in microwave photonics and the input RF power independent phase detection characteristic in electronic phase detectors. It overcomes the limitations of the input RF signal power and frequency need to be known prior to phase detection in the reported microwave photonic based phase detectors. Experimental results demonstrate 0°-180° RF signal phase difference detection with 1° resolution and less than ±2.6° errors for different RF signal frequencies (10 GHz, 14 GHz and 18 GHz) and different RF modulation indexes (0.2, 0.4 and 0.7). Results also demonstrate the proposed phase detector has excellentrepeatability. [ABSTRACT FROM AUTHOR]

Analog coherent receiver (ACR) is an attractive alternative to ADC+DSP based coherent receiver for reducing the complexity and power consumption in near-future high-capacity coherent data center interconnects (DCIs). Carrier phase recovery and compensation (CPRC), which is one of the major operations in the coherent DCIs, is essential to compensate for the phase and frequency offsets between the lasers and phase noise of lasers. In this work, we present a CPRC architecture for ACR based DCIs. The proposed CPRC approach comprises a dual loop architecture for frequency and phase offset corrections. Detailed design, analysis, effects of non-idealities, and simulation results of the dual loop CPRC are presented. For our analyses, circuit-realizable parameters have been used and the CPRC can be implemented in advanced CMOS/FinFET/SiGe technology nodes. The presented analog CPRC technique, along with lowering the power consumption, reduces the complexity in 200 Gbps/ $\lambda$ coherent DCIs. [ABSTRACT FROM AUTHOR]

Research in the field of monitoring and registration of geophysical disturbances being a complex scientific and technical problem of great importance has been carried out. Disturbances of fluctuating media have a significant impact on the functioning of technical systems for control, safety, navigation, communications, etc. For this reason, the development of methods and tools for monitoring and registration of geophysical disturbances is an urgent task in many fields of science and technology. The article discusses a method for registering geophysical disturbances in fluctuating media using a spatially separated radio-acoustic generator. The method for registering geophysical disturbances is based on comparing the phase of an acoustic signal received from a fluctuating medium with the phase of a signal emitted into a controlled medium. The output signal of the phase detector is a DC voltage, described by a monotonic function of the phase difference of the input signals. A condition for self-excitation of a spatially separated radio-acoustic generator, which is determined by the general solution of the transient component of a second-order differential equation, is formulated. Block diagrams of the technical implementation of the method are presented. The principle of disturbances registration is based on the comparison of the phases of signals received and emitted into the controlled medium. Based on the results of the experimental study, a phase diagram of the output signal of the phase detector is presented as a response to the throwing of objects of various sizes into the area of acoustic beam propagation. The results of the study are relevant for the following areas of application: sounding of continental sea and ocean shelves, monitoring of vortex and turbulent disturbances in the airspace of airport runways, control of sea waves and underwater currents in the waters of seaports, detection of foreign objects in protected areas. [ABSTRACT FROM AUTHOR]

A new topology that generates a DC voltage whose value is depending on the phase difference of two input RF signals is presented. It is implemented by the mixer concept. With the use of microwave photonics, the mixer-based phase detector can be operated over a very wide frequency range. It also has the advantages of high phase detection resolution, small phase detection error, and small DC offset and phase offset. The phase detector can be constructed using off-the-shelf components including a single integrated optical modulator and a low-speed balanced detector. Measured results on the phase detector demonstrate a 0° to 180° RF signal phase difference detection range for 3.5 GHz to 18 GHz input RF signal frequencies, less than ±3° phase detection error and 2° phase detection resolution.

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) $0.18~\mu \text{m}$ 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

In this brief, a four-phase delay-locked loop (DLL) with low phase error, low power consumption, and small area is presented for time-to-digital conversion application. A highly matched single-ended differential single-ended voltage-controlled delay line is proposed to improve the phase uniformity of these multiple output signals. A digital auxiliary duty-cycle corrector is designed to adjust the width of the output signal to reduce the pulse width error and to make the duty cycle of each output signal approximately 50%. Designed using 0.18- $\mu \text{m}$ CMOS technology, this DLL occupies an active area of 111.32 $\mu \text{m}\,\,\times $ 82.74 $\mu \text{m}$. With a 1.8 V supply voltage and a 250 MHz operating frequency, the measured power consumption and output phase error rate of this DLL are 2.28 mW and 1.3%, respectively. [ABSTRACT FROM AUTHOR]

Active load impedance variations in a phased array transmitter cause significant power amplifier (PA) performance degradation, in terms of output power, linearity, and power-added efficiency, which are key parameters to enable high-speed data throughputs using spectrally efficient modulation schemes. The system performance can be restored by using PAs having active or passive reconfigurability with the help of antenna impedance sensors. This article presents a low-power reflection-coefficient sensor for 5G millimeter-wave phased-array applications. The complex load impedance of the PA is determined based on the complex voltage over a sensing element, which can be integrated and co-designed with the PA output matching network, with minimal loss (< 0.2 dB) and a negligible area penalty. A full-range phase detector with improved detection resolution is proposed, enabling an amplitude-insensitive phase detection. Fabricated in a 22 nm FD-SOI process, the sensor prototype occupies a silicon area of 0.024 mm2 and consumes 13.2 mW power. The sensor demonstrates a wide detection range with $\vert \Gamma \vert $ up to 0.7 (VSWR 5.67) in a load-pull test at 28 GHz. From $\Gamma $ circle of 0.2 up to 0.7, the maximum detection errors in the magnitude and phase of the $\Gamma $ are 0.14° and 40°, respectively. [ABSTRACT FROM AUTHOR]

Analog domain signal processing is an attractive approach for the reduction of power consumption in high capacity short reach coherent links. An analog domain equalizer for coherent links, as part of an all-analog solution, was first proposed and demonstrated by our group earlier. In the present work, we focus on the proof-of-the-concept demonstration of a carrier phase synchronization chip designed in a 130 nm SiGe BiCMOS technology. The chip, along with other loop components, is able to compensate for the time varying phase offsets between the modulated signal and the local oscillator (LO) in coherent homodyne links. The chip's functionality has been validated experimentally for operation at 40 Gbps, i.e., for QPSK modulation at 20 Gbaud and 16-QAM modulation at 10 Gbaud, in polarization multiplexed-carrier based self-homodyne (PMC-SH) links. Integrating such circuits in advanced technology nodes, such as the 7 nm FinFET process, can lead to low-power, low-cost, and high capacity DCI solutions for short reach applications. Additionally, the analog signal processing (ASP) based approach can reduce the latency added by the DSP based solutions. This reduction can be significant in intra-rack ($< $ 100 m), high SNR links, wherein the propagation delay and the latency added by the FEC engine are not too high. [ABSTRACT FROM AUTHOR]

This article presents a circuit for the precise vertical landing of drones based on a three phase-shifts detection of a single frequency transmitted from the landing point. The circuit can be considered as a new navigation sensor that assists in guidance corrections for landing at a specific point. The circuit has three inputs to which the signal transmitted from an oscillator located at the landing point arrives with different delays. The input signals are combined in pairs in each of the three analog phase detectors, after having passed through 3 dB at 90° hybrid couplers that guarantee a theoretical nonambiguous phase shift range of ±90°. Each output has a voltage that is proportional to the phase shift between each of the input signals, which in turn depends on the position relative to the landing point. A simple landing algorithm based on phase shift values is proposed, which could be integrated into the same flight control platform, thus avoiding the need to add additional processing components. To demonstrate the feasibility of the proposed design, a triangular phase shift detector prototype has been implemented using commercial devices. Calibration and measurements at 2.46 GHz show a dynamic range of 30 dB and a nonambiguous detection range of ±80° in the worst cases. Those specs let us track the drone during the landing maneuver in an inverted cone formed by a surface with a ±4.19 m radius at 10 m high and the landing point. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This article presents the results of the research of noiseimmunity of wireless communication systems using signals that are formed on the basis of eight-position quadrature-amplitude modulation (8-QAM) and eight-position amplitude modulation of many components (8-AMMC). The research was conducted using simulation of a wireless communication system, built using a detector, implemented on the basis of a phase locked loop. The influence of phase locked loop parameters on the detection quality of these signals in the condition of the interference in the communication channel was researched, and a comparative analysis of the noise immunity of wireless communication systems using these signals was carried out.

The aim of this study was to obtain accurate angular positions and velocities from resolver signals; resolver-to-digital conversion (RDC) often adopts a phase-locked loop (PLL) as a demodulation algorithm. However, resolver signals often come with quadrature errors and harmonics, which lead to a severe reduction in PLL accuracy. The conventional PLL does not consider the impact of the quadrature error, and the bandwidth of the PLL is much larger than the fundamental frequency of resolver signals for pursuing a low dynamic error. These reasons render the retention of resolver harmonics in the demodulation results. In this paper, a disturbance-compensated PLL (DC-PLL) is proposed, which consists of a phase detector for suppressing quadrature error and harmonics (SQEH-PD) and a second-order observer. Firstly, since the quadrature error does not change with the angle velocity, the pre-estimated quadrature error is used in the SQEH-PD to compensate for the quadrature error in resolver signals. Secondly, although the frequency of the harmonics changes with the velocity, the amplitudes of the harmonics do not change. Therefore, the pre-estimated amplitudes of harmonics and estimated angular position are used in the SQEH-PD to compensate for the harmonics in resolver signals. Thirdly, a second-order observer is designed to estimate the angular position and velocity by regulating the phase detector error. Compared with the conventional PLL, the proposed DC-PLL has a stronger anti-disturbance ability against the quadrature error and harmonics by configurating the phase detector error and the estimated position error, which have a linear relation. Simulation and experimental results prove the effectiveness of the proposed method.

The paper presents the results of simulation of a detector, implemented on the basis of a phase locked loop device (PLL), the mathematical modeling of signals with 8-QAM modulation, and investigates the influence of PLL parameters on the receiving quality of these signals with the interference in the communication channel. As a result of the study, the optimal parameters were found to provide the maximum noise-immunity for the communication system, which uses complex types of signals phase modulation. Two methods of signal detector composition were considered and compared in terms of noise-immunity. The first one is classic detector based on PLL synchronization and the second one - modified detector with specific additional filters. Modified detector was chosen for maintaining the further experiments due to its potential higher noise-immunity. The second part of the work was dedicated to the research of detection efficiency of modified detector using complex phase modulated signal 8-QAM. The simulation of this signal and the model adequacy check were carried out using Matlab software. The next step was the research of influence of filter parameters on the modified detector's noise-immunity during the 8-QAM signal detection. The results of simulation show the optimum parameters at which the maximum noise-immunity of phase detector was achieved. These parameters may be useful for further researches or for the process of phase detector design.

The satellite laser ranging method is based on measuring the transit time of a laser pulse from the transmitter to the satellite and back to the receiver. A special feature of the TPL telescope is that the laser signal is transmitted and received by the same telescope. This requires auxiliary equipment to separate these signals. In addition, this telescope is also used for visual tracking of the object, which adds complexity to the optical design. In most cases, the signals are separated mechanically using rotating mirrors. In one position, the mirrors transmit the signal to a specific channel, and they reflect the optical signal into another channel in the other position. The rotational speed of the mirrors corresponds to the frequency of the laser transmitter. Both mirrors rotate at the same frequency but with a different phase. A logic circuit built on two D-triggers and one 2-input NAND element is used as a phase detector. The paper discusses the scheme and principle of operation of the device for mirror synchronization by signals of the control computer and mirror position sensors. This device has been successfully used at the Riga-1884 laser location station of the University of Latvia. [ABSTRACT FROM AUTHOR]

A new topology that generates a DC voltage whose value is depending on the phase difference of two input RF signals is presented. It is implemented by the mixer concept. With the use of microwave photonics, the mixer-based phase detector can be operated over a very wide frequency range. It also has the advantages of high phase detection resolution, small phase detection error, and small DC offset and phase offset. The phase detector can be constructed using off-the-shelf components including a single integrated optical modulator and a low-speed balanced detector. Measured results on the phase detector demonstrate a 0° to 180° RF signal phase difference detection range for 3.5 GHz to 18 GHz input RF signal frequencies, less than ±3° phase detection error and 2° phase detection resolution. [ABSTRACT FROM AUTHOR]

A cascaded optical modulator topology for detecting the phase difference of two microwave signals is presented. It operates based on mixing of two microwave signals. The phase difference of two microwave signals can be obtained from the system output DC voltage. The phase detector is designed to eliminate the problems of DC offset and phase offset, which are present in reported structures. Experimental results demonstrate phase detection of two microwave signals with a 0° to 180° phase difference, less than ±3° phase detection errors and less than 1 mV DC offset. Results also demonstrate the phase detector can be operated over a wide frequency range. [ABSTRACT FROM AUTHOR]

In this paper, we propose a replica-based all digital delay locked loop(ADDLL). In the ADDLL, the phase detector detects the phase error, and the accumulator(ACC) determines how long the output clock leads to or delays the input clock. In addition, the analog charge pump, loop filter(LF), and voltage controlled delay line are replaced by the ACC and digitally controlled delay line(DCDL), thereby decreasing the leakage current and size of the LF. In this study, the ADDLL uses a replica DCDL to describe a technique for detecting the phase error that may be caused by changes in temperature or supply voltage after the DLL is locked. The proposed DCDL circuit works with a 180 nm CMOS process and has a power consumption of 12 MW, using a supply voltage of 1.8 V at 625 MHz. The total size of the layout is 250×300 μm. [ABSTRACT FROM AUTHOR]

Unlike conventional frequency-locked loop(FLL) oscillators, in this paper, a novel FLL-frequency synthesizer(FLL-FS) is proposed using a resonator with a resonance frequency fL lower than the oscillation frequency. The proposed FLL-FS oscillates at nfL (n is an integer), and comprises a voltage-controlled oscillator(VCO), frequency divider, and frequency detector(FD). To verify the feasibility of the proposed FLL-FS structure, a prototype FLL-FS is presented. The selected resonator was a surface-mount ceramic resonator with a resonance frequency of 11.255 MHz. The FD consists of the selected resonator and an XOR-phase detector. The frequency divider is a fixed-frequency divider and has a division ratio of 128/129. The selected VCO has a frequency tuning range that includes a multiplied frequency of 11.255 MHz by 128/129. The fabricated frequency synthesizer demonstrated a successful FLL-FS operation, and the measured phase noise was −91 dBc/Hz at an offset frequency of 100 kHz. [ABSTRACT FROM AUTHOR]