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In this article, two accurate nonlinear methods are proposed to calculate non-symmetrical locking ranges of the Injected Cross-Coupled Oscillator (ICCO) with the parallel RLC tank and series RL with a parallel C tank for both weak and strong injection levels. By writing governing differential equations of circuit elements of the ICCO, graphical presenting of current vectors, and using the averaging method for solving nonlinear equations, equations of the ICCO are simplified. Then, exact non-symmetrical locking ranges are calculated using the iterative method. Moreover, the describing function of the oscillator's nonlinear part, an inverse tangent function, is applied to the model. The inverse tangent function generates complicated governing differential equations of circuit elements that are accurate. Then, it is solved to ICCO for the first time and has novel results for calculating non-symmetrical locking ranges. There is a good agreement between theoretical and simulation results. The proposed non-symmetrical locking ranges are accurate in both weak and strong injections. The absolute percent of errors for various levels of the injection signal is less than 20%. In the bargain, proposed locking ranges are the most accurate compared to previously published results. [ABSTRACT FROM AUTHOR]

Injection‐locked dividers feature ultrahigh operating frequency, low power consumption, and low phase noise, making them suitable for Q‐band phase‐locked loop. This paper presents a transformer‐based divide‐by‐4 injection locking frequency divider with a high third harmonic rejection buffer based on 40‐nm CMOS technology. Employing a fourth‐order transformer resonator enhances the third‐order harmonic amplitude, increasing the injection efficiency and expanding the locking range. The proposed high third harmonic rejection buffer using a source degeneration inductor can effectively suppress the output of the third harmonic caused by the resonator, ultimately yielding a clean fundamental frequency signal. Simulation results demonstrate that the proposed divide‐by‐4 injection‐locked frequency divider (ILFD) achieves a locking range of 10.2 GHz (from 40.3 to 50.5 GHz) with 0 dBm input signal. The core divide‐by‐4 ILFD circuit consumes 4.6 mW power with a 0.9 V supply and occupies an area of 0.026 mm2. [ABSTRACT FROM AUTHOR]

Conventional current‐reused 8:1 injection‐locked frequency dividers (ILFDs) either use a 2:1 p‐core LC sub‐ILFD stacking on a direct‐injection 4:1 n‐core LC sub‐ILFD or a 2:1 ring‐oscillator LC sub‐ILFD stacking on a direct‐injection 4:1 n‐core LC sub‐ILFD. Because the current‐mode 4:1 n‐core LC sub‐ILFD normally has a smaller locking range, it restricts the locking range of a current‐reused 8:1 ILFD. This article studies a wide locking range 8:1 current‐reused ILFD designed in a 0.18 μm CMOS process. The designed 8:1 ILFD uses a 4:1 ring‐oscillator LC sub‐ILFD stacking on a direct‐injection 2:1 n‐core LC sub‐ILFD. At the core power consumption 19.53 mW and at the incident power of 0 dBm, the 8:1 locking range is 1.11 GHz (65.37%), from the incident frequency 4.16–8.2 GHz. [ABSTRACT FROM AUTHOR]

This paper designs a C-band single-stage $LC$ -tank injection locked frequency quintupler (ILFQ) fabricated in $0.18~\mu \text{m}$ CMOS process. The differential input/output ILFQ circuit is made of a first-harmonic injection-locked frequency oscillator (ILO) and a frequency quadrupler/quintupler. The free-running oscillation frequency of the ILFQ is around 7.6 GHz. At the dc power consumption of 9.9 mW and at the incident power of 0 dBm, the input locking range is from the incident frequency 1.456 GHz to 1.644 GHz to provide an output signal source from the frequency 7.28 GHz to 8.22 GHz. The whole chip occupies a die area of $1.114\times 1.060$ mm2. The designed circuit is also used as a new X-band single-stage LC-tank injection locked frequency quadrupler, which shows measured $\times 4$ output locking range from 7.82 GHz to 8.6 GHz.

High multiplication-factor even-modulus frequency multipliers are often configured as multi series frequency multipliers. This paper designs a single-stage $LC$ -tank injection locked frequency sixtupler (ILFS) fabricated in $0.18~\mu \text{m}$ CMOS process and the ILFS merges many sub-circuits in one by sharing a common supply and passive inductive elements. The circuit design, operation principle and measurement results of the ILFS are addressed. The differential input and single-phase output ILFS circuit is made of two frequency doublers, a first-harmonic injection-locked oscillator and an active frequency tripler using one frequency doubler. The free-running oscillation frequency of the ILO is around 5.716 GHz. At the dc power consumption of 20.9 mW and at the incident power of 0 dBm, the $\times 6$ input locking range is from the incident frequency 0.94 GHz to 1.02 GHz to provide an output signal source from the frequency 5.64 GHz to 6.12 GHz. The whole chip occupies a die area of $1.141\times 1.2$ mm2. Other high multiplier factors are also measured on the designed chip.

Based on a detailed analysis of harmonic generation in ring-based injection-locked frequency dividers (ILFDs), this article shows that concurrent injection signals can be generated in these stages by driving both tail and direct injectors with the same input signal. Based on this result, a novel ring-based divide-by-five ILFD is presented, where multi-injection is reinforced by a dual-path scheme, largely broadening the locking range with no penalty in power dissipation. The stage, implemented in a 28-nm CMOS process, operates over the 8-to-101.6-GHz frequency range achieving a >20% locking over the 13.6–69.1-GHz interval, with 5.6-mW maximum power consumption from a 0.9-V supply. The stage also achieves 101.6 GHz, the highest operating frequency among state-of-the-art CMOS ILFDs by five, with 2.6% locking range. [ABSTRACT FROM AUTHOR]

This paper proposes and analyzes a CMOS divide-by-8 injection locked frequency divider (ILFD) with a divide-by-2 ring oscillator stacked on a capacitive cross-coupled oscillator used as an LC divide-by-4 ILFD. The divide-by-8 ILFD in the TSMC $0.18~\mu \text{m}$ 1P6M CMOS process has a locking range from 15.5 GHz to 17.8 GHz at the power consumption of 10 mW. The varactorless divide-by-8 ILFD occupies a small area of $0.8044\times 0.72$ mm2. The ILFD can be used in divide-by-4 mode and has a locking range from 4.8 GHz to 10.6 GHz at the power consumption of 10.43 mW. The ring oscillator based frequency divider (FD) is designed with a pair of differential outputs so that the whole divide-by-8 ILFD provides differential output. The ring oscillator FD uses unbalanced component parameters to optimize the circuit performance and it supplies two unbalanced tail currents to the LC ILFD, which also provide unbalanced outputs despite the circuit topology is a symmetric one. The unbalanced approach offers design flexibility.

This letter proposes a CMOS divide-by-16 injection-locked frequency divider (ILFD) with a divide-by-4 ring-oscillator frequency divider (FD) stacked on a capacitive cross-coupled LC divide-by-4 ILFD. The divide-by-16 ILFD in the Taiwan Semiconductor Manufacturing Company, Limited (TSMC) $0.18~\mu \text{m}$ 1P6M CMOS process has a locking range from 10.76 to 12.6 GHz at the power consumption of 12.5 mW and an external injected signal power $P_{\mathrm {inj}}$ of 0 dBm. The varactor-less divide-by-16 ILFD uses the ring-oscillator FD with wide locking range to track the input frequency from the LC ILFD output, and occupies an area of $1.2\times1.198$ mm2. [ABSTRACT FROM AUTHOR]

This brief presents a 19–48.3-GHz fully-on-chip divided-by-2 injection-locked frequency divider (ILFD) based on a 6th-order transformer for a wide locking range in 40-nm CMOS technology. The proposed 6th-order transformer extends the resonator’s locking range by introducing more zeros and poles that could widen the frequency range satisfying the locking conditions. Furthermore, an inductive gain peaking technique is adopted to ensure start-up conditions and achieve low power consumption. The measurement results demonstrate a locking range of 29.3 GHz from 19 GHz to 48.3 GHz, which satisfies most applications for different nations’ 5G standards. The chip occupies a core area of 0.0518 mm2 and dissipates 2.88 mW from a 0.6-V voltage supply. [ABSTRACT FROM AUTHOR]

A 73 ~ 106 GHz divide-by-2 injection-locked frequency-divider (ILFD2) using 90 nm CMOS technology is presented. To achieve a wide locking range, an optimal transistor width ratio of the injection transistor (or mixer) and cross-coupled transistors (CCT) is adopted. To enhance the operation frequency, distributed LC network is used as the load of the CCT. To enhance the input sensitivity, an input power matching network is included in the injection transistor. In addition, for further locking ranging enlargement, the inductive peaking and forward-body-bias techniques are used in the injection transistor for raising its quadrature output current (or conversion gain). The ILFD2 consumes 4.92 mW, and achieves an excellent phase noise of – 106.2 dBc/Hz (at 1 MHz offset from the output frequency of 50 GHz). The ILFD2 achieves a wide locking-range of 33 GHz (73–106 GHz (36.9%)), covering the 77 GHz automotive radar frequency band and the 94 GHz imaging radar frequency band. The ILFD2 can be operated at a low input power of – 60 dBm, one of the best input sensitivities ever reported for a W-band CMOS ILFD2. The core area of the ILFD2 is only 0.014 mm2. [ABSTRACT FROM AUTHOR]

A W‐band injection‐locked frequency divider (ILFD) with modified transformer coupling resonant is demonstrated and implemented in a 40‐nm CMOS technology. The locking range and operation frequency of the ILFD is improved without increasing chip area or circuit complexity. The measured locking range of the ILFD covers from 86 to 104 GHz. The measured phase noise of the modified W‐band ILFD is −114.89 dBc/Hz at 1 MHz. The ILFD also attains a figure of merit normalized (FoM) of 243.1. [ABSTRACT FROM AUTHOR]

In this paper, a complete system analysis of photonic local carrier generation technique has been investigated. The generated carrier is potentially suitable to replace the existing microwave/RF Local Carrier (LC) used in commercial Low Noise Blocks (LNBs) for the Phased Array (PA) receiver system. The optical LC generated from heterodyning of two commercialized lasers is being stabilized with an Optical Frequency Lock Loop (OFLL). This approach resulted in a generated carrier at the Ku-band (10.7GHz to 12.75GHz) signal received from a PA receiver. Various loop parameters of the OFLL have been investigated to comply with the requirements of the commercial LNBs The proposed OFLL shows a 2400 fold improvement in the frequency stability at 1000s averaging time compared to its free running condition. It is also demonstrated that with an optimized loop gain of 30dB, the loop response time of the proposed OFLL becomes 11 µs. [ABSTRACT FROM AUTHOR]

This letter simulates and measures a wide locking range LC‐resonator injection‐locked frequency divider (ILFD) designed in the TSMC 0.18 μm process. The balanced‐injection 8:1 ILFD uses a current‐mode design method with one 2:1 p‐core LC sub‐ILFD and one 4:1 n‐core LC sub‐ILFD with wide locking range. The 4:1 sub‐ILFD uses a 5‐turn symmetric octagonal inductor and two 4‐turn inter‐wound transformers and parasitic capacitors to build the LC‐resonator. The primary and the secondary inductors in the 1:1 transformer are identical for simple design. At the core power consumption 9.537 mW and at the incident power of 0 dBm, the measured 8:1 locking range is 1.11 GHz, from the incident frequency 16.83 to 17.94 GHz. The whole CMOS die occupies an area of 0.931 × 1.2 mm2. The simulated 8:1 sub‐ILFD also has wide locking range. [ABSTRACT FROM AUTHOR]

This article presents and analyzes a wide-locking range divide-by-5 injection-locked frequency divider (ILFD) manufactured in the TSMC 0.18- $\mu \text{m}$ processes. The ILFD uses the balanced injection method and uses the pure harmonic mixing approach at low injection power, and it is designed with an RLC dual-resonance resonator. The harmonic mixer relies on the self-generated second harmonic, which increases with injection power. Because of no narrowband filter as used in the linear mixer counterpart, the divide-by-5 ILFD uses a wideband design method. In addition, the ILFD enhances the divide-by-5 locking range via the overlapped dual-band locking ranges as verified by both experiment and simulation. At the drain–source bias ${V} _{\text{DD}}$ of 0.8 V and at the incident power of 0 dBm, the locking range of the divide-by-5 ILFD is 3.6 GHz, from the incident frequency 13.0–16.6 GHz with the percentage 24.3%. The core power consumption is 4.09 mW, and the die area is $1.02\times0.93$ mm2. [ABSTRACT FROM AUTHOR]

This article designs and analyzes LC injection-locked frequency dividers (ILFDs) using dual-resonance LC resonator. The ILFD consists of two single-resonance LC-tank capacitive cross-coupled sub-ILFDs operating at 3.7 and 5.1 GHz, respectively, and the two sub-ILFDs are coupled by the electric field through a pair of metal–insulator–metal (MIM) capacitors. The die area in the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18- $\mu \text{m}$ CMOS is $0.65\times1.023$ mm2. By controlling the gate voltages of the switching transistors, the ILFD has three different operational modes—high-band dominant mode, low-band dominant mode, and concurrent oscillation mode. Overlapped locking range is demonstrated for the first time in the designed electric-field coupling resonator ILFD. Non-overlapped locking range is found for the ILFD manifesting an effect of the dual-resonance resonator. [ABSTRACT FROM AUTHOR]

A novel approach to monitoring the laser injection-locking (IL) state is proposed and verified using the side-mode suppression ratio (SMSR). In a photonics experiment for laser IL, an optical spectrum analyzer with the conventional criterion of a 35-dB SMSR is conventionally used to detect the locking state of a Fabry–Pérot (FP) laser with multiple longitudinal modes to an external master laser with one longitudinal mode. Since the 35-dB criterion is not always a sufficient locking condition, we propose a microwave-photonic technique to determine the stable-locking regime based on the observation of the radio-frequency (RF) components. A novel approach to monitoring the generated additional spectral components uses the well-known delayed-self-homodyne technique and the RF spectrum analyzer. For the novel generation of additional longitudinal groups on each FP laser’s resonator mode in the optical spectrum and consequently the overlapping RF components in the RF spectrum, an additional external resonator with low reflectivity was connected to the slave FP laser. The novel monitoring approach was experimentally verified by connecting a 1-m-long external cavity with 0.5% reflectivity and observing the optical IL phenomenon of a 1550-nm FP semiconductor laser.

In this work, we demonstrate two low-power and wide-locking-range W-band CMOS divide-by-3 injection-locked frequency dividers (ILFD3) using stacked cross-coupled-transistor topology. The first ILFD3 (ILFD31) uses an on-chip balun to transform the single input signal to differential output signals, which are amplified by the lower cross-coupled transistors and then inject the source terminals of the upper cross-coupled transistors. The second ILFD3 (ILFD32) uses a tail transistor to amplify the injection signal, which then injects the source terminals of the lower cross-coupled transistors. Due to the strong second harmonic signal (2finj) at the source terminals of the upper cross-coupled transistors, there are notable locked fundamental signals (finj) at the drain terminals of the upper cross-coupled transistors. ILFD31 occupies a chip area of 0.744 × 0.859 mm2 (i.e. 0.639 mm2), consumes a low power of 1.6 mW, and achieves a locking range of 3.4 GHz (92.5-95.9 GHz). ILFD32 occupies a chip area of 0.87 × 0.775 mm2 (i.e. 0.674 mm2), consumes a low power of 0.13 mW, and achieves an excellent locking range of 18 GHz (91.8-109.8 GHz), one of the best results ever reported for W-band CMOS ILFD3s. [ABSTRACT FROM AUTHOR]

Abstract An actively mode-locked laser (AMLL) is subjected to RF modulation frequency detuning away from its fundamental resonant frequency. The standard theoretical model of mode-locked lasers is extended with perturbative analysis and injection locking theory. The proposed model shows that with increasing detuning, the number of modes with phase-lock decreases. For a mode n , the injection range R n is found to decrease as n − 1 , thus making higher modes more susceptible to unlocking by RF detuning. Experimental verification of these theoretical predictions is obtained by using a custom built Yb 3 + doped fiber based ring AMLL. The AMLL operates at 1064 nm , with a repetition rate of f 0 = 26. 69 MHz. The unlocking of modes is studied in the electrical domain by varying the RF detuning over a range of ± 13 kHz with a step-size of 130 Hz. The locking limits of a mode decrease as n − 1 as predicted by the theory. The fundamental mode (n = 1) has an injection range of 143. 4 kHz , with the higher modes, n > 1 , having smaller injection ranges as predicted by the theory. [ABSTRACT FROM AUTHOR]

The paper presents a method based upon the statistical linearisation technique of evaluating the locking range of a single loop optoelectronic oscillator for an angle modulated signal corrupted with Gaussian noise. Experimental results along with formulas for calculating the locking range along with the system equation are presented and they are in good agreement with the theoretical results. Some new findings regarding the dependence of locking range on the input carrier to noise ratio are reported. [ABSTRACT FROM AUTHOR]

Abstract: A comprehensive study on the output power, the modulation response, and the relative intensity noise (RIN) behavior of an optically injection‐locked mid‐infrared quantum‐cascade laser reveals that the modulation bandwidth and the output power are enhanced in the stable locking range, while the RIN of the slave laser is a superposition of the master and slave noise sources. Since the RIN level of the master laser can even take the lead, a design procedure is introduced to improve the main characteristics of a free‐running laser, including the RIN, the photon lifetime, the modulation bandwidth, and the bias current, using facet reflectivity tailoring. A figure of merit is defined and the RIN reduction of about 20 dB Hz−1 is obtained for very low injection powers compared with the injection‐locked system before the design of master laser. [ABSTRACT FROM AUTHOR]

Closed-form expressions are derived for predicting the locking ranges and the amplitudes of the locked oscillations of injection locking frequency dividers (ILFDs) with dual-resonance tank. The stability of the predicted locked-states is also assessed, showing that these are always stable in the locking ranges. These results are obtained by a proper transformation of the circuit equations that are reduced to a quasi-normal form by a suitable change of the circuit variables and then solved by applying the method of slowly varying amplitudes and phases. The derived formulas give results significantly more accurate than that resulting from the well-known Adler’s equation, improperly applied in practice to ILFDs with dual resonance tank. Numerical results, obtained by using BSIM3 transistor models, validate the presented results. [ABSTRACT FROM PUBLISHER]

Summary: A wide locking range divide‐by‐5 injection‐locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18‐μm 1P6M CMOS process. Conventional divide‐by‐5 ILFD has limited locking range. The proposed divide‐by‐5 ILFD is based on a capacitive cross‐coupled voltage‐controlled oscillator (VCO) with a dual‐resonance resonator, which is implemented in the divide‐by‐5 ILFD to obtain a wide overlapped locking range. At the drain‐source bias VDD of 0.9 V and at the incident power of 0 dBm, the measured locking range of the divide‐by‐5 ILFD is 3.2 GHz, from the incident frequency 9.4 to 12.6 GHz, the percentage is 29.09%. The core power consumption is 2.98 mW. The die area is 0.987 × 1.096 mm2. [ABSTRACT FROM AUTHOR]

The generation by optical injection locking of spectrally unadulterated microwave signals using waveguide based external cavity semiconductor lasers (WECSL) is demonstrated. A tunable frequency of 2−11 GHz, limited by the modulator’s bandwidth and the photodetector (PD), was created as proof-of-experiment by the injection locking of the two WESCLs. A single sideband (SSB) phase noise of −75 dBc/Hz from the generated carrier at 10 kHz offset and a phase noise variance at an optimum injection ratio region was 0.03 rad2, corresponding to 1.7°, were observed. The main feature of this approach is the consolidation of the upsides of microwave generation at low phase noise with a broad tuning range and the capacity of hybrid photonic integration. In addition, the injection locking characteristics were used to determine the Q factor of the complicated optical cavities with unknown inner losses.

A W-band injection-locked frequency divider (ILFD) with low-power and wide locking range is presented in this paper. The operation frequency and locking range are enhanced by using split transformer-coupled oscillator. The optimum bias and the size of the injection transistor are chosen to achieve wider locking range without increasing chip area and dc power consumption. The proposed ILFD is implemented in 90-nm CMOS and exhibits 25.4% locking range from 75.1 to 99 GHz at an input power of 0 dBm without any tuning mechanism. The core dc power consumption is 2.45 mW with a supply voltage of 0.7 V and the core chip size is $0.13 \times 0.2$ mm2. [ABSTRACT FROM PUBLISHER]

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A varactorless divide-by-4 injection-locked frequency divider (ILFD) with LC resonator is designed. The ILFD uses the parasitic capacitors and the inductor architecture to construct a dual-resonance resonator. The ILFD has two locking ranges associated with the dual-resonance resonator. The locking range of the ÷4 ILFD is wider than conventional single-band ÷4 LC-tank ILFD because of overlapped locking ranges. The designed single-stage ÷4 ILFD was fabricated in the TSMC 0.18 μm 1P6M CMOS process. At the incident power of 0 dBm, the locking range is 6.6 GHz from 7.3 to 13.9 GHz at the power consumption of 5.59 mW. [ABSTRACT FROM AUTHOR]

A triple-band divide-by-2 LC injection-locked frequency divider (ILFD) was implemented in the TSMC 0.18 μm 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt 4th order LC resonators to form a 6th order resonator with three resonant frequencies. Measured data has shown that the ILFD has three locking ranges at fixed bias condition or by varactor bias switching. [ABSTRACT FROM AUTHOR]

A wide locking range nMOS divide-by-2 RLC injection-locked frequency divider (ILFD) was designed and implemented in the TSMC 0.18-µm BiCMOS process. The ILFD is based on a cross-coupled oscillator with one direct injection MOSFET and a RLC resonator. The RLC resonator is used to extend the locking range so that dual-band locking ranges can be merged in one locking range at both low and high injection powers. At the drain-source bias of 0.9 V for switching transistors, and at the incident power of 0 dBm the locking range of the divide-by-2 ILFD is 7.24 GHz, from the incident frequency 2.65 to 9.89 GHz, the locking range percentage is 115.47%. The power consumption of ILFD core is 8.685 mW. The die area is 0.726 × 0.930 mm2. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

We present a novel frequency tracking method that exploits the dynamics of injection locking in a quadrature ring oscillator to increase the effective locking range from 5% (7–7.4 GHz) to 90% (4–11 GHz). The quadrature phase error between I and Q phases of an injection locked ring oscillator is derived and shown to contain frequency error information, both inside and outside the locking range. This error is utilized to form a first-order frequency tracking quadrature locked loop (QLL). This loop generates accurate clock phases for a 4-channel parallel optical receiver using a forwarded clock at quarter-rate. The QLL drives an ILO at each channel without any repeaters for local quadrature clock generation. Each local ILO has deskew capability for phase alignment. The receiver maintains a constant energy-per-bit consumption across 16–32 Gb/s by adaptive body biasing in a 28 nm FDSOI technology. [ABSTRACT FROM PUBLISHER]

A wide-locking range divide-by- 3~LC injection-locked frequency divider (ILFD) is proposed and implemented in the TSMC 0.18- \mu \text{m} 1P6M CMOS process. The divide-by-3 ILFD uses a cross-coupled nMOS pair, an injection MOSFET pair, and a sixth-order RLC resonator. The divide-by-3 ILFD has three oscillation frequency bands and three locking ranges. At the drain-source bias V\mathbf {DD} of 0.9 V and at the incident power of 0 dBm, by switching a varactor bias, the high-band, middle-band, and low-band locking ranges of the ILFD are, respectively, given by 3.47 GHz (33.87%) from 8.51 to 11.98 GHz, 3.72 GHz (54.86%) from 4.92 to 8.64 GHz, and 1.05 GHz (19.76%) from 4.88 to 5.93 GHz. The operation range is 7.1 GHz (84.2%) from 4.88 to 11.98 GHz. The ILFD-core power consumption is 6.759 mW. A wider locking range of 4.43 GHz (67.07%) from 4.39 to 8.82 GHz is obtained by overlapping the three locking ranges at a fixed bias condition. The die area is 0.991 \times 1.04 mm2. [ABSTRACT FROM PUBLISHER]

This paper reviews the use of capacitive cross-coupled oscillator in the design of wide locking-range injection-locked frequency dividers (ILFDs). The advantages of capacitive cross-coupled ILFDs as compared to direct cross-coupled ILFDs are lower power consumption and wider locking range. Experimental examples of CMOS divide-by-2, divide-by-3 and divide-by-4 ILFDs are used to demonstrate the RF performance improvement by using this circuit topology. [ABSTRACT FROM AUTHOR]

A novel wide locking range divide-by-4 injection-locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18 µm 1P6M CMOS process. The divide-by-4 ILFD uses two injection transistors in series and DC-biased above threshold voltage and a frequency doubler to enhance the function of linear mixers. At the drain-source bias of 0.9 V and at the incident power of 0 dBm, the locking range of the divide-by-4 is 2.6 GHz; from the incident frequency 12.2 to 14.8 GHz, the percentage is 19.26%. The core power consumption is 10.35 mW. The die area of ILFD is 1.026 × 0.943 mm2. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The pulse repetition rate (RR) tuning and locking range (LR) as well as the pulse train timing stability of passively mode‐locked quantum‐well (QW) semiconductor lasers (SCLs) subject to single‐cavity optical self‐feedback (OFB) are investigated experimentally and by simulations. A simple and universal stochastic time‐domain model confirms the experimentally observed RR control and LR as well as timing jitter (TJ) improvement in QW SCLs subject to very long OFB cavities with lengths up to 73.1 m. In particular, the model allows predicting control potential and limits of the RR tuning, locking and TJ improvement depending on the choice of OFB delay length for time‐delay mode‐locked semiconductor laser stabilisation experiments. [ABSTRACT FROM AUTHOR]

Wide locking range is an important parameter for injection-locked frequency divider (ILFD) to cope with the supply voltage variation. This paper proposes a wide locking range divide-by-4 ILFD implemented in the TSMC 0.18 μm 1P6 M CMOS process. The ILFD uses a capacitive cross-coupled voltage-controlled oscillator as the core. The dc gate bias of cross-coupled FETs is smaller than dc drain bias to optimize the power and locking range. Dual-resonance LC resonator is also used to enhance the locking range. At the drain-source bias of 1.2 V, and at the incident power of 0 dBm the measured locking range of divide-by-4 ILFD is 3.3 GHz, from the incident frequency 7.5-10.8 GHz, the percentage is 36.06%. The core power consumption is 11.83 mW. The die area is 0.883 × 0.851 mm. [ABSTRACT FROM AUTHOR]

A wide locking range and operation range push–push divide-by-4 injection-locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18 μm BiCMOS process. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator for easy startup oscillation and single-ended injected dual-injection transistors. The common drain node of dual injection transistors is AC-tied to the output of a frequency doubler. At the drain-source bias of 0.8 V, and at the incident power of 0 dBm the operation range of the divide-by-4 is 3.23 GHz, from the incident frequency 15.85 to 19.08 GHz, the percentage is 18.49%. The locking range of the divide-by-4 is 1.4 GHz, from the incident frequency from 17.08 GHz to 19.08 GHz, the percentage is 11.06%. The core power consumption is 6.53 mW. The die area is 0.83×0.597 mm 2 . [ABSTRACT FROM AUTHOR]

A novel wide locking range divide-by-2 injection-locked frequency divider (ILFD) is proposed in the paper and was implemented in the TSMC 0.18-µm 1P6M CMOS process. The divide-by-2 ILFD is based on a cross-coupled voltage-controlled oscillator (VCO) with an LC resonator and injection MOSFETs with source voltage coupled from ILFD output, and the injection MOSFET mixer is biased in subthreshold region. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm the locking range of the divide-by-2 ILFD is 6.4 GHz; from the incident frequency 3.7 GHz to 10.1 GHz, the percentage is 92.75%. The core power consumption is 16.56mW. The die area is 0.839 × 0.566mm². [ABSTRACT FROM AUTHOR]

ABSTRACT This letter presents a wide-locking range CMOS divide-by-3 injection-locked frequency dividers (ILFD) using single-ended injection signal. The fabricated 0.18 μm CMOS ÷3 ILFD uses cross-coupled switching transistors, single-injection MOSFET, and a dual-resonance RLC resonator. The consumed power of the ÷3 ILFD core is 7.97 mW at the DC drain-source voltage 0.76 V. At an external injected signal power Pinj = 0 dBm, the measured locking range is 2.97 GHz (25.25%) from 10.28 to 13.25 GHz and the operation range is 5.17 GHz (48.5%) from 8.08 to 13.25 GHz. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2720-2723, 2015 [ABSTRACT FROM AUTHOR]

The present paper, aside considering the influence of a forcing signal, discusses the effect of frequency modulated synchronizing signal on optoelectronic oscillator and the corresponding FM–AM conversion for the injection synchronized optoelectronic oscillator is studied. A method to calculate the locking range of a synchronized angle modulated OEO is presented. The amplitude and phase equations are derived using the cyclic passage theory utilizing Barkhausen's criteria. The variation of modulation index and locking range with fiber delay has been presented. Finally, the growth of oscillation amplitude and the phase-plane plot of the system are studied. It is to be noted that nothing has been reported on the synchronizing capability of the angle modulated OEO as far as the knowledge of the authors goes. [ABSTRACT FROM AUTHOR]

ABSTRACT A wide locking range, injection locked frequency divider (ILFD) circuit topology is explored. The modulus-four ILFD utilizes a cross-coupled voltage-controlled oscillator in conjunction with transformer feedback, parallel-tuned resonator, and two-segment, series mixers at the injection point. The transformer feedback and two-segment mixing circuit topology achieves a locking range of 2.7 GHz (14.1 to 16.8 GHz) at an injection point bias of 0.9 Vdc and 0 dBm injection power. Spectral measurements at the ILFD output demonstrate proper phase-lock operation and expected phase noise reduction using a high quality signal source at the ILFD input. The ILFD is implemented in the TSMC 0.18 μm 1P6M CMOS process, utilizes a die area of 0.839 × 0.566 mm2 and consumes 16.56 mW. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:557-562, 2015. [ABSTRACT FROM AUTHOR]