Search

Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless SOI FinFET by different spacer engineering techniques with hafnium based (HfxTi1-xO2) high-k dielectric in the gate stack. The device process parameters like dielectric spacer impact, nano-fin geometry variation, and power analysis along with DC, Analog/RF, and linearity metrics at the nanoscale are investigated. To increase the accuracy of results at lower gate lengths, quantum models are involved by using TCAD simulator. The proposed device shows excellent electrical characteristics with DIBL = 10.6 mV/V, SS = 63.6 mV/dec, switching ratio (ION/IOFF) = ~107 and good ON-OFF performance metric Q = gm/SS = 2.06 × 10−5 S-dec/μm-mV even at 5 nm LG. The performance impact of outer low-k spacer dielectric variation in dual-k spacer reveals that performance enhancement of ~77% in terms of switching ratio, reduction of leakage current by ~73%, and improvement of gm by ~10% have been noticed from SiO2 + HfO2 to Si3N4 + HfO2. However, due to high-k dielectric in dual-k spacer gate capacitances increases, which leads to deterioration of RF parameters like ft, τ, and GBW. The Air single-k spacer shows good performance for RF applications with ft = 600 GHz, τ = 1 ps, GBW = 1.23 THz and dynamic power = 0.095 fJ/μm at LG = 5 nm. However, the linearity characteristics deteriorates for dual-k spacers and higher dielectric single-k spacers (SiO2, Si3N4) has been noticed. This investigation reveals that at nanoscale Air spacer outperforms all other spacer combinations for low power applications and better linearity (low distortion), and assures further scaling for RF applications. [ABSTRACT FROM AUTHOR]

Since our demonstration of unsupervised learning using the CMOS-only charge-trap transistors (CTTs) as analog synapses, there has been an increasing interest in exploiting the device for various other neural network (NN) applications. However, most of these studies are limited to mere simulation due to the absence of detailed experimental device characterization. In this article, we provide a comprehensive investigation of the programming behavior of CTTs, including analog retention, intra- and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array. It is found that, after programming, the channel current gradually increases to a higher level, and the shift is larger when the device is programmed to a higher threshold voltage. With this postprogramming current increase appropriately accounted for, individual devices can be programmed to an equivalent precision of five bits, and three bits can be achieved for devices in an array. Our results reveal the promising future of using the CTT as a CMOS-only analog memory device. [ABSTRACT FROM AUTHOR]

With the transition to ≤28-nm CMOS technology nodes, the surface analytical challenges with regard to steadily decreasing dimensions and still growing materials options raise the demand of high performing surface analysis techniques. Characterization of ultrathin films and multilayer stacks, especially in high-k metal gate stacks, by means of low energy ion scattering spectroscopy (LEIS) with its monolayer sensitivity has been established as a very useful analysis technique next to Auger electron spectroscopy, , and time-of-flight secondary ion mass spectrometry. Questions regarding film nucleation, growth, coverage, and diffusion can be answered, thereby enabling those processes to be controlled appropriately. In this work, growth studies of ALD HfO2 and TiN are shown, as well as film thickness determination based on surface spectra. PVD aluminum and lanthanum, acting as work function metals on the gate oxide, were deposited, and their film formation and closure were investigated. Further application fields of LEIS have emerged from the characterization of in-die features on patterned wafers. As presented on test arrays, it is possible to detect material deep in trenches. This is an advantage if residues need to be identified after etch or clean processes. [ABSTRACT FROM AUTHOR]

In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125°C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore's gap between the high-performance logic and the embedded memory. [ABSTRACT FROM AUTHOR]

As standard planar transistors have reached their scaling limit new sophisticated architectures have found their way into mass production. One option is the Fully Depleted Silicon-on-Isolator (FDSOI) technology, which combines performance efficiency with a cost effective, planar architecture. Approximately, 75% of the process steps in FDSOI can be leveraged from the established 28 nm bulk technology, while there are certain process modules that require the introduction of new processes, i.e., low- k spacer deposition and the epitaxial growth of SiGe gate channels and Si:B, SiGe:B source/drain regions. In this article, we want to focus on the deposition of the low- k spacer, which provides low gate-to-drain capacitances. The standard SiN spacer was replaced by a SiBCN spacer. Electrical results show a clear 10% increase in ring-oscillator frequency. [ABSTRACT FROM AUTHOR]

The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials.

Ultra-thin interfacial silicon oxide layers are grown by microwave-based plasma oxidation at temperatures below 200 °C. The influence of plasma gas composition and plasma pulsing on layer properties is tested. The oxides are compared to standard thermally grown oxide and wet chemical oxide. Layer properties are evaluated by x-ray photo electron spectroscopy and are electrically characterized by means of TiN/HfO 2 /SiO 2 high-k metal gate stacks. [ABSTRACT FROM AUTHOR]

A 128 Mb 0.07 \mu\m^2 6T high-density SRAM bitcell with write-assist circuitry has been successfully implemented using 16 nm high-k metal gate FinFET technology. This study proposes two write-assist techniques: 1) suppressed coupling signal negative bit-line (SCS-NBL) technique and 2) write recovery enhanced lower cell-VDD (WRE-LCV) technique to reduce the SRAM minimal supply voltage. The area overheads of these two techniques are 2% and 3%, respectively. The silicon data show that both of these techniques can improve overall SRAM VMIN performance by more than 300 mV at the 95th percentile. [ABSTRACT FROM PUBLISHER]

This paper reports a new static RAM (SRAM) cell featuring its self-matching characteristic for enhanced static noise margin (SNM) in low-voltage applications. This new SRAM employs trimming devices replacing pull-down transistors to compensate mismatches. Through a blanket trimming operation enabling self-matching of the two branches, effective suppression of variability with improved SNM distribution has been successfully demonstrated in nanoscaled SRAMs. [ABSTRACT FROM AUTHOR]

In this brief, threshold voltage mismatch of fully integrated n-type FinFETs based on a gate-first process was studied experimentally. Significantly improved threshold voltage mismatch due to undoped FIN body was confirmed with the experimental data. By comparing mismatch values of thin- and thick-oxide nMOS, we found that factors, which do not scale with gate oxide thickness, including line edge roughness and metal-gate granularity (MGG), can explain \sim60\% of total mismatch of thin-oxide devices. Moreover, we report a convex shape of threshold voltage mismatch following the increase of the number of FINs and propose a possible explanation of the abnormal behavior. Due to channel width quantization, two competing contributors impact mismatch: as FIN number becomes smaller mismatch due to MGG likely play an important role which increases threshold voltage mismatch, whereas FIN number becomes larger, systematic variation becomes the main factor, which also increases threshold voltage mismatch. [ABSTRACT FROM PUBLISHER]

Abstract: The replacement metal gate (RMG) defectivity control is very challenging for high-k metal gate (HKMG) RMG chemical mechanical polishing (CMP) processes. In this study, three major defect types, including fall on particle, micro-scratch and corrosion, post Al metal CMP process have been investigated to provide the total solutions for preventing the formation of these defects. The fall on particles were fully removed as a repulsive force created between the surfaces of the Al metal gate and polishing abrasives by introducing appropriate acid based slurries and chemical solutions. Furthermore, the micro-scratches could be significantly eliminated as implementing a reliable soft pad at the final polishing step. Severe integranular corrosion and pitting issues on the surface of the RMG structures were also found to be effectively prevented by creating a capable passivation layer with minimized micro-galvanic corrosion level on the top surface of the Ti-doped Al metal gate structures. [Copyright &y& Elsevier]

Abstract: The fundamental film properties and micro-structures of the different aluminum (Al) metal layers are evaluated to fabricate a replacement metal gate (RMG) device for the high-k metal gate (HKMG) application at 28nm node. A PVD Al fill-in metal deposition process, called one step hot Al (HAL), was found the resistivity increases with increasing the thickness of the Ti wetting layer. The higher pinhole density with the preferred (111) crystal orientation in the HAL layers indicate the film properties with lower reflectivity, higher resistivity and lower removal rate of the Al chemical mechanical polishing (AlCMP). In contrast, the other PVD Al deposition approach, called two steps cold hot Al (CHAL), was identified to possess lower resistivity and higher reflectivity without pinhole structures than the HAL. The smaller grain sizes with the preferred (220) orientation in the CHAL could effectively prevent the formation of pinhole and enhance the removal rate of the AlCMP. The non-uniform with crystallized TiAl3 phase detected in the bottom of the as-deposited HAL and CHAL films could obviously impact the removal rate of the AlCMP. An optimized CHAL fill-in metal deposition process with a larger than 40Å Ti wetting layer are needed to simultaneously meet the process requirements of the Al gapfill and AlCMP planarization for achieving a reliable RMG structures. [Copyright &y& Elsevier]

We report on ultrascaled (LG = 23 nm) compressively strained SiGe-based FDSOI pMOSFET with ultrathin body. The devices have been fabricated using a high-K metal gate (TiN/HfSiON) process flow. SiGe channels (3.4 nm) have been epitaxially grown on 3-nm thick 300-mm SOI wafers and combined with embedded Si0.7Ge0.3(:B) raised source and drain (RSD) for Vth,p tuning and smart strain management. Indepth electrical characterizations point out the +120-mV Vth,p tuning, the excellent short-channel, and DIBL control (similar to SOI reference), and show for the first time extremely low variability for SiGe-based FD pMOSFETs. Furthermore, we investigate hole-transport properties as a function of gate length and temperature and demonstrate 60% Raccess reduction with SiGe RSD and +330% mobility enhancement at 23-nm gate length with respect to 7-nm thick SOI reference. [ABSTRACT FROM AUTHOR]

The authors have addressed the application of advanced ion beam-based analytical techniques to various physical characterization aspects in sub-32-nm semiconductor front-end-of-line materials and processes. We have presented the application of 18O-isotope labeling in combination with SIMS depth profiling to follow O-migration in high- k/metal gate stacks. We have also demonstrated the application of complementary low-energy ion scattering and time-of-flight SIMS surface analysis to determine high- k thin film closure and growth mode for different deposition techniques. We have also proposed alternative Dynamic Secondary Ion Mass Spectrometry (DSIMS) protocols for the quantitative analysis of phosphorous ultra-shallow junctions, resulting in more accurate near-surface P-profile and in situ B-doped Si1− xGe x epitaxial films with explicit correction of sputter and ionization yield variations as function of [Ge]. We have demonstrated the feasibility of backside SIMS on appropriate III-V high-mobility channel stacks, resulting in unprecedented depth resolution at the source/drain metal-contact/III-V interface. Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

Abstract: Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs. [Copyright &y& Elsevier]

We investigated the formation of an ultra-thin (<10 Å) and a highly stable interfacial layer (IL) using an ozonated deionized water (DIW-O 3) for Si 0.75 Ge 0.25 channel material. X-ray photoelectron spectroscopy (XPS) results confirmed the presence of mainly SiO 2 with minor contributions from GeO x (GeO and GeO 2) in the interfacial oxide layer. High resolution transmission electron microscopy (TEM) and X-ray energy dispersive spectroscopy (XEDS) confirms the absence of elemental Ge in the HfO 2 film indicating a stable interface between the high-k and SiGe channel. An excellent electrical performance was achieved with an inversion layer thickness (T inv) of 13.5 Å, peak hole mobility of 180 cm2 V−1.s−1 and peak interface trap defect density (N it) of 4–4.5 × 1011 cm−2. As demonstrated, physical properties of Si 0.75 Ge 0.25 IL is well correlated to the electrical performance highlighting the ability of DIW-O 3 based IL to serve as an ideal candidate for integrating SiGe channel material in high-volume manufacturing. Unlabelled Image [ABSTRACT FROM AUTHOR]