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We investigate the MX2 (M = {Hf, Zr}, X = {S, Se}) transition metal dichalcogenides patterned into armchair (AC) and zigzag (ZZ) nanoribbons (NRs) as potential channel materials in future logic field-effect devices. Ab initio quantum transport simulations are employed to assess the electronic, transport, and ballistic field-effect transistor (FET) properties of devices with such quasi-one-dimensional channels. We report a non-monotonic scaling behavior of MX2NR properties due to strong quantum confinement effects, which is reflected in a strong dependence of the ON-state current (ION) of MX2NR FETs on the nanoribbon configuration. The ∼2 nm-wide HfSe2 and ZrSe2 AC-PFETs have the highest ION of up to 2.6 mA/μm at 10 nA/μm OFF-state current. Surprisingly, MX2NR ZZ-NFETs exhibit a current increase of up to 70% when channel width is scaled down, with ION reaching 2.2 mA/μm in ∼2 nm-wide devices. The high ON-state performance is a direct consequence of high carrier injection velocity, which is explained by analyzing the band structure, transmission, and density of states. We demonstrate that nanostructured MX2 materials can be promising candidates for future logic transistors based on multi-nanowire architectures. [ABSTRACT FROM AUTHOR]

The deep-level drain current transient spectroscopy (Id-DLTS) measurements of Al -doped SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) strongly suggest that the reduction in the channel mobility at low temperatures is related to a shallow trap detectable at 70 K. Using the Shockley–Reed–Hall (SRH) theory, the level of this trap has been extracted to be around 0.15 eV below the conduction band minimum of SiC. Density functional theory (DFT) calculations of Al Si N C Al Si and Al Si O C Al Si defect complexes have found one configuration of the Al Si O C Al Si complex, which has a charge transition level within the SRH extracted trap level range. Therefore, we suggest that these Al Si O C Al Si defects are likely candidates for traps responsible for the channel mobility reduction. [ABSTRACT FROM AUTHOR]

Large Schottky barriers formed at the interfaces between graphene and 2D semiconductors often degrade device performance. Here, taking the Janus MoSO as a prototype and using the first-principles calculations together with the band unfolding technique, we demonstrate that the Ohmic contact (OC), which is absent in pristine graphene/MoXY (X/Y = S, Se, Te. X ≠ Y), is realized in the pristine graphene/MoSO (G/MoSO) heterostructure. G/OMoS shows the n -type OC (OC- n) that leads to the p -doping of the graphene layer with a hole density of 1.17 × 10 13 /cm 2 , while G/SMoO exhibits the p -type Schottky contact with a tunable Schottky barrier height. The realization of OC and the interface dependent contact type are mainly attributed to the large intrinsic dipole between asymmetric S and O layers, which dominate the different behaviors of charge transfer and the associated interface dipole in heterostructures. Inspired by the finding, considering the larger dipole moment in Janus MoSeO and MoTeO, we further confirm that both OC- n and OC- p exist in pristine G/MoSeO and G/MoTeO. Moreover, on comparison with MoSO, both G/OMoS and G/SMoO show enhanced optical absorptions (∼ 10 5 cm − 1 ) in most of the visible light range. Our results not only show the potential application of G/MoSO in nanoelectronic devices such as field-effect transistors but also indicate that dipole engineering would help us to predict or design desirable electric contacts of Janus-transition metal dichalcogenide-based metal/semiconductor systems in advance. [ABSTRACT FROM AUTHOR]

The successful synthesis and discovery of unique properties in two-dimensional Janus materials have positioned them as promising candidates for applications in sensors, field-effect transistors, and ultrasensitive detectors. In this study, we utilized first-principles calculations to predict a novel Janus CeIBr monolayer. Our calculations show that Janus CeIBr monolayer behaves as a bipolar magnetic semiconductor, demonstrating both mechanical and thermodynamic stability, along with a high Curie temperature of 242 K and in-plane magnetic anisotropy (102.92 meV). A notable intrinsic valley splitting of 66 meV is also evident in CeIBr, highlighting its distinctive valley contrast characteristic. Furthermore, the application of biaxial strain effectively transforms the magnetic ground state of CeIBr from a ferromagnetic state to an antiferromagnetic state and alters the direction of the easy magnetization axis from in-plane to out-of-plane. Our findings offer a theoretical foundation for the design of novel anomalous valley Hall effect-based electronic devices utilizing the Janus CeIBr monolayer. [ABSTRACT FROM AUTHOR]

4H-SiC/ SiO 2 interface states play a major role in the performance and reliability of modern 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs). To gain new insights into these interface states, we developed a cryogenic measurement technique that uses photon-assisted electron depopulation to probe device performance limiting 4H-SiC/ SiO 2 interface states. This technique enables the characterization of shallow as well as deep states at the 4H-SiC/ SiO 2 interface of fully processed devices using a cryogenic probe station. Our method is performed on n-channel 4H-SiC MOSFET test structures with deposited oxide and postoxidation anneal. We identify conditions under which the electrons remain trapped at 4H-SiC/ SiO 2 interface states and trigger the controlled photon-assisted electron depopulation within a range of photon energies. This allows us to prove the presence of near interface traps, which have previously been found in thermally grown 4H-SiC MOS structures. Our results are supported by device simulations. Additionally, we study the impact of irradiation intensity and light exposure time on the photon-induced processes. [ABSTRACT FROM AUTHOR]

We propose a main mechanism of large valley splitting experimentally observed at the interface of buried oxide (BOX)/silicon-on-insulator (SOI) structures. Silicon metal-oxide-semiconductor field effect transistors fabricated on a SIMOX (001) substrate, which is a kind of the SOI substrate, that is annealed at high temperatures for a long time are known to exhibit large valley splitting, but the origin of this splitting has long been unknown. Extended zone effective-mass approximation predicts that strain significantly affects valley splitting. In this study, we analyzed valley splitting based on this theory and found that the shear strain along [110] of approximately 5% near the BOX interface is a promising source for large valley splitting. [ABSTRACT FROM AUTHOR]

The ultra-wide bandgap of gallium oxide provides a rich plethora of electrically active defects. Understanding and controlling such defects is of crucial importance in mature device processing. Deep-level transient spectroscopy is one of the most sensitive techniques for measuring electrically active defects in semiconductors and, hence, a key technique for progress toward gallium oxide-based components, including Schottky barrier diodes and field-effect transistors. However, deep-level transient spectroscopy does not provide chemical or configurational information about the defect signature and must, therefore, be combined with other experimental techniques or theoretical modeling to gain a deeper understanding of the defect physics. Here, we discuss the current status regarding the identification of electrically active defects in beta-phase gallium oxide, as observed by deep-level transient spectroscopy and supported by first-principles defect calculations based on the density functional theory. We also discuss the coordinated use of the experiment and theory as a powerful approach for studying electrically active defects and highlight some of the interesting but challenging issues related to the characterization and control of defects in this fascinating material. [ABSTRACT FROM AUTHOR]

In this paper, the p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) with varying combinations of gate metal work function and gate geometry are fabricated and investigate the influence of gate leakage current (IGS) on the threshold voltage (VTH) and subthreshold swing (SS). The unique dependence of VTH and SS on gate geometry for different metals is observed, which is different from traditional field-effect transistors. A novel hybrid physics model, consisting of the traditional capacitance divider model and hole injection model, is proposed to explain this phenomenon, and the results exhibit an excellent agreement with the experimental data. The holes traverse the gate/p-GaN Schottky barrier by thermal emission or tunneling and inject into the p-GaN layer, generating the IGS. Expanding upon the traditional capacitance divider model, a portion of the injected holes accumulate at the p-GaN/AlGaN interface and induce the corresponding electrons at the AlGaN/GaN heterojunction, which promotes channel conduction. Hence, the transfer curves display the correlation between IGS and VTH as well as SS. The results show that high IGS can alleviate the instability of VTH caused by the lithographic overlay error, and simultaneously optimize SS. This work offers a novel perspective for examining the turn-on mechanism of p-GaN HEMTs, thereby contributing to device design. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a hydrogen-terminated diamond (H-diamond) field-effect transistor (FET) with Al2O3/CeB6 gate materials. The CeB6 and Al2O3 films have been deposited by electron beam evaporation technique, sequentially. For the 4/8/12/15 μm gate length (LG) devices, the whole devices demonstrate distinct p-type normally off characteristics, and all the threshold voltage are negative; all the absolute values of leakage current density are 10−4 A/cm2 at a VGS of −11 V, exhibiting a relatively low leakage current density compared with CeB6 FETs, and this further demonstrates the feasibility of the introduction of Al2O3 to reduce the leakage current density; the maximum drain–source current density is −114.6, −96.0, −80.9, and −73.7 mA/mm, which may be benefited from the well-protected channel. For the 12 μm LG devices, the saturation carrier mobility is 593.6 cm2/V s, demonstrating a good channel transport characteristic. This work may provide a promising strategy for the application of normally off H-diamond FETs significantly. [ABSTRACT FROM AUTHOR]

Molybdenum disulfide (MoS2), a semiconducting two-dimensional layered transition metal dichalcogenide (2D TMDC), with attractive properties enables the opening of a new electronics era beyond Si. However, the notoriously high contact resistance (RC) regardless of the electrode metal has been a major challenge in the practical applications of MoS2-based electronics. Moreover, it is difficult to lower RC because the conventional doping technique is unsuitable for MoS2 due to its ultrathin nature. Therefore, the metal–insulator–semiconductor (MIS) architecture has been proposed as a method to fabricate a reliable and stable contact with low RC. Herein, we introduce a strategy to fabricate MIS contact based on atomic layer deposition (ALD) to dramatically reduce the RC of single-layer MoS2 field effect transistors (FETs). We utilize ALD Al2O3 as an interlayer for the MIS contact of bottom-gated MoS2 FETs. Based on the Langmuir isotherm, the uniformity of ALD Al2O3 films on MoS2 can be increased by modulating the precursor injection pressures even at low temperatures of 150 °C. We discovered, for the first time, that film uniformity critically affects RC without altering the film thickness. Additionally, we can add functionality to the uniform interlayer by adopting isopropyl alcohol (IPA) as an oxidant. Tunneling resistance across the MIS contact is lowered by n-type doping of MoS2 induced by IPA as the oxidant in the ALD process. Through a highly uniform interlayer combined with strong doping, the contact resistance is improved by more than two orders of magnitude compared to that of other MoS2 FETs fabricated in this study. [ABSTRACT FROM AUTHOR]

The rising temperature due to a self-heating or thermal environment not only degrades the subthreshold performance but also intensifies thermal stress, posing a severe challenge to device performance and reliability design. The thermal stress effects on the ON-state performance of the p-type fin field-effect transistor were previously studied. However, as far as we know, how thermal stress affects its subthreshold conduction remains unclear, which is studied in this manuscript. The impact of thermal stress due to the self-heating of adjacent devices on subthreshold conduction is investigated by solving the quantum transport, thermal conduction, and force balance equations for ballistic transport and dissipative transport with phonon scattering. Then, the thermal stress effects at different ambient temperatures are further discussed and analyzed. The simulation results show that the OFF-state leakage current can be reduced by thermal stress, even up to 9.28% for the (110)/[001] device operating at an ambient temperature of 550 K, and its reduction is the comprehensive result of the thermal stress effects on the band structure, potential profile, carrier distribution, and source-to-drain tunneling. In addition, the thermal stress has no significant effects on subthreshold swing although it can change the magnitude of the subthreshold current. Moreover, the effect of thermal stress on subthreshold conduction is highly dependent on the thermal environment of the device and the crystal orientation of the channel semiconductor material. [ABSTRACT FROM AUTHOR]

The performance of SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) degrades seriously after a period of continuous operation. To directly understand this issue, we conduct real-time time-dependent density functional theory (TDDFT) simulations on a series of nitrogen passivated SiC– SiO 2 interfaces to monitor the interaction between carriers and interface atoms. We find that the nitrogen passivation always leaves behind two local states near the VBM, which gives a chance to the strong interaction between channel carriers and C–N bonds, and finally results in the generation of C dangling bond defects. These processes are vividly presented and confirmed by the TDDFT simulation. Additionally, the results show that the new defects are more easily formed by the passivated C cluster than the passivated Si vacancy. These studies provide physical insights into the degradation mechanisms of working SiC MOSFETs, while simultaneously demonstrating the advantage of TDDFT as a crucial tool for investigating defect generation dynamics in semiconductor devices. [ABSTRACT FROM AUTHOR]

Gallenene is a novel metallic 2D material that can provide a semiconducting counterpart if patterned into quasi-one-dimensional (quasi-1D) nanostructures, i.e., gallenene nanoribbons (GaNRs). We investigate semiconducting GaNRs as a potential channel material for future ultrascaled field-effect transistors (FETs) by employing quantum transport simulations based on Green's functions and tight-binding Hamiltonians with the orbital resolution calibrated on ab initio calculations. The impact of GaNR width downscaling from ∼6 nm down to ∼0.2 nm on the electronic, transport, and ballistic device properties is investigated for the FET channel length of 15 nm. We report current enhancement and injection velocity overshoot effects for sub-1.2 nm-wide nFETs and pFETs, with a maximum current increase of 53% in the 1.2 nm-wide GaNR pFET in comparison to the widest device. In addition, promising current-driving capabilities of n- and p-channel GaNR FETs are observed with top ballistic currents of more than 2.2 mA/μm and injection velocities of up to 2.4 × 107 cm/s. The reported data are explained by analyzing the evolution of band structure and related parameters such as injection velocity, quantum capacitance, effective transport mass etc., with increasing quantum confinement effects in ultranarrow GaNRs. Generally, we find that quasi-1D gallenene is a promising channel material for future nanoscale FETs, especially for transistor architectures based on stacked nanosheets. [ABSTRACT FROM AUTHOR]

Negative differential resistance (NDR) is observed in various emerging electronic devices. As compared to the conventional silicon-based field effect transistor (FET), the NDR is widely investigated in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs. In this work, we study the NDR effect for the TMD-based metal-edge-contact MoS 2 double-gate FET with 10 nm channel length. The multiscale atomistic simulation is demonstrated for the lateral heterostructure of a metal–semiconductor–metal FET by density functional theory, maximally localized Wannier function tight-binding Hamiltonian, and non-equilibrium Green's function methods. The quantum transport model in the given lateral heterostructure resulted in NDR in a double-gate FET. Here, we focus on the NDR by the systematic study of the transmission spectrum of the metal-edge-contact MoS 2 channel FET and finally compare it with zero NDR ideal highly doped FET. The peak-to-valley ratio in the NDR response can be modulated with the change in the gate-to-source voltage and can be used to explore various future electronic applications. [ABSTRACT FROM AUTHOR]

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices. [ABSTRACT FROM AUTHOR]

Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process. [ABSTRACT FROM AUTHOR]

For over half a century, traditional silicon-based integrated circuits (ICs) have been the basis of computational electronics and are widely used in computers, cell phones, and other fields. With the rapid development of human society, silicon-based semiconductor technology is approaching its physical and engineering limits. Our increasing diversity of non-traditional computing needs, such as ultra-small, ultra-fast, ultra-low-power wearables, and space radiation protection, is driving the search for new electronic materials. Semiconducting single-walled carbon nanotubes (s-SWCNTs) have many excellent electrical properties, such as high carrier mobility and high ballistic transport, making them strong candidates for new semiconductor materials in the post-Moore era. Carbon-based electronic technology has been developed for over 20 years, and the fundamental issues such as the material purification of s-SWCNTs, preparation prospects of s-SWCNT-based field-effect transistors (CNT FETs), and device physics based on CNT FETs have been basically solved. However, the chiral diversity of s-SWCNTs may lead to problems such as fluctuations in the electrical performance of CNT FETs, limiting the application of s-SWCNTs in high-end ICs. Monochiral s-SWCNTs not only have excellent electrical properties but also have a controllable structure and uniformity, which are crucial for the high-end IC of CNTs. However, some problems exist in the purity and yield of monochiral s-SWCNT preparation and the optimization of monochiral CNT FETs. Therefore, the chiral sorting of CNTs is reviewed in this paper, and the progress of polymer reprocessing in chiral separation is highlighted. Then, the research progress of monochiral CNT FETs is introduced, and possible development directions are summarized and analyzed. Finally, the application prospects of chiral-enriched s-SWCNTs include challenges and future opportunities. [ABSTRACT FROM AUTHOR]

The relocation of peripheral transistors from the front-end-of-line (FEOL) to the back-end-of-line (BEOL) in fabrication processes is of significant interest, as it allows for the introduction of novel functionality in the BEOL while providing additional die area in the FEOL. Oxide semiconductor-based transistors serve as attractive candidates for BEOL. Within these categories, In2O3 material is particularly notable; nonetheless, the excessive intrinsic carrier concentration poses a limitation on its broader applicability. Herein, the deposition of Hf-doped In2O3 (IHO) films via atomic layer deposition for the first time demonstrates an effective method for tuning the intrinsic carrier concentration, where the doping concentration plays a critical role in determine the properties of IHO films and all-oxide structure transistors with Au-free process. The all-oxide transistors with In2O3: HfO2 ratio of 10:1 exhibited optimal electrical properties, including high on-current with 249 µA, field-effect mobility of 13.4 cm2 V−1 s−1, and on/off ratio exceeding 106, and also achieved excellent stability under long time positive bias stress and negative bias stress. These findings suggest that this study not only introduces a straightforward and efficient approach to improve the properties of In2O3 material and transistors, but as well paves the way for development of all-oxide transistors and their integration into BEOL technology. [ABSTRACT FROM AUTHOR]

Theoretical models have predicted that pH-responsive surface groups can reduce the sensitivity of field-effect transistor biosensors. However, attempts to prove this experimentally have shown conflicting results. In this work, a graphene field effect transistor (gFET) biosensor is used, which, without modification, is pH insensitive. The surface of the graphene is then functionalized using 1-hydroxypyrene to modulate the pH sensitivity of the gFET. A pH sensitivity ranging from 3.9 to 36.8 mV/pH was demonstrated. The biosensitivity of the gFETs was tested using streptavidin–biotin as a model system. The experimental results showed no correlation between biosensitivity and pH sensitivity. An electrochemical membrane model was used to determine the expected relationship between biosensitivity and pH sensitivity. The model results show that biosensitivity does not decrease until a certain threshold pH sensitivity is reached. This threshold is dependent on factors such as the acid dissociation constants of the surface hydroxyl groups and ion concentration. Furthermore, the differences between the simulation and experiment suggest that the effect of screening is greatly reduced when the analyte binds within a membrane. [ABSTRACT FROM AUTHOR]

In this study, the ungated AlGaN/GaN devices with special mesa structures were designed. The hypothesis of effective width expansion was tested experimentally by using ungated samples with different sizes, and an empirical expression for calculating the conduction channel effective width was given according to the experimental results. Finally, split-gate AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate lengths were prepared, and the channel electron mobility of split-gate samples was calculated by using the empirical expression and polarization Coulomb field (PCF) scattering theoretical model. The results showed that, for split-gate AlGaN/GaN HFETs, with the increase in the gate length, the total amount of additional polarization charges underneath the gate increases, resulting in the enhancement of the PCF scattering intensity. [ABSTRACT FROM AUTHOR]

This paper investigates near-interfacial charge trapping effects in graphene field-effect transistors with high-K gate dielectrics. Experimental and model-based analysis elucidates the impact of trapped charge on the transport properties of graphene. Landauer formalism is applied to correlate trapping-enhanced charged impurity scattering to degradation in conductivity and mobility. The analysis shows a significant reduction in conductivity and mobility with a transition toward the dominance of charge impurity scattering as evidenced by their dependence on the sheet carrier density. Moreover, we quantify the impact of trapped charge buildup on the carrier backscattering mean free path associated with charged impurities. This work provides new insights into the impact of charge trapping toward the development of logic, memory, and neuromorphic devices based on graphene and other low-dimensional materials and ultrascaled high-K dielectrics. [ABSTRACT FROM AUTHOR]

Graphene-based field-effect transistors (FETs) are suitable for pH sensors due to their outstanding surface chemical properties and its biocompatibility. To improve the devices' stability and pH sensitivity, different sets of dielectric passivation layers composed of monolayer hexagonal boron nitride with and without aluminum oxide layers were evaluated. Non-linearities of the pH response were observed. Heterostructure FETs were derived from subtractive manufacturing of commercially transferred two-dimensional materials on four-inch SiO2/Si wafers via stainless steel and polypropylene masking. Phosphate solutions (10 mM) of varying pH were incubated on bare devices, whereby liquid-gating elucidated linear changes in the Dirac voltage of hBN/graphene (−40 mV/pH) that was smaller than a device consisting only of monolayer graphene (−47 mV/pH). Graphene-based FETs were passivated with aluminum oxide nanofilms via electron beam or atomic layer deposition and were observed to have distinct Raman spectral properties and atomic force microscopy topologies corroborating the hypothesis that morphological differences of the deposited aluminum oxide influence the pH-dependent electrical properties. Atomic layer deposition of aluminum oxide on the 2D sensing areas resulted in non-linear shifting of the Dirac voltage with respect to pH that evolved as a function of deposition thickness and was distinct between graphene with and without hexagonal boron nitride as a capping monolayer. The non-linear response of varying thickness of AlxOy on graphene-based FETs was progressively reduced upon basic wet etching of the AlxOy. Overall, passivated graphene-based transistors exhibit deposition-dependent pH responses. [ABSTRACT FROM AUTHOR]

We propose and analyze the performance of terahertz (THz) room-temperature bolometric detectors based on the graphene channel field-effect transistors (GC-FET). These detectors comprise the gate barrier layer (BL) composed of the lateral hexagonal-boron nitride black-phosphorus/hexagonal-boron nitride (h-BN/b-P/h-BN) structure. The main part of the GC is encapsulated in h-BN, whereas a short section of the GC is sandwiched between the b-P gate BL and the h-BN bottom layer. The b-P gate BL serves as the window for the electron thermionic current from the GC. The electron mobility in the GC section encapsulated in h-BN can be fairly large. This might enable a strong resonant plasmonic response of the GC-FET detectors despite relatively lower electron mobility in the GC section covered by the b-P window BL. The narrow b-P window diminishes the Peltier cooling and enhances the detector performance. The proposed device structure and its operation principle promote elevated-temperature GC-FET THz detector responsivity values and other characteristics, especially at the plasmonic resonances. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) power devices are becoming central components in high voltage electronics. However, defects at interfaces and in the bulk continue to severely impact their reliability and performance. Here, we develop a charge pumping method to characterize SiC/SiO 2 interface defects in fully fabricated commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). The method is then used to address spin states at the SiC/SiO 2 interface via charge pumping electrically detected magnetic resonance (CP-EDMR). We apply these methods to investigate the power MOSFET after electron irradiation over a dose range of 10 13 − 10 17 cm − 2 . We finally discuss CP-EDMR as a technique to interrogate spins during device operation for real-time monitoring of the device quality, performance, and degradation and as a probe for local magnetic fields. [ABSTRACT FROM AUTHOR]

Field-effect transistors (FETs) made from colloidal quantum dot (QD) solids commonly suffer from current–voltage hysteresis caused by the bias-stress effect (BSE), which complicates fundamental studies of charge transport in QD solids and the use of QD FETs in electronics. Here, we show that the BSE can be eliminated in n-channel PbSe QD FETs by first removing the QD ligands with a dose of H2S gas and then infilling the QD films with alumina by atomic layer deposition (ALD). The H2S-treated, alumina-infilled FETs have stable, hysteresis-free device characteristics (total short-term stability), indefinite air stability (total long-term stability), and a high electron mobility of up to 14 cm2 V−1 s−1, making them attractive for QD circuitry and optoelectronic devices. The BSE-free devices are utilized to conclusively establish the dependence of the electron mobility on temperature and QD diameter. We demonstrate that the BSE in these devices is caused by both electron trapping at the QD surface and proton drift within the film. The H2S/alumina chemistry produces ligand-free PbSe/PbS/Al2O3 interfaces that lack the traps that cause the electronic part of the BSE, while full alumina infilling stops the proton motion responsible for the ionic part of the BSE. Our matrix engineering approach should aid efforts to eliminate the BSE, boost carrier mobilities, and improve charge transport in other types of nanocrystal solids. [ABSTRACT FROM AUTHOR]

Switching a silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor between inversion and accumulation with removed drain and grounded source terminals leads to defect-assisted carrier recombination and light emission. The energy spectrum of the emitted photons provides valuable information on the involved defects, located both at the 4H-SiC/ SiO 2 interface and in the 4H-SiC bulk. Here, we measured and analyzed the emitted light over a broad temperature range between 12 and 297 K. Our results reveal two local maxima in light intensity around 30 and 140 K. Most importantly, the local intensity maxima and the related temperatures correlate with both the overall recombination current and gate capacitance measurements. The spectral analysis allowed us to distinguish between recombinations occurring on 4H-SiC bulk defects and 4H-SiC/ SiO 2 interface-related defects. We explain an initial increase of light emission with decreasing temperature to competing non-radiative pathways with activation energies of 34 and 60 meV for SiC/ SiO 2 interface- and 4H-SiC bulk-related emissions, respectively. Based on an extensive literature review, we link the measured photon emission to donor–acceptor pair recombination, the EH 6 / 7 or the Z 1 / 2 defect centers. In addition to that, we could link a prominent peak at 2.915 eV to the L 1 line of the D 1 -center. Most importantly, we conducted our own ab initio simulations revealing that recombination via P bC -centers, previously identified with carbon dangling bonds at the 4H-SiC/ SiO 2 interface [Cottom et al., J. Appl. Phys. 124, 045302 (2018)], could also provide an explanation for the photon emission around 1.75 eV. Finally, our simulation of an interface-related silicon vacancy V Si , I reveals a radiative transition around 2.8 eV. [ABSTRACT FROM AUTHOR]

In this work, we study the electronic properties of nanotubes with spin–orbit interaction that exhibit a spin Hall effect. Nanoribbons made of these materials are expected to have topologically protected states. The lack of edge states in a seamless tube eliminates the possibility of finding a topological edge state. The spin–orbit interaction breaks the degeneracy of Dirac's cones and eliminates the chance of finding a metal nanotube. As a consequence, this makes all nanotubes with spin–orbit interaction trivial band insulators. We focus our attention on two features. First, we study the energy band gap as a function of the diameter of the nanotubes. Then, we concentrate on controlling the bandgap of a nanotube by applying an external radial electric field. Finally, we discuss the possibility of using one of these tubes as a field-effect transistor. [ABSTRACT FROM AUTHOR]

We implemented an ion-sensitive field effect transistor (ISFET) array chip comprising n-ISFET and p-ISFET for sensor application using 0.18 μ m CMOS technology. N-channel metal-oxide semiconductor (NMOS) and P-channel metal-oxide semiconductor (PMOS) ISFETs are fabricated in regular dimensions (< 8 μ m) compatible with the standard CMOS process. We implemented n-ISFET cells and p-ISFET cells of different dimensions for characterization and to observe the possible effect of scalability. Each cell also has two identical NMOS and PMOS ISFETs of standard dimension, unlike very large dimensions (> 200 μ m). We are using metals 1–6 and via together on the gate area to make it an extended or floating gate for the electrochemical sensing of ISFET. These metals are electrically floating with an intermediate dielectric. These different-size floating gate ISFETs provide different sensing areas, and the passivation Si3N4 layer is used for pH sensing without any extra post-processing measures. We observe the ISFET sensitivity and performance with the 0.18 μ m technology submicron effect. The measured results propose ISFET as a promising sensor device for portable applications. The ISFET chip dimension is 1179 μ m × 1185 μ m. [ABSTRACT FROM AUTHOR]

One-dimensional (1D) semiconductor nanostructures exhibit exceptional performance in mitigating short-channel effects and ensuring low power consumption. However, the scarcity of high-mobility p-type 1D materials impedes further advancement. Molecular-based materials offer high designability in structure and properties, making them a promising candidate for 1D p-type semiconductor materials. A molecular-based 1D p-type material was developed under the guidance of coordination chemistry. Cu–HT (HT is the abbreviation of p-hydroxy thiophenol) combines the merits of highly orbital overlap between Cu and S, fully covered surface modification with phenol functional groups, and unique cuprophilic (Cu–Cu) interactions. As such, Cu–HT has a remarkable hole mobility of 27.2 cm2 V−1 s−1, which is one of the highest reported values for 1D molecular-based materials to date and even surpass those of commonly used amorphous silicon as well as the majority of 1D inorganic materials. This achievement underscores the significant potential of coordination polymers in optimizing carrier transport and represents a major advancement in the synthesis of high-performance, 1D p-type semiconductor materials. [ABSTRACT FROM AUTHOR]

The current study concerns highly reliable visible light sensing by C60 fullerene functionalized single‐walled carbon nanotube (SWCNT) based phototransistor. The absorbance of visible light (532 nm) increases significantly due to the formation of an interlink between the SWCNT network and C60 clusters. Photogenerated excess electrons in SWCNT are trapped by the C60 clusters and increase the effective hole concentrations in the SWCNT channel, which eventually improves the photoconductive gain. C60‐SWCNT channel is further integrated into the back gated field effect transistor (FET) structure in which 90 nm SiO2 dielectric thickness is used. The responsivity toward visible light is further enlarged with appropriate negative gate electrostatic. In order to ensure the morphological and structural behavior of C60‐SWCNT, various microscopic and spectroscopic characterizations are performed. The C60‐SWCNT phototransistor exhibits responsivity of 1.219 A W−1 at Vgs = – 21 V. The detectivity and rise/fall time of C60‐SWCNT came around to be 2.34 × 1010 Jones, 86.42 ms/3.35 ms at the same Vgs. The maximum external quantum efficiency (EQE) of the C60‐SWCNT phototransistor is very high, ≈274%. In the overall study, a comprehensive discussion is introduced on the effect of variable gate potential on the performance of the C60‐SWCNT phototransistor. [ABSTRACT FROM AUTHOR]

In the case of low-dimensional semiconductor devices, the basic physical properties of materials can be measured through device manufacturing using single crystal synthesis and exfoliation, but for expansion into various application fields, technology that can synthesize the material itself directly on the substrate is needed. For multi-composition low-dimensional semiconductor materials like Nb2Pd3Se8, the physical characteristics of constituent elements differ, making direct growth control on a substrate extremely challenging. This study successfully synthesized Nb2Pd3Se8 wires using different metal precursors (niobium and palladium) through liquid precursor–intermediated chemical vapor deposition (LPI-CVD). By adjusting the concentration of the liquid precursor and the synthesis temperature, the reproducible growth of Nb2Pd3Se8 wires was achieved, ranging in lengths from 2.29 to 15.04 μm. It was confirmed that PdSe2 is initially synthesized at lower temperatures (below 620 °C), and at temperatures above 620 °C, this PdSe2 transforms into Pd17Se15. Nb2Pd3Se8 is synthesized from the Pd17Se15 at these higher temperatures. X-ray diffraction (XRD) analysis revealed that the wires exhibit a preferred orientation along the (210) plane. Electronic device fabrication using these wires demonstrated their application potential as n-type semiconductors. Field-effect transistor (FET) measurements revealed remarkable performance, with an Ion/Ioff ratio of 575 and an electron mobility of 2.03 cm2 V−1 s−1. LPI-CVD provides a promising strategy for synthesizing ternary chalcogenide materials, opening possibilities for exploring diverse ternary phases. This study highlights the importance of controllability, reproducibility, and FET performance in growing Nb2Pd3Se8 wires via the CVD system, thereby paving the way for integrated applications and facilitating mixed-dimensional studies with other nanomaterials. [ABSTRACT FROM AUTHOR]

In the case of low-dimensional semiconductor devices, the basic physical properties of materials can be measured through device manufacturing using single crystal synthesis and exfoliation, but for expansion into various application fields, technology that can synthesize the material itself directly on the substrate is needed. For multi-composition low-dimensional semiconductor materials like Nb2Pd3Se8, the physical characteristics of constituent elements differ, making direct growth control on a substrate extremely challenging. This study successfully synthesized Nb2Pd3Se8 wires using different metal precursors (niobium and palladium) through liquid precursor–intermediated chemical vapor deposition (LPI-CVD). By adjusting the concentration of the liquid precursor and the synthesis temperature, the reproducible growth of Nb2Pd3Se8 wires was achieved, ranging in lengths from 2.29 to 15.04 μm. It was confirmed that PdSe2 is initially synthesized at lower temperatures (below 620 °C), and at temperatures above 620 °C, this PdSe2 transforms into Pd17Se15. Nb2Pd3Se8 is synthesized from the Pd17Se15 at these higher temperatures. X-ray diffraction (XRD) analysis revealed that the wires exhibit a preferred orientation along the (210) plane. Electronic device fabrication using these wires demonstrated their application potential as n-type semiconductors. Field-effect transistor (FET) measurements revealed remarkable performance, with an Ion/Ioff ratio of 575 and an electron mobility of 2.03 cm2 V−1 s−1. LPI-CVD provides a promising strategy for synthesizing ternary chalcogenide materials, opening possibilities for exploring diverse ternary phases. This study highlights the importance of controllability, reproducibility, and FET performance in growing Nb2Pd3Se8 wires via the CVD system, thereby paving the way for integrated applications and facilitating mixed-dimensional studies with other nanomaterials. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistors (Fe-FETs) offer promising candidates for neuromorphic computing. However, it is still challenging to achieve a light-tunable field effect, which limits the function of photo-synapse. In this work, a ferroelectric semiconductor floating-gate transistor (FSF-FET) is proposed based on MoS2/h-BN/α-In2Se3 van der Waals heterojunctions (vdWHs), in which the two-dimensional ferroelectric semiconducting α-In2Se3 and dielectric h-BN serve as the trapped layer of charges and prevent layer, respectively. The excellent memory performances are exhibited, including a high programming/erasing ratio of over 107, a large memory window ratio of 74.69%, and good non-volatility. Moreover, the FSF-FETs also possess the light-tunable synapse behaviors, including the high paired-pulse facilitation of 236% and an obvious transition from short-term plasticity to long-term plasticity. The high recognition rate of 93.9% is achieved with dual-mode modulation of light and electrical pulses. The ferroelectric semiconductor floating-gate design opens up a strategy to realize the light-tunable field effect of Fe-FETs for photo-synapse. [ABSTRACT FROM AUTHOR]

This study aims to reduce the fabrication complexity and cost of nanoscale devices by utilizing a Junction-less Vertical TFET based on charge plasma for unmarked detection in biological sensors. The Heterojunction Ferro dioxide charge plasma Vertical Tunnel Field Effect Transistor (HJ-F-CP-VTFET) architecture offers the potential to streamline manufacturing processes and lower production costs. A small gap in the gate dielectric is created by selectively etching away the gate oxide layer near the source end. Initially, the drain current characteristics of two devices, HJ-Si-CP-VTFET and HJ-F-CP-VTFET, are compared. Following this, the impact of varying the length, thickness, work function and dielectric constant of the gap under different bias settings is investigated to understand the sensing characteristics of the HJ-F-CP-VTFET. The biosensor is evaluated and compared with the HJ-F-CP-VTFET, focusing on parameters such as total current density, electron concentration, BTBT e-Tunneling rate, electric field, energy band diagram, electron and hole concentration and SRH recombination rate across a range of kvalues from 1 to 12. The ATLAS device simulator is used for all simulations and designs. For the value k = 12, the device HJ-F-CP-VTFET Ion/Ioff current ratio outcome is 1.116 × 1011. [ABSTRACT FROM AUTHOR]

Vertical field effect transistor (VFET), in which the semiconductor is sandwiched between source/drain electrodes and the channel length is simply determined by the semiconductor thickness, has demonstrated promising potential for short channel devices. However, despite extensive efforts over the past decade, scalable methods to fabricate ultra-short channel VFETs remain challenging. Here, we demonstrate a layer-by-layer transfer process of large-scale indium gallium zinc oxide (IGZO) semiconductor arrays and metal electrodes, and realize large-scale VFETs with ultra-short channel length and high device performance. Within this process, the oxide semiconductor could be pre-deposited on a sacrificial wafer, and then physically released and sandwiched between metals, maintaining the intrinsic properties of ultra-scaled vertical channel. Based on this lamination process, we realize 2 inch-scale VFETs with channel length down to 4 nm, on-current over 800 A/cm2, and highest on-off ratio up to 2 × 105, which is over two orders of magnitude higher compared to control samples without laminating process. Our study not only represents the optimization of VFETs performance and scalability at the same time, but also offers a method of transfer large-scale oxide arrays, providing interesting implication for ultra-thin vertical devices. Vertical field-effect transistors (VFETs) have potential for the realization of ultra-scaled devices, but their fabrication is usually limited by trade-offs between scalability and channel length. Here, the authors report a large-scale transfer method to realize indium gallium zinc oxide/graphene VFETs with van der Waals metallic contacts and reduced channel length. [ABSTRACT FROM AUTHOR]

Ferroelectrics are essential in memory devices for multi-bit storage and high-density integration. Ferroelectricity mainly exists in compounds but rare in single-element materials due to their lack of spontaneous polarization in the latter. However, we report a room-temperature ferroelectricity in quasi-one-dimensional Te nanowires. Piezoelectric characteristics, ferroelectric loops and domain reversals are clearly observed. We attribute the ferroelectricity to the ion displacement created by the interlayer interaction between lone-pair electrons. Ferroelectric polarization can induce a strong field effect on the transport along the Te chain, giving rise to a self-gated ferroelectric field-effect transistor. By utilizing ferroelectric Te nanowire as channel, the device exhibits high mobility (~220 cm2·V−1·s−1), continuous-variable resistive states can be observed with long-term retention (>105 s), fast speed (<20 ns) and high-density storage (>1.92 TB/cm2). Our work provides opportunities for single-element ferroelectrics and advances practical applications such as ultrahigh-density data storage and computing-in-memory devices. Authors find room-temperature ferroelectricity in single element Te nanowires, highlighting that reducing dimensions to 1D in low-dimensional piezoelectric materials with chain structures is an effective strategy to induce ferroelectricity absent in their 2D form. [ABSTRACT FROM AUTHOR]

The field-effect transistors (FETs) based on reduced graphene oxide (rGO) with SiO2, porous silicon (PS), and oxidized porous silicon (PSox) supporting layers were obtained. The influence of charged impurities in the silicon substrate and electrically active defects in the support layers on the electrical properties of the FETs was studied based on the capacitance-voltage characteristic analysis. Localized electron states in the SiO2, PS, and PSox supporting layers that affect the charge transfer in the rGO-based FETs were determined using thermally stimulated depolarization spectroscopy. The influence mechanisms of various supporting layers on the electrical characteristics of the obtained FETs are discussed. [ABSTRACT FROM AUTHOR]

This paper presents simulation analysis of an inverter made from non-aligned double gate field effect transistors (NADGFETs) in Sub-100 nm regime. The inverter consists of n-channel NADGFET and p-channel NADGFET device with a channel length of 40 nm and 50% non-alignment between gate and source/drain. The response of the inverter was tested by a combination of gate dielectric constant (k) and metal work function (ϕ). Three gate dielectrics namely, SiO2 (k = 3.9), Si3N4 (k = 7.2), HfO2 (k = 24), and three metal work function namely tungsten (ϕ = 4.5 eV), molybdenum (ϕ = 4.75 eV), gold (ϕ = 5 eV), were considered in the NADGFET inverter. This paper defines a kϕ index as characterising parameter to explore the best response from inverter configuration with minimum propagation delay, and minimum power consumption at super-high frequency. The paper proposes to analyse the NADGNFET device, in term of ION current, ION/IOFF ratio, cut-off frequency, and gate delay. And observes that low k material with moderate metal work function gives best response. The work then simulates the inverter and group the results into voltage transfer curve (VTC), transient response, and power dissipation category. The result shows that when inverter was subjected to high frequency, all the kϕ combination responds good, however when the inverter was subjected to super-high frequency, the low value of kϕ combination performs well. Thus, the result concludes that SiO2-M2 combination will be best selection to get minimum propagation delay and dynamic power dissipation by the inverter. The test strategy presented in this paper on the basis of kϕ index can serve as benchmark to test inverter device at super-high frequency. [ABSTRACT FROM AUTHOR]

The facile spin coating fabrication of high‐dielectric‐constant (high‐k) multicomponent (Al,Ti,V,Zr,Hf)Ox films with an equivalent oxide thickness of ≈0.95 nm and the investigation of their thermal stability and dielectric and electrical properties of the resulting advanced metal–oxide–semiconductor (MOS)‐based electronic devices are reported in this study. Various heating conditions, including drying following spin coating, annealing after drying, and forming gas annealing, were investigated to optimize the quality of the films and reduce film defects. The favorable film‐based MOS devices exhibited robust capacitance–voltage (C–V) and current–voltage (I–V) characteristics with a remarkable k value of approximately 62 at 1 kHz. The thermal stability of the films was affirmed through a rapid thermal annealing treatment at 900°C for 5 s and observation of nondegraded C–V and I–V curves. The electrical performance of the resulting MOS field‐effect transistors (MOSFETs), including a threshold voltage of 0.4 V, an on/off ratio of 106, a saturated mobility of 40.1 cm2 V−1 s−1, and a subthreshold swing of 66.7 mV dec−1, was obtained. Moreover, hole‐ and electron‐trapping measurements through negative and positive gate bias stress instabilities, respectively, indicate the reliable performance of our MOSFETs. Our results imply that solution‐based processes are promising for fabricating fundamental semiconductor devices. [ABSTRACT FROM AUTHOR]

The piezotronics effect utilizes a piezopotential to modulate and control current in piezo-semiconductors. Ferroelectric materials, as a type of piezoelectric materials, possess piezoelectric coefficients that are significantly larger than those found in conventional piezoelectric materials. Here, we propose a strain modulated ferroelectric field-effect transistor (St-FeFET) utilizing external strain instead of gate voltage to achieve ferroelectric modulation, which eliminates the need for gate voltage. By applying a very small strain (0.01%), the St-FeFET can achieve a maximum on-off current ratio of 1250% and realizes a gauge factor (GF) of 1.19 × 106, which is much higher than that of conventional strain sensors. This work proposes a new method for realizing highly sensitive strain sensors and presents innovative approaches to the operation methods of ferroelectric field-effect transistors as well as potential applications for coupling of strain sensors and various devices across different fields. [ABSTRACT FROM AUTHOR]

This study introduces a biosensor employing a dielectric-modulated dual material gate tunnel field effect transistor (DM-DMG TFET) in 10 nanometer technology. To detect diverse bio molecules, the biosensor incorporates a nano gap cavity formed through gate overlap on the drain side. The variation in ambipolar current serves as the sensing parameter, influenced by altering the dielectric constants of immobilized bio molecules within the nano cavity. In this paper, the simulation results of biosensor employing a dielectric-modulated dual material gate tunnel field effect transistor with different dielectric constants imposed in nano cavity. A comprehensive examination of the biosensor's performance is conducted, exploring various positions and filling factors of bio molecules within the nano cavity region. This analysis involves a thorough investigation into the device's performance, considering a range of parameters such as drain current, electric field distribution, variations in surface potential, configurations of energy bands, behaviors of carrier concentration, and the Ion/Ioff ratio. The simulations are done using the Silvaco TCAD Atlas tool. [ABSTRACT FROM AUTHOR]

Adders and subtractors are essential to many integrated circuits (IC), including microprocessors, and micro controllers. However, using complementary metal oxide semiconductor (CMOS) and field effect transistor (FET) technology to make conventional adders and subtractors increased transistor count and power consumption. So, this effort begins with hybrid adder-subtractor designs using FinFET and graphene nano-ribbon FET(GnrFET) nano technologies. Initial development of an enhanced full adder with carry prediction (EFOCP) based on multiplexer logic with rapid carry-output selection reduced sum estimation delays. The considerable reduction in carry-output selection time led to this finding. The dynamic path auto-configurable adder (DPAA) selects high-speed and low-speed carry propagation channels using the EFOCP module. The DPAA was also used to create a two-complement based dynamic path auto-configurable subtractor (DPAS). Last, the dynamic path auto-configurable joint adder-subtractor (DPAJAS) combines DPAA and DPAS. Compared to existing approaches, the proposed DPAJAS design reduces Total Energy Consumption (TEC) by 23.3%, Total Path Delay (TPD) by 17.9%, and Carry Out Rise Delay by 18.2%. It also reduces Carry Out Fall Delay (COFD) by 19.4%, Sum Rise Delay (SRD) by 18.2%, and Sum Fall Delay by 18.3%. Finally, the proposed DPAJAS reduces Average Power Consumption (APC) 17.6%. These enhancements demonstrate the higher performance and efficiency of the proposed EFOCP, DPAA, DPAS, and DPAJAS designs. [ABSTRACT FROM AUTHOR]

Solid-state nanopores offer a range of distinct advantages over biological nanopores, such as structural diversity and greater stability and durability; this makes them highly promising for high-resolution nanoparticle sensing. Biological nanopores can exhibit gating characteristics with stress-responsive switches and can demonstrate specificity toward particular molecules. Drawing inspiration from biological nanopores, this paper introduces a novel polymer nanopore with field-effect characteristics, leveraging a conductive polymer in its construction to showcase intriguing gating behavior. Notably, in this device, the polymer layer serves as the gate, enabling precise control over the source–drain current response inside and outside the pore by simply adjusting the gate voltage. This unique feature allows fine-tuning of the nanopore's sensitivity to nanoparticles of varying sizes and facilitates its operation in multiple modes. Experimental results reveal that the developed polymer nanopore field-effect transistor demonstrates remarkable selectivity in detecting nanoparticles of various sizes under different applied voltages. The proposed single device demonstrates the exceptional ability to detect multiple types of nanoparticle, showcasing its immense potential for a wide range of applications in biological-particle analysis and medical diagnostics. ARTICLE HIGHLIGHTS: • Sub-100-nm nanopipettes were processed by glass-capillary pulling, electrodeposition, and electropolymerization. • The reduction in nanopore tip diameter due to polymer deposition improves the efficiency of the detection of nanoparticles with different sizes, materials, and electrical properties. • By modulating the bias applied to the polymer at the nanopore tip, flexible regulation of nanoparticle translocation events can be achieved. [ABSTRACT FROM AUTHOR]

Graphene films grown by the chemical vapor deposition (CVD) method suffer from contamination and damage during transfer. Herein, an innovative ice‐enabled transfer method under an applied electric field and in the presence of Cu2O (or Cu2O‐Electric‐field Ice Transfer, abbreviated as CEIT) is developed. Ice serves as a pollution‐free transfer medium while water molecules under the electric field fully wet the graphene surface for a bolstered adhesion force between the ice and graphene. Cu2O is used to reduce the adhesion force between graphene and copper. The combined methodology in CEIT ensures complete separation and clean transfer of graphene, resulting in successfully transferred graphene to various substrates, including polydimethylsiloxane (PDMS), Teflon, and C4F8 without pollution. The graphene obtained via CEIT is utilized to fabricate field‐effect transistors with electrical performances comparable to that of intrinsic graphene characterized by small Dirac points and high carrier mobility. The carrier mobility of the transferred graphene reaches 9090 cm2 V−1 s−1, demonstrating a superior carrier mobility over that from other dry transfer methods. In a nutshell, the proposed clean and efficient transfer method holds great potential for future applications of graphene. [ABSTRACT FROM AUTHOR]

The rapidly evolving communication field demands higher data capacity, faster transmission speeds, and improved anti-interference capabilities. However, the physical limitations of silicon-based photonics technology hinder the realization of photodetectors and other active devices. The discovery of two-dimensional (2D) materials, such as graphene, has opened promising opportunities for on-chip photodetection, showcasing distinctive physical and chemical properties and ultrathin nature. In this review, we first describe several representative 2D materials, including graphene, black phosphorus, and transition metal dichalcogenides (TMDCs). These materials offer diverse band structures and properties, presenting a plethora of options for varied applications. Then we highlight the utilization of these 2D materials in the development of high-performance photodetection devices, including photodiodes, field-effect transistors, and photodetectors. Furthermore, we delve into the practical applications of photodetectors, including room-temperature imaging, visual sensors, spectrometers, ranging, and other optoelectronic integrated systems. These real-world applications vividly demonstrate the versatility and potential of 2D materials across diverse fields. Overall, the unique structures and properties of 2D materials offer new possibilities for applications across various domains. Future research should be devoted to further explore the properties and applications of 2D materials to advance their development in the field of science and technology. [ABSTRACT FROM AUTHOR]

Photodetectors are essential optoelectronic devices that play a critical role in modern technology by converting optical signals into electrical signals, which are one of the most important sensors of the informational devices in current 'Internet of Things' era. Two-dimensional (2D) material-based photodetectors have excellent performance, simple design and effortless fabrication processes, as well as enormous potential for fabricating highly integrated and efficient optoelectronic devices, which has attracted extensive research attention in recent years. The introduction of spontaneous polarization ferroelectric materials further enhances the performance of 2D photodetectors, moreover, companying with the reduction of power consumption. This article reviews the recent advances of materials, devices in ferroelectric-modulated photodetectors. This review starts with the introduce of the basic terms and concepts of the photodetector and various ferroelectric materials applied in 2D photodetectors, then presents a variety of typical device structures, fundamental mechanisms and potential applications under ferroelectric polarization modulation. Finally, we summarize the leading challenges currently confronting ferroelectric-modulated photodetectors and outline their future perspectives. [ABSTRACT FROM AUTHOR]