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A true random number generator (TRNG) using Digital clock manager (DCM) blocks of a Xilinx FPGA has advantages of minimal usage of logic elements and tunability of clock frequencies to search for better randomness. Its operating principle is beat frequency detection, which uses the least significant bits (LSBs) of a counter that counts the number of successive logic-ones captured by a D flip-flop. In this brief, we evaluate the DCM-based TRNG with 100 frequency pairs. The findings of this brief include: 1) only 12 frequency pairs passed the diehard statistical tests when three LSBs were extracted as directed in the previous work; 2) the value of the counter exhibits biphasic histograms; 3) small counter values show less uncertainty; and 4) the number of frequency pairs that passed the tests was doubled to 24 by extracting only one LSB from small counter values, with a 16.9% reduction in the generation rate.

In the practical ASIC and SOC designs the multiple clocks are used and the designs are called as multiple clock domain designs. These kinds of designs need to be described using the efficient design architectures and Verilog RTL. This chapter focuses in the key design techniques which are used to describe the multiple clock domain designs while passing data from one of the clock domain to other. The chapter key highlights are the detail description for the synchronizers, data path, and control path synchronization logic using the efficient Verilog RTL. This chapter also discusses on the key design challenges in the multiple clock domain designs and even this chapter focuses on the design guidelines to describe the efficient clock domain designs.

The realization of power electronic applications on hardware is a challenging task. The digital control circuit strategies are used to overcome the analog control strategies by providing great flexibility with simple equipment and higher switching frequencies. In this manuscript, an area optimized, modified digital space vector (DSV) pulse width modulation is designed and realized on low-cost FPGA. The modified digital space vector pulse width modulation (DSVPWM) uses a phase-locked loop (PLL) to generate clocks using the digital clock manager (DCM). These DCM clocks are used in the DSVPWM module to synchronize the other sub-modules. The voltage generation unit generates the three-phase (3-Ф) voltages and is used in the alpha-beta generation and sector determination unit. The reference active vectors are made by the reference generation unit and used in switching time calculation. The PWM pulses are generated using switching time generation, and lastly, the dead time occurrence unit generates the final SVPWM gate pulses. The modified DSVPWM is synthesized and implemented on Spartan-3E FPGA. The modified DSVPWM utilizes 17% slices, works at 102.45 MHz, and consumes 0.070 W total power. The simulation results and the resource utilization of modified DSVPWM are represented in detail. The modified DSVPWM is compared with existing PWM approaches on different Spartan-series FPGAs with better chip area improvement

This brief presents a random number generator (RNG) based on irregular sampling of regular waveform method where the irregular signal is obtained by combining Fibonacci-Galois ring oscillators with an XOR gate. The RNG is implemented on a FPGA (field-programmable gate array). The regular waveform generated by the digital clock manager of the FPGA, is sampled at times corresponding to certain number of rising edges of the irregular signal, and the resulting bit stream is subjected to statistical tests of randomness. It is demonstrated that the resulting bit sequence from the proposed RNG satisfies NIST 800–22 test suit and Rabbit and SmallCrush batteries from TestU01 library without any need for post-processing such as Von Neumann or XOR. A comparison between the methods regular sampling of irregular waveform and irregular sampling of regular waveform is given in terms of robustness against external interference. The impact of selection of Fibonacci-Galois polynomials is discussed. Using digital design flow for TSMC 65nm process, an asic implementation of the proposed RNG is given having 1115 gates and 4.811 mW estimated power.

The modern cryptographic systems demand a random number generator to be of low-complexity and also be undeterminable simultaneously. The applications range from key generation, random padding bits, PIN/password generation, authentication protocols, and nonce generation. This paper introduces a new hybrid method that uses jitter as the randomness source. The proposed design incorporates a Ring Oscillators with Programmable Delay Lines and a Digital clock manager. Reduction in the correlation between the equal length ring oscillators is achieved by programmable delay lines and the Digital Clock Manager allows on-the-fly tunability which eventually enhances the randomness quality. A Von Neumann corrector is employed as a post-processor to eliminate any bias if present in the output bitstream and further improves the quality of randomness. The proposed TRNG achieves high throughput and low hardware footprint with a minimum cost of hardware. An analysis of the National Institute of Standards and Technology (NIST) tests demonstrates the effectiveness of the proposed architecture.

International audience; Lightweight ciphers such as ASCON facilitate ease of implementation as well as provide better performance over conventional ciphers, thus making it suitable for resource-constrained devices. However, hardware implementations of these ciphers are vulnerable to a multitude of physical attacks (such as fault injections) requiring dedicated countermeasures thus causing a negative impact on security, performance and power consumption. Modeling and understanding the impact of these attacks on cipher operations and end users is mandatory. Further, detection and mitigation of such fault injection attacks is challenging due to the interconnected nature of cipher design, coupled with the varying number of possible design choices and with the forced trade-offs that need to be done in order to implement expensive countermeasures at the lowest possible cost. In this work, we aim to model a fault injection attack on ASCON and analyze its impact on FPGA. In particular, we implement the ASCON cipher and propose a methodology for fault injection attacks using synchronous clock glitching by Digital Clock Manager (DCM) introducing a novel approach of locality, which can be exploited to emulate general delay faults on focused parts of the design, such those induced by pulsed EM injections.

In recent years, digital pulse width modulator (DPWM) has been widely used in the fields of electronic engineering, such as power converters, digital radar systems, control systems etc. High-resolution DPWM signal is simulated on ISE (Integrated Synthesis Environment) Design Suite 14.5 using two different approaches and a modified method. The first approach is based on Digital Clock Manager (DCM) module, which provides more stability than the RS latch utilized in previous work. As for the second method, look-up-table (LUT) is employed as the basic resources to construct high resolution DPWM signal. This can be easily implemented on low-cost FPGA devices because of the significantly simplified structure. The resolutions of two approaches can reach upto 625ps and 500ps respectively. In modified method, the resolution of DPWM signal can reach upto 1250ps.

This brief presents a random number generator (RNG) based on irregular sampling of regular waveform method where the irregular signal is obtained by combining Fibonacci-Galois ring oscillators with an XOR gate. The RNG is implemented on a FPGA (field-programmable gate array). The regular waveform generated by the digital clock manager of the FPGA, is sampled at times corresponding to certain number of rising edges of the irregular signal, and the resulting bit stream is subjected to statistical tests of randomness. It is demonstrated that the resulting bit sequence from the proposed RNG satisfies NIST 800-22 test suit and Rabbit and SmallCrush batteries from TestU01 library without any need for post-processing such as Von Neumann or XOR. A comparison between the methods regular sampling of irregular waveform and irregular sampling of regular waveform is given in terms of robustness against external interference. The impact of selection of Fibonacci-Galois polynomials is discussed. Using digital design flow for TSMC 65nm process, an asic implementation of the proposed RNG is given having 1115 gates and 4.811 mW estimated power.

This research proposes a scheme of field programmable gate array (FPGA) to generate an impulse-radio ultra-wideband (IR-UWB) pulse. The FPGA scheme consists of three parts: digital clock manager, four-delay-paths stratagem, and edge combiner. The IR-UWB radar system is designed to detect human subjects from their respiration underneath the rubble in the aftermath of an earthquake and to locate the human subjects based on range estimation. The proposed IR-UWB radar system is experimented with human subjects lying underneath layers of stacked clay bricks in supine and prone position. The results reveal that the IR-UWB radar system achieves a pulse duration of 540 ps with a bandwidth of 2.073 GHz (fractional bandwidth of 1.797). In addition, the IR-UWB technology can detect human subjects underneath the rubble from respiration and identify the location of human subjects by range estimation. The novelty of this research lies in the use of the FPGA scheme to achieve an IR-UWB pulse with a 2.073 GHz (117 MHz&ndash, 2.19 GHz) bandwidth, thereby rendering the technology suitable for a wide range of applications, in addition to through-obstacle detection.

Significant efforts are required for protection of cryptographic implementation in hostile environment, adversary injects fault in the cryptosystem by varying supply voltage, clock glitch and obser...

This paper establishes a fundamental theory of secure clock synchronization. Accurate clock synchronization is the backbone of systems managing power distribution, financial transactions, telecommunication operations, database services, etc. Some clock synchronization (time transfer) systems, such as the Global Navigation Satellite Systems (GNSS), are based on one-way communication from a master to a slave clock. Others, such as the Network Transport Protocol (NTP), and the IEEE 1588 Precision Time Protocol (PTP), involve two-way communication between the master and slave. This paper shows that all one-way time transfer protocols are vulnerable to replay attacks that can potentially compromise timing information. A set of conditions for secure two-way clock synchronization is proposed and proved to be necessary and sufficient. It is shown that IEEE 1588 PTP, although a two-way synchronization protocol, is not compliant with these conditions, and is therefore insecure. Requirements for secure IEEE 1588 PTP are proposed, and a second example protocol is offered to illustrate the range of compliant systems., 14 pages, 9 figures, accepted for publication in IEEE Journal of Selected Topics in Signal Processing

This paper introduces a 128 bit Tunable genuine Random number generator for cryptographic applications. In this, Digital clock supervisor (DCM), Dynamic incomplete reconfiguration (DPR), Beat Frequency Detection (BFD)—TRNG (True irregular number generator) methods were utilized. Cryptographic computations can be executed on Field Programmable Gate Arrays (FPGAs). In this work a True Random Number Generator (TRNG) used for cryptography application is proposed. The current work relies upon ring oscillators. The proposed work relies upon standard of Beat Frequency Detection (BFD). To the deficiencies and Jitter from the oscillators being the hotspot for the arbitrariness, we proposed an enhanced BFD—TRNG setup fitting for FPGA based applications. This work is finished by utilizing Xilinx programming.

This paper studies the impact of clock mismatches and quantization on networked control systems. We consider a scenario where the plant's state is measured by a sensor that communicates with the controller through a network. Variable communication delays and clock jitter do not permit a perfect synchronization between the clocks of the sensor and controller. We investigate limitations on the clock offset tolerable for stabilization of the feedback system. For a process with a scalar-valued state, we show that there exists a tight bound on the offset above which the closed-loop system cannot be stabilized with any causal controllers. For higher dimensional plants, if the plant has two distinct poles, then the effect of clock mismatches can be canceled with a finite number of measurements, and hence there is no fundamental limitation. We also consider the case where the measurements are subject to quantization in addition to clock mismatches. For first-order plants, we present necessary conditions and sufficient conditions for stabilizability, which show that a larger clock offset requires a finer quantization.

This paper introduces a new concept of a true random number generator (TRNG) based on two stages of randomness. The first stage is based on a novel chaotic circuit, which utilizes time as a continuous random variable in a feedback loop. The second stage is based on metastability; however, in contrast to known digital solutions, a flip-flop is stimulated by chaotic initial conditions. The advantage of chaotic behavior is the circuit’s immunity to active injection side-channel attacks (e.g., a frequency attack). The circuit design parameters can also vary in a wide range, which makes the TRNG insensitive to process, voltage and temperature (PVT) conditions and tolerance. Moreover, the design is extremely simplified, and therefore, feasible to implement in simple and inexpensive reprogrammable devices (no digital clock manager, programmable delay line, or phase locked loop are required). The TRNG ensures a constant (synchronous) 1-Mb/s bit rate output without additional post-processing. The randomness tests prove a high quality of an output bit stream, which is relatively high when compared with other solutions based on similar hardware resources.

In this research, we propose the Clock Synchronization by Least Common Multiple (CSLCM) method to remove the clock offset and clock skew among the sensor nodes. The proposed CSLCM enables the nodes to reach a network synchronization time by calculating the least common multiple of their Clock Time Period (CTP). The network is organized into clusters and every node reaches the network synchronization time using its own CTP. Simulation results show that, the CSLCM algorithm is more efficient compared to the Average Time Synchronization with Pairwise messages (ATSP) in terms of accuracy, communication overhead, and computation overhead.

By demanding authentication exercises for example communications, electronic cash frameworks, plate encryption, the cryptographic frameworks have become a core aspect in our daily lives. Random numbers are an significant factor in strengthening and anchoring the protection of e-mail messages used in multiple encryption applications, including key ages, encryption, convention coverage, web wagering. Random flight numbers for basic mystery keys are basic to the protection of criphotographical calculations. In a variety of cryptographic systems, actual random number generators (TRNGs), The part has been incorporated, including PIN / secret word age, validation agreements, key age, random cushions and age of nunce. The circuit uses an undetermined random mechanism as a fundamental source, largely as electric commotion. Programmable field door arrays (FPGAs) are the optimal stage for the success of equipment that offers substantial safety conditions. The TRNG suggested is subject to the Xilinx-FPGA Bit Recurrence Recognition Guideline.

In the paradigm of stochastic computing, arithmetic functions are computed on randomized bit streams. The method naturally and effectively tolerates very high clock skew. Exploiting this advantage, this paper introduces polysynchronous clocking, a design strategy in which clock domains are split at a very fine level. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock distribution network can be relaxed. This allows for a higher working frequency and so lower latency. The benefits of both approaches are quantified. Polysynchronous clocking results in significant latency, area, and energy savings for wide variety of applications.

This paper proposes an integrated shift register circuit for an in-cell touch panel that is robust over clock noises. It is composed of 10 thin film transistors and 1 capacitor, and the time division driving method is adopted to prevent the negative effect of display signals on the touch sensing. Two pre-charging nodes are employed for reducing the uniformity degradation of gate pulses over time. In particular, the proposed circuit connects a drain of the first pre-charging node's pull-up thin film transistor (TFT) to the positive supply voltage instead of clock signals. This facilitates to lower coupling noises as well as to clock power consumption. The simulation program with an integrated circuit emphasis is conducted for the proposed circuit with low temperature poly-silicon TFTs. The positive threshold voltage that shifts up to 12 V at the first pre-charging pull-up TFT can be compensated for without the uniformity degradation of gate pulses. For a 60-Hz full-HD display with a 120-Hz reporting rate of touches, the clock power consumption of the proposed gate driver circuit is estimated as 7.13 mW with 160 stages of shift registers. In addition, the noise level at the first pre-charging node is lowered to −28.95 dB compared with 2.37 dB of the previous circuit.

The Internet of Things is a trending future technological revolution that emerging distributed computing and real-time based application and its development depends on dynamic technical innovation in a number of important fields from wireless sensors to nanotechnology. Cloud integration with IoT made things more convenient and easy. Clock synchronization between systems in a distributed network is the complex and tedious job. It is mandatory to get sync with other and source as well. There are many proposed ways of data synchronization protocols like NTP, global position system to maintain sync process between Systems or IoT devices network. In this paper, we are proposing a clock synchronization approach to sync clocks between IoTs and Cloud which are connected with each other in distributed network. Here we have used cloud service Software as a Service to collect the information to analysis and trigger the results action to IoTs. In this paper, we present the Clock Synchronization based on precision time protocol between IoTs simulation model for Omnet++ with INET framework, which allows us to check clock sync accuracy with a different network configured topologies. We have tried to minimize the clock drift with clock offset updating and with master–slave phenomena also minimize the master–slave delay. To show our simulation results we have used chunks nodes of IoTs in distributed manner placed in different places with different clock values. The simulation result shows that proposed approach works in the desired manner within ideal and network delay symmetry.

High-performance architectures are over-provisioned with resources to extract the maximum achievable performance out of applications. Two sources of avoidable power dissipation are the leakage power from underutilized resources, along with clock power from the clock hierarchy that feeds these resources. Most reconfiguration mechanisms either focus solely on power gating execution resources alone or in addition, simply turn off the immediate clock tree segment which supplied the clock to those resources. These proposals neither attempt to gate further up the clock hierarchy nor do they involve the clock hierarchy in influencing the reconfiguration decisions. The primary contribution of CHARSTAR is optimizing reconfiguration mechanisms to become clock hierarchy aware. Resource gating decisions are cognizant of the power consumed by each node in the clock hierarchy and additionally, entire branches of the clock tree are greedily shut down whenever possible. The CHARSTAR design is further optimized for balanced spatio-temporal reconfiguration and also enables efficient joint control of resource and frequency scaling. The proposal is implemented by leveraging the inherent advantages of spatial architectures, utilizing a control mechanism driven by a lightweight offline trained neural predictor. CHARSTAR, when deployed on the CRIB tiled microarchitecture, improves processor energy efficiency by 20-25%, with efficiency improvements of roughly 2x in comparison to a naive power gating mechanism. Alternatively, it improves performance by 10-20% under varying power and energy constraints.

Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. In this work, we introduce a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF). The merit of LC-MBFF is that the logically constituent 1-bit flip-flops in LC-MBFF can be physically apart (i.e., no relocation), providing no need to set aside white space. Utilizing LC-MBFFs, we propose a multi-bit flip-flop allocation algorithm which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption. Experimental results with ISCAS89 and IWLS2005 benchmark circuits show that our proposed allocation algorithm using the newly designed multi-bit flip-flops is able to reduce on average the clock power by 8.51% while the best known multi-bit flip-flop allocation algorithm [7] reduces by 5.37%. Additionally, we extend our algorithm to support the multi-bit flip-flop allocation for circuits with clock polarity assignment.

This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm2 in a 65-nm CMOS technology.

Time synchronization is crucial for wireless sensor networks (WSNs) since it maintains data consistency, coordination, and enables other fundamental operations. Over the last decade, a number of powerful time synchronization algorithms have been proposed for clock accuracy optimization by using signal processing techniques. However, most of these algorithms attempt to estimate the clock phase offset and skew and do not correct the node's local clock at every timing packet exchange before the clock parameters are jointly estimated, which reduces the network synchronization accuracy during the estimation of clock parameters and limits the applicability of the synchronization algorithms for some practical sensor networks where a global time scale is consistently required. Motivated by this, this paper investigates the synchronization scheme of having inactive nodes overhearing the pairwise sender-receiver time synchronization based on acknowledgement with clock correction at every synchronization. Assuming exponential random delays, the maximum likelihood estimators (MLEs) of clock skew and the corresponding approximate Cramer-Rao lower bounds (CRLBs) for active and overhearing nodes are derived. In addition, we also consider a linear synchronization model that the clock skew is directly estimated. Simulation results verify the efficiency of the clock skew estimators.

We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees’ dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock activities when the modules in these tree branches are inactive. While this clock gating technique has been extensively studied in 2D circuits, its application in 3D-ICs is unclear. In 3D-ICs, a shutdown gate is connected to a control signal unit through control TSVs, which may cause placement conflicts with existing clock TSVs in the layout due to TSV’s large physical dimension. We develop a two-phase clock tree synthesis design flow for 3D-ICs: (1) 3D abstract clock tree generation based on K-means clustering and (2) clock tree embedding with simultaneous shutdown gates’ insertion based on simulated annealing (SA) and a force-directed TSV placer. Experimental results indicate that (1) the K-means clustering heuristic significantly reduces the clock power by clustering modules with similar switching behavior and close proximity, and (2) the SA algorithm effectively inserts the shutdown gates to a 3D clock tree, while considering control TSV’s placement. Compared with previous 3D clock tree synthesis techniques, our K-means clustering-based approach achieves larger reduction in clock tree power consumption while ensuring zero clock skew.

Time synchronization plays an important role in the spacecraft formation flight and constellation autonomous navigation, etc. For the application of clock synchronization in a network system, it is not always true that all the observed nodes in the network are interconnected, therefore, it is difficult to achieve the high-precision time synchronization of a network system in the condition that a certain node can only obtain the measurement information of clock from a single neighboring node, but cannot obtain it from other nodes. Aiming at this problem, a novel method of high-precision time synchronization in a network system is proposed. In this paper, each clock is regarded as a node in the network system, and based on the definition of different topological structures of a distributed system, the three control algorithms of time synchronization under the following three cases are designed: without a master clock (reference clock), with a master clock (reference clock), and with a fixed communication delay in the network system. And the validity of the designed clock synchronization protocol is proved by both stability analysis and numerical simulation.

In a high-performance VLSI design, the clock network consumes a significant amount of power. While most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous amount of dynamic power to charge/discharge the large global clock capacitance. New circuit approaches for current-mode (CM) clocking save significant clock power, but have been limited to only symmetric networks, while most application specific integrated circuits have asymmetric clock distributions. In this paper, we propose the first CM clock synthesis (CMCS) methodology to reduce the overall clock network power with low skew. The method can integrate with traditional clock routing followed by transmitter and receiver sizing. We validate the proposed methodology using ISPD 2009 and 2010 industrial benchmarks using an extracted SPICE model distributed in 1.4–275.6-mm2 area and consists of 81–2249 sinks. This methodology saves 39%–84% average power with similar skew on the benchmarks using 45-nm CMOS technology simulation of clock frequencies range from 1–3 GHz. In addition, the CMCS methodology takes $2.4-9.1\times $ less running time and consumes 20%–26% less transistor area compared with synthesized, buffered VM clock distributions.

Clock trees, which deliver the clock signal to every clock sink in the whole system, switch actively at high frequency, which makes them one of the most dominant sources of noise. While many clock polarity assignment (PA) techniques were proposed to mitigate the clock noise, no attention has been paid to the PA under useful skew constraints. In this work, we show that the clock PA problem under useful skew constraints is intractable and propose a comprehensive and scalable clique search based algorithm to solve the problem effectively. In addition, we demonstrate the applicability of our solution by extending it for PA under delay variation environment. Through experiments with ISPD'10 benchmark circuits, we show that our proposed clock PA algorithm is able to reduce the peak noise by 10.9% further over that of the conventional global skew bound constrained PA. Finally, we compare our PA technique against decoupling capacitor embedding technique which is a commonly used method for noise reduction. HighlightsWe propose a clock buffer polarity assignment algorithm under useful clock skew constraints that enables the consideration of individual setup and hold time constraints for the reduction of power and ground noise emitted by the clock trees.We prove that the polarity assignment under useful clock skews is intractable.A heuristic framework that is able to trade-off between the quality of solution and run-time is proposed.

Timestamp free clock synchronization in a master–slave network, i.e., synchronization where no timestamps are exchanged between the nodes, is considered. For highly accurate synchronization, a novel discrete-valued clock model is introduced. It is based on the observation that clocks are discrete counters in digital wireless radios. Considering this model, it is shown that the round-trip time (RTT) measurements follow specific pulse or step shaped functions. The estimated parameters of these RTT functions are used to determine the clock parameters (clock skew and phase) and the propagation delay. Numerical analysis illustrate that when RTT measurements are collected using discrete-valued clocks, the proposed estimation schemes outperform estimators derived from the continuous clock model, which is used in the state-of-the-art methods. Moreover, the presented scheme performs similar to recently presented discrete-valued clock approaches with more stringent hardware assumption. The correctness of the proposed models is validated through hardware experiments.

A simple circuit for duty-cycle correction is proposed in this paper. The configuration is flexible consisting of only three CMOS inverters in a feedback loop. It does not require any reference signal and, therefore, it can be used as a standalone circuit, while it can be applied on a single-ended clock path without breaking the clock line. Simulation results in a 65 nm CMOS technology and 1 V supply voltage give a duty-cycle error less than 1% for a duty-cycle input clock variation between 30 and 70% with a frequency range from 2.4 to 2.9 GHz.

With the application of internet in manufacturing, motion control system is tend to networking. Clock synchronization is a basic requirement to guarantee capability of coordination in networked motion control systems. In this paper, we propose a frequency-tracking clock servo (FTCS) to adjust the local clock to synchronize with the reference clock. The frequency of FTCS can rapidly lock onto the reference frequency and the offset can be fully compensated within a single synchronizing cycle. Simulations and experiments are performed to validate the feasibility and superiority of FTCS. Compared with the proportional-integral clock servo, FTCS can achieve the rapid synchronized speed and better precision with low frequency of sending synchronization messages.

Clocking of electrical circuit is a crucial issue since clock signal is used to establish the flow-of-time inside electronic world. Before, during and after the "Moore's law", flow-of-time is an eternal issue. Alongside processor, memory/storage and analog/ RF technologies, IC clocking could be regarded as the 4th major IC design technology. In the past several decades, clock is mostly used in the form of fixed-frequency with high frequency stability. For future system, however, this type of clock signal is not sufficient because its usage environment is not expected to be stationary but dynamic. To meet this challenge, innovation in IC clocking is required. This paper first discusses the difficulties in creating flow-of-time; then the two long-lasting problems in clock generation are identified, and then new challenges in the design of future system are summarized. Afterwards, the Time-Average-Frequency based flexible clock generator is introduced and its potential to confront these challenges is addressed. Several major issues in modern design are discussed. The paper concludes with a vision that, for electronic system to improve its information processing efficiency to next level, clock technology is the next frontier to be explored.

Clock networks are required to be constructed with adequate safety margins in the skew constraints to operate correctly even under the influence of variations. In this work, a scalable clock scheduler is developed to drive a synthesis framework that constructs useful skew clock trees with large safety margins that are tailored to the tree topology. Sequential elements are clustered early in the topology, if it is impossible provide adequate robustness to variations using only safety margins. Compared to earlier studies, the proposed framework performs the clock scheduling one to two orders of magnitude faster and improves yield and capacitive cost on several synthesized circuits.

The work solves a new problem of optimizing the boundary of buffered clock trees, which has not been addressed in the design automation as yet. Precisely, we want to show that the clock cells that directly drive flip-flops should not necessarily be buffers. By taking into account the internal structure of flip-flops, we can have a freedom of choosing either buffers or inverters for the cell implementation from library. This in fact leads to cancel out the two inverters, one in the driving buffer and another in each flip-flop, thereby reducing the power consumption on the clock tree, including flip-flops. We generalize this idea to look into the possibility of co-optimizing the driving buffers and flip-flops together to reduce the clock power at the boundary of clock trees, and propose an effective four-step synthesis algorithm of clock tree boundary for low power. By applying our proposed technique to benchmark circuits, it is observed that the clock power is able to be reduced by 4.45 % ~ 6.33 % further on average without timing violation.

Time synchronization is extremely important for wireless sensor networks (WSNs). For large-scale WSNs, hierarchical clock synchronization, which can effectively save energy by reducing communication overhead, has become an attractive approach in practical networks. Based on the hierarchical network, in this paper, we present a global clock skew estimation scheme with immediate clock adjustment. The maximum likelihood estimator and corresponding Cramer–Rao lower bound of the clock skew are derived under the Gaussian delay model, and the simulation results verify that the proposed method is efficient.

This paper suggests a simple method to solve the clock skew problem generated on two or several separate chips when voltage difference, or gradient, occurs between/among the chips. Generation and distribution of clock signals with minimum skews becomes a critical factor in overall system performance in today’s GHz operation speed. With a few connection lines, similar to Data Bus, between two chips, named CBL (Clock Bus Line), a multi-chip synchronization method is newly proposed and proved through simulations and TTL chip measurements. With 2% of supplied voltage differences in different chips, within 3% of the period clock skew is guaranteed in this new scheme. A feasible way of implementation of this CBL method in today’s integrated circuits is also described along with CMOS layout.

The present invention discloses a method for synchronizing a clock signal which designs a ring oscillator with a stable fractal structure. The method for synchronizing a clock signal comprises the following steps of: receiving a voltage source from a first chip generating a first clock signal and a second chip generating a second clock signal; oscillating the first clock signal and the second clock signal in a clock line located between the first chip and the second chip; and outputting the first clock signal and the second clock signal as the clock signal having the same frequency and the same phase. The clock line connects three ends of the first chip and the second chip having the same fractal structure.

Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work. . The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of thedesign. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fundamental functional blocks of the processor include Input/Output blocks, configurable logic blocks, Block RAM, and Digital clock Manager and each block permits to connect to multiple sources for the routing. The Auxiliary units enhance the performance of the processor. The comparative study elevates the designed model in terms of Area, Power and Frequency. MATLAB2D/3D graphs represents the relationship among various parameters of this pipelining. In this pipeline model, it consumes very less power (0.129 W),path delay (11.180 ns) and low LUT utilization (421). Similarly, the proposed model achieves better frequency increase (285.583 Mhz.), which obtained better results compared to other models.

The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.

This paper presents the analysis of random number generators(RNGs) based on regular sampling of irregular waveform method where the irregular signal is obtained from the oscillations of combined Fibonacci and Galois ring oscillators. As the proposed random number generator is made up of logic gates only, it is implemented on a FPGA (field-programmable gate array). The regular waveform generated by the digital clock manager of the FPGA is used for sampling the irregular signal and the resulting bit stream is uploaded to a computer where it is subjected to standard statistical test. The polynomials defining the Fibonacci and Galois ring oscillators are varied to assess the relationship between the polynomial and the randomness of the output bit stream. It is demonstrated that for both polynomial functions, by combining enough number of oscillator structures, the output bit streams from each RNG satisfy standard statistical tests without post processing. To the best of our knowledge, this paper presents the first comparative study on the impact of polynomials on random number generators based on Fibonacci and Galois ring oscillators.

Due to constraints of cost and size for mobile devices, a digital self-synchronous OFDM receiver is preferable in mobile applications since it only requires economical crystal oscillators plus free-running analog front-end circuits. However, there are more stringent requirements for clock timing recovery tasks in such a self-synchronous receiver. This paper presents an efficient and robust clock timing recovery scheme for the digital self-synchronous OFDM receiver. It is based on the canonical Gardner structure, but new techniques are devised for performance improvement. A joint iterative estimation algorithm is used for error detection, which can not only improve the detection precision, but also maintain the loop's dynamic performance. A direct control method based on a simple dynamic delay technique instead of the numerical-controlled oscillator mechanism is adopted to smoothly adjust the timing recovery by adaptively performing asynchronous resampling on the discrete sequence of the received signal. Theoretical analysis and numerical simulation results are also presented to verify the effectiveness of the proposed clock timing recovery scheme and conduct performance analysis and evaluation.

A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: 1) a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the entire clock network and 2) a novel clock tree synthesis algorithm to ensure that the same timing constraints (i.e., clock frequency, skew, and slew) are satisfied. The proposed methodology is integrated within an industrial design flow. Experimental results on ISCAS’89 benchmark circuits demonstrate that the overall power consumed by the clock tree can be reduced by up to 27% and 44% in, respectively, 32- and 45-nm technologies while satisfying the same timing constraints. Furthermore, the proposed low-swing DFF cell maintains the clock-to-Q delay the same while achieving up to 32% and 15% power savings in the overall flip-flop power of the benchmark circuits at, respectively, 1- and 1.5-GHz clock frequencies.

EtherCAT has been widely applied in the motion control domain due to its advantages of the fast response speed, low CPU usage and good synchronization performance. Although the built-in distributed clock (DC) synchronization mechanism exhibits strong performance between slaves, the method of clock synchronization between the master and the reference clock is left open for selection by users and there are very few studies in this area. This paper introduces three synchronization modes for EtherCAT and analyzes the reasons for packet loss in free run mode and DC mode. This paper presents a novel method to realize the master clock synchronization with the reference clock. The proposed method can eliminate the settling time which is unusual in other synchronization mechanisms. The method is implemented on Windows with real-time extension and experimental results prove its feasibility.

We argue that grid structures are a very promising alternative to the standard approach for distributing a clock signal throughout VLSI circuits and other hardware devices. Traditionally, this is accomplished by a delay-balanced clock tree, which distributes the signal supplied by a single clock source via carefully engineered and buffered signal paths.Our approach, termed HEX, is based on a hexagonal grid with simple intermediate nodes, which both control the forwarding of clock ticks in the grid and supply them to nearby functional units. HEX is Byzantine fault-tolerant, in a way that scales with the grid size, self-stabilizing, and seamlessly integrates with multiple synchronized clock sources, as used in multi-synchronous Globally Synchronous Locally Asynchronous (GALS) architectures. Moreover, HEX guarantees a small clock skew between neighbors even for wire delays that are only moderately balanced. We provide both a theoretical analysis of the worst-case skew and simulation results that demonstrate very small typical skew in realistic runs.

dissipation is major drawback in the digital sequential circuit design of low power electronic devices. Clock signal is one input which is common for all the sequential circuits. The clock signal has major power dissipation at high frequencies. The clock gating technique can be implemented at architectural level to reduce the power dissipation at dynamic and clock power level. Aim of this paper is to analyze, implement and comparison between various clock gating techniques for a 8-bit ALU on a artix7,45 nm technology with xc7a100t-3csg324 , xc6slx41-1Ltqg144 spartan6 with 40nm FPGA board. The two clock gating techniques are proposed and used in the design are namely: T-flip flop and use of latch. This technique is implemented by using Xilinx 14.1. T flip flop is best for this design as it requires less number of gate counts and also less area. Operation using11 instructions are performed in the proposed design. This technique is designed through T Flip-Flop based on gated clock ALU at RTL level. At different operating frequencies of 100MHZ, 200MHZ, 300MHZ, 400MHZ & 500MHZ, the dissipated power is 5mw, 9mw, 14mw, 19mw,24mw respectively. Keywordscircuit, T-FF, Clock- Gating, Implementation