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CHARSTAR
- Source :
- ISCA
- Publication Year :
- 2017
- Publisher :
- Association for Computing Machinery (ACM), 2017.
-
Abstract
- High-performance architectures are over-provisioned with resources to extract the maximum achievable performance out of applications. Two sources of avoidable power dissipation are the leakage power from underutilized resources, along with clock power from the clock hierarchy that feeds these resources. Most reconfiguration mechanisms either focus solely on power gating execution resources alone or in addition, simply turn off the immediate clock tree segment which supplied the clock to those resources. These proposals neither attempt to gate further up the clock hierarchy nor do they involve the clock hierarchy in influencing the reconfiguration decisions. The primary contribution of CHARSTAR is optimizing reconfiguration mechanisms to become clock hierarchy aware. Resource gating decisions are cognizant of the power consumed by each node in the clock hierarchy and additionally, entire branches of the clock tree are greedily shut down whenever possible. The CHARSTAR design is further optimized for balanced spatio-temporal reconfiguration and also enables efficient joint control of resource and frequency scaling. The proposal is implemented by leveraging the inherent advantages of spatial architectures, utilizing a control mechanism driven by a lightweight offline trained neural predictor. CHARSTAR, when deployed on the CRIB tiled microarchitecture, improves processor energy efficiency by 20-25%, with efficiency improvements of roughly 2x in comparison to a naive power gating mechanism. Alternatively, it improves performance by 10-20% under varying power and energy constraints.
- Subjects :
- 010302 applied physics
Power gating
Computer science
Control reconfiguration
Clock gating
Digital clock manager
Gating
02 engineering and technology
General Medicine
Clock skew
01 natural sciences
Clock synchronization
Timing failure
Microarchitecture
020202 computer hardware & architecture
Computer architecture
Logic gate
0103 physical sciences
0202 electrical engineering, electronic engineering, information engineering
Frequency scaling
CPU multiplier
Subjects
Details
- ISSN :
- 01635964
- Volume :
- 45
- Database :
- OpenAIRE
- Journal :
- ACM SIGARCH Computer Architecture News
- Accession number :
- edsair.doi.dedup.....1a6485dda5c2838dd6f9ac71f9ac2d80