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Design Methodology for Voltage-Scaled Clock Distribution Networks
- Source :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:3080-3093
- Publication Year :
- 2016
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2016.
-
Abstract
- A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: 1) a novel D-flip-flop (DFF) cell that maximizes power savings by enabling low-voltage/swing operation throughout the entire clock network and 2) a novel clock tree synthesis algorithm to ensure that the same timing constraints (i.e., clock frequency, skew, and slew) are satisfied. The proposed methodology is integrated within an industrial design flow. Experimental results on ISCAS’89 benchmark circuits demonstrate that the overall power consumed by the clock tree can be reduced by up to 27% and 44% in, respectively, 32- and 45-nm technologies while satisfying the same timing constraints. Furthermore, the proposed low-swing DFF cell maintains the clock-to-Q delay the same while achieving up to 32% and 15% power savings in the overall flip-flop power of the benchmark circuits at, respectively, 1- and 1.5-GHz clock frequencies.
- Subjects :
- Synchronous circuit
Engineering
business.industry
Underclocking
020208 electrical & electronic engineering
Clock gating
Hardware_PERFORMANCEANDRELIABILITY
02 engineering and technology
Digital clock manager
Clock skew
020202 computer hardware & architecture
Clock network
Hardware and Architecture
Clock domain crossing
Hardware_INTEGRATEDCIRCUITS
0202 electrical engineering, electronic engineering, information engineering
Electronic engineering
Electrical and Electronic Engineering
business
Software
Hardware_LOGICDESIGN
CPU multiplier
Subjects
Details
- ISSN :
- 15579999 and 10638210
- Volume :
- 24
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Accession number :
- edsair.doi...........dd790ba576bfdc16509d7d996c7f6477