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© 2013 IEEE. After 50 years of Moore's Law, Si CMOS, the mainstream logic technology, is on a course of diminishing returns. The use of new semiconductor channel materials with improved transport properties over Si offer the potential for device scaling to nanometer dimensions and continued progress. Among new channel materials, III-V compound semiconductors are particularly promising. InGaAs is currently the most attractive candidate for future III-V based n-type MOSFETs while InGaSb is of great interest for p-channel MOSFETs. At the point of most likely deployment, devices based on these semiconductors will have a highly three-dimensional architecture. This paper reviews recent progress toward the development of nanoscale III-V MOSFETs based on InGaAs and InGaSb with emphasis on scalable technologies and device architectures and relevant physics. Progress in recent times has been brisk but much work remains to be done before III-V CMOS can become a reality.

We present a detailed study of the off-state leakage current in scaled self-aligned InGaAs FinFETs. In long-channel devices, band-to-band tunneling at the drain-end of the channel is shown to be the root cause of excessive off-state current. This conclusion emerges from its characteristic electric field and temperature behavior and the absence of gate length and fin width dependencies. In short-channel devices, off-state current is significantly larger and it increases as the gate length shortens or the fin widens. We attribute this behavior to current multiplication through the gain of a floating-base parasitic bipolar transistor that is present inside the MOSFET. We extract the bipolar current gain which in short-channel devices is found to increase as the gate length shortens and decrease as the fin width narrows. In long channel devices, the current gain drops exponentially due to base recombination. This has allowed us to extract the diffusion length of electrons in the body of the transistor., DTRA (Grant HDTRA1-14-1-0057), NSF (Grant 0959514)

We investigate time-dependent dielectric breakdown (TDDB) in AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs) under forward bias AC stress which better emulates real-world operational conditions. To this end, we have performed TDDB experiments across a wide range of frequencies, temperatures, and recovery voltage levels. We find that TDDB under AC stress shows longer breakdown times than under DC stress and that this increase is more prominent with higher frequency, lower temperature, and more negative recovery voltage. We hypothesize that this is due to the dynamics of the gate stack in GaN MIS-HEMTs biased with a high positive gate voltage. Under these conditions, a second electron channel forms at the dielectric/AlGaN interface. This process is relatively slow as these electrons come from the 2DEG at the AlGaN/GaN interface and must overcome the energy barrier presented by the AlGaN. At the same gate voltage then, the electric field across the gate oxide is lower in magnitude under AC stress at high enough frequency than under DC stress explaining the obtained results.

The electrical degradation of InAlN/GaN high-electron-mobility transistors for millimeter-wave applications has been examined under simultaneous high V [subscript DS,stress] and high I[subscript Dstress] electrical stress. Besides a drain current decrease and a positive threshold voltage shift, the creation of an anomalous source-side gate leakage path has been identified. We attribute this to high electric-field induced trap generation in the AlN layer directly under the gate edge on the source side. The resulting increase in gate leakage further exacerbates the degradation of the gate diode. In addition, we postulate that high-power stress leads to significant device self-heating that causes gate sinking and leads to a permanent positive threshold voltage shift and drain current degradation.

We have investigated time-dependent dielectric breakdown in high-voltage AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors, with a focus specifically on the role of temperature under positive gate stress conditions. We aim toward understanding the temperature dependence of progressive breakdown (PBD) as well as hard breakdown. We find that the temperature dependence of time-to-first breakdown, hard breakdown, and the gate current evolution during PBD all share similar, shallow activation energies that suggest a common underlying mechanism. However, the gate current noise during PBD seems to be independent of temperature and is likely due to a tunneling process. Understanding of temperature-dependent breakdown is essential to developing accurate device lifetime estimates.

This study comprehensively analyzed the reliability of trapping and hot-electron effects responsible for the dynamic on-resistance (Ron) of GaN-based metal–insulator–semiconductor high electron mobility transistors. Specifically, this study performed the following analyses. First, we developed the on-the-fly Ron measurement to analyze the effects of traps during stress. With this technique, the faster one (with a pulse period of 20 ms) can characterize the degradation; the transient behavior could be monitored accurately by such short measurement pulse. Then, dynamic Ron transients were investigated under different bias conditions, including combined off state stress conditions, back-gating stress conditions, and semi-on stress conditions, in separate investigations of surface- and buffer-, and hot-electron-related trapping effects. Finally, the experiments showed that the Ron increase in semi-on state is significantly correlated with the high drain voltage and relatively high current levels (compared with the off-state current), involving the injection of greater amount of hot electrons from the channel into the AlGaN/insulator interface and the GaN buffer. These findings provide a path for device engineering to clarify the possible origins for electron traps and to accelerate the development of emerging GaN technologies.

The single-event-transient response of InGaAs FinFETs with different fin widths is examined using pulsed-laser and heavy-ion irradiation. Devices with wider fins collect more charge in both environments. Quantum-well structures confine charge collection in the channel, and determine the sensitive volume. Simulations show that the charge density produced by irradiation is similar for devices with different fin widths, but more charge is collected by wider fin devices due to the larger channel volume. Charge accumulated in the buffer and substrate layers modulates the body potential, altering the degree of back-gate control, leading to additional effects associated with charge accumulation in wider fin devices. Optical simulations for a model system suggest that optical phenomena in the fins should be considered for laser testing. These include optical interference, plasmonic enhancement at the metal-dielectric interfaces, and enhanced electron-hole pair recombination due to multiple reflections in multigate devices with nanoscale dimensions.

This letter introduces a novel alcohol-based digital etch technique for III-V FinFET and nanowire MOSFET fabrication. The new technique addresses the limitations of the conventional water-based approach in enabling structures with sub-10-nm 3-D features. Using the same oxidation step, the new technique shows an etch rate of 1 nm/cycle, identical to the conventional approach. Sub-10 nm fins and nanowires with a high mechanical yield have been achieved. InGaAs nanowires with a diameter of 5 nm and an aspect ratio greater than 40 have been demonstrated. The new technique has also been successfully applied to InGaSb-based heterostructures, the first demonstration of digital etch in this material system. Vertical InGaAs nanowire gate-all-around MOSFETs with a subthreshold swing of 70 mV/decade at V DS = 50 mV have been obtained at a nanowire diameter of 40 nm, demonstrating the good interfacial quality that the new technique provides.

Schottky gate degradation of W-band InAlN/AlN/GaN high-electron-mobility transistors (HEMTs) has been studied under prolonged positive gate stress. Two different degradation mechanisms have been identified. In an early stage, a gate leakage current increase takes place without any observable drain current nor source and drain resistance degradation. We propose electric field induced trap generation in the AlN barrier layer as the cause. Under harsher gate stress, a second degradation mechanism kicks in where gate leakage current, as well as drain current and the source and drain resistances degrade significantly. We attribute this to Schottky barrier degradation due to severe local self-heating., National Reconnaissance Office (Contract DII NRO000-13C0309)

We present a comprehensive study of bias temperature instability (BTI) in GaN MOSFETs under moderate positive and negative gate bias stress. We investigate the evolution of threshold voltage (V T ), maximum transconductance (g m,max ), and subthreshold swing (S). Our results show a universal continuous, symmetrical, and reversible VT shift and gm,max change as gate stress voltage (VGS,stress) increases from -5 to 5V at room temperature. The time evolution of V T is well described by a power law model. The voltage dependence, time dependence, and temperature dependence of our results suggest that for moderate gate bias stress, positive BTI and negative BTI are due to a single reversible mechanism. This is electron trapping/detrapping in preexisting oxide traps that form a defect band very close to the GaN/oxide interface and extend in energy beyond the conduction band edge of GaN and below the Fermi level at the channel surface at 0 V.

A p-type Diamond:H/WO 3 metal-oxide-semiconductor field-effect transistor (MOSFET) based on surface transfer doping is demonstrated. Using a low-temperature ALD-grown HfO 2 as gate insulator, the Diamond:H/WO 3 MOSFETs show excellent output characteristics, gate-controllable 2-D hole gas, and low gate leakage current. Long-channel FETs exhibit improved subthreshold behavior but reduced transconductance with respect to short-channel devices. An observed WO 3 -thickness-dependent threshold voltage is consistent with enhanced surface transfer doping as the WO 3 layer is thinned down. Low-temperature measurements suggest a significantly lower mobility than expected in this material system. This illustrates the challenge of maintaining high TMO quality during device fabrication.

Recently, sub-10-nm-diameter InGaAs vertical nanowire (VNW) MOSFETs have been demonstrated. The key to this achievement was the use of Ni for the top ohmic contact. In this paper, we present a detailed study of the impact of Ni and Mo contacts on the electrical characteristics of highly scaled InGaAs VNW MOSFETs. Sequential annealing experiments are presented that reveal the optimum temperature for each type of contact. A negative temperature dependence of the ON-resistance of 7-nm-diameter Ni-contacted devices suggests the existence of an energy barrier. We also observe an unexpected transconductance and drain-induced barrier loweirng (DIBL) dependence on transistor diameter in Ni-contacted devices as well as abnormal DIBL asymmetry to swapping source and drain. All these results can be explained by Ni diffusing down the nanowire during the contact annealing process, reducing the effective channel length, and creating a Schottky-barrier drain.