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Artificial intelligence is used for various applications and is promising as an indispensable infrastructure in future societies. Neural networks are representative technologies that imitate human brains and exhibit various advantages. However, the size is bulky, the power is huge, and some advantages are not demonstrated because they are executed on Neumann-type computers. Neuromorphic systems are biomimetic systems from the hardware level to implement neuron and synapse elements, and the size is compact, the power is low, and the operation is robust. However, because the conventional ones are not composed of fully optimized hardware, the power is not yet minimal, and extra control circuits must be used. In this article, we developed a neuromorphic system using memcapacitors and autonomous local learning. By using memcapacitors, the power can be minimal, and by using autonomous local learning, the control circuits to handle the synapse elements can be deleted. First, the memcapacitors are completed in a cross-bar array, where the ferroelectric layers are sandwiched between the horizontal and perpendicular electrodes. The polarization and capacitance exhibit hysteresis due to the dielectric polarization. Next, autonomous local learning is introduced as follows. During the training phase, associative patterns to be memorized are directly sent, relatively high voltages are applied, and dielectric polarizations are induced. During the operation phase, relatively low voltages are applied, and input signals are weighted with the capacitances of the memcapacitors, summed, and transferred as the output signals. Finally, the experimental system is set up, and the experimental results are acquired. The memorized patterns during the training phase, distorted patterns as the input signals during the operation phase, and retrieved patterns as the output signals in the operation phase are shown. Researchers found that the retrieved patterns are completely the same as the memorized patterns. This means that the neuromorphic system works as an associative memory.

A spectrum of emerging applications including edge artificial intelligence advocate the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this paper. Based on novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in layout. An analytical model is also presented which allows us for a systematic investigation on the energy reduction by adapting our design to various pre-search structures. Validated on a post-layout 32W64 ternary CAM in 28nm, our parallel-matching scheme performs at 2.6GHz with 0.42fJ/bit/search, and the (8-bit) pre-search scheme achieves 0.19fJ/bit/search at 1.1GHz, both under the 0.9V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45V with a minimum energy consumption of 0.06fJ/bit/search at 50MHz.

Dynamic memristor (DM)-cellular neural networks (CNNs), which replace a linear resistor with flux-controlled memristor in the architecture of each cell of traditional CNNs, have attracted researchers' attention. Compared with common neural networks, the DM-CNNs have an outstanding merit: when a steady state is reached, all voltages, currents, and power consumption of DM-CNNs disappeared, in the meantime, the memristor can store the computation results by serving as nonvolatile memories. The previous study on stability of DM-CNNs rarely considered time delay, while delay is quite common and highly impacts the stability of the system. Thus, taking the time delay effect into consideration, we extend the original system to DM-D(delay)CNNs model. By using the Lyapunov method and the matrix theory, some new sufficient conditions for the global asymptotic stability and global exponential stability with a known convergence rate of DM-DCNNs are obtained. These criteria generalized some known conclusions and are easily verified. Moreover, we find DM-DCNNs have 3ⁿ equilibrium points (EPs) and 2ⁿ of them are locally asymptotically stable. These results are obtained via a given constitutive relation of memristor and the appropriate division of state space. Combine with these theoretical results, the applications of DM-DCNNs can be extended to other fields, such as associative memory, and its advantage can be used in a better way. Finally, numerical simulations are offered to illustrate the effectiveness of our theoretical results.

Age-related declines in associative memory are ubiquitous, having been observed across a wide array of stimuli and experimental paradigms. Research further shows that such decreases in behavioral discriminability arise from increases in false memories for recombined lures. The current study examined the underlying neural basis of associative false memories by using representational similarity analyses to examine both age differences in the reactivation of encoded representations during retrieval and the neural overlap in the similarity of neural patterns underlying targets and related lures during retrieval. Behaviorally, we observed an age-related reduction in d’, which was shown to be driven by increased false alarms in the older adults. While we found no age difference in the relationship between patterns of neural activity underlying hits across memory phases (as measured by ERS), the similarity of neural patterns underlying targets and lures was affected by age. Specifically, while younger and older adults exhibited overall higher pattern similarity between hits and CRs compared to hits and FAs (as measured by RSA), this difference was reduced in older adults within occipital cortices. Additionally, greater Hit-FA representational similarity correlated with increases in associative FAs across occipital, frontal, and parietal cortices. Results suggest that while neural representations underlying targets may not differ across age, greater pattern similarity between the neural representation of targets and lures may reflect reduced distinctiveness of the information encoded in memory, such that old and new items are more difficult to discriminate, leading to more false alarms.

In this work, we are interested in a class of Bi-directional associative memory neural networks (BAMNNs) with hybrid time-varying delays and D operator. We establish some sufficient conditions to guarantee the existence and global exponential stability of measure-pseudo almost periodic solutions of the considered BAMNNs, using contraction mapping principle, exponential dichotomy theory, differential inequality techniques, and the properties of the measure-pseudo almost periodic functions. A numerical example along with a graphical illustration are presented to support the effectiveness and fasibility of the obtained results. The results in this paper are original and complement the previous outcomes.

We tend to mentally segment a series of events according to perceptual contextual changes, such that items from a shared context are more strongly associated in memory than items from different contexts. It is also known that timing context provides a scaffold to structure experiences in memory, but its role in event segmentation has not been investigated. We adapted a previous paradigm, which was used to investigate event segmentation using visual contexts, to study the effects of changes in timing contexts on event segmentation in associative memory. In two experiments, we presented lists of 36 items in which the interstimulus intervals (ISIs) changed after a series of six items ranging between 0.5 and 4 s in 0.5 s steps. After each list, participants judged which one of two test items were shown first (temporal order judgment) for items that were either drawn from the same context (within an ISI) or from consecutive contexts (across ISIs). Further, participants judged from memory whether the ISI associated to an item lasted longer than a standard interval (2.25 s) that was not previously shown (temporal source memory). Experiment 2 further included a time-item encoding task. Results revealed an effect of timing context changes in temporal order judgments, with faster responses (Experiment 1) or higher accuracy (Experiment 2) when items were drawn from the same context, as opposed to items drawn from across contexts. Further, in both experiments, we found that participants were well able to provide temporal source memory judgments based on recalled durations. Finally, replicated across experiments, we found subjective duration bias, as estimated by psychometric curve fitting parameters of the recalled durations, correlated negatively with within-context temporal order judgments. These findings show that changes in timing context support event segmentation in associative memory.

We propose that the specificity with which associations in episodic memory can be remembered varies on a continuum. Older adults have been shown to forget highly specific information (Greene & Naveh-Benjamin, 2020b), and in Experiment 1, we provide further evidence that older adults' deficits in associative memory scale with the amount of specificity that needs to be retrieved. In Experiment 2, we address whether depleted attentional resources, simulated in young adults under divided attention at encoding, could account for older adults' associative memory specificity deficits. Participants studied face-scene pairs and later completed an associative recognition test, with test pairs that were old, highly similar or less similar to old pairs, or completely dissimilar. Participants rated their confidence in their decisions. False positive recognition responses increased with the amount of specificity needed to be retrieved. Whereas older adults' associative memory deficits scaled with how much specific information needed to be remembered, younger adults under divided attention had a more general deficit in associative memory. Confidence-accuracy analysis showed that participants were best able to calibrate their confidence when less specific information was needed to perform well. While divided attention young adults were generally prone to high-confidence errors, older adults' high-confidence errors were most apparent when highly specific information needed to be remembered. These results provide further evidence for levels of specificity in episodic memory. Access to the most specific levels is most vulnerable to forgetting, in line with a specificity principle of memory (Surprenant & Neath, 2009). Further, depleted attentional resources at encoding cannot entirely explain older adults' associative memory specificity deficits. (PsycInfo Database Record (c) 2021 APA, all rights reserved).

TCAM is widely used for rule tables in network switches. An efficient update scheme, which requires as few rule moves as possible, is often time-consuming to compute, while the fast computation likely yields a mediocre update scheme. We studied the existing algorithms and found none is satisfactory to the emerging applications. In this paper, we present a simple greedy algorithm, GreedyJump, which achieves fast computation and efficient update scheme at the same time, both with the best-in-class performance. The evaluation qualifies GreedyJump as the default TCAM update algorithm ready for meeting the scalability challenges in various application scenarios.

Content-addressable memory (CAM) is a massively parallel searching device that returns the address of a given search input in one clock cycle. Field-programmable gate array (FPGA)-based CAMs are becoming popular due to their applications in the latest networking systems, e.g., software-defined networks (SDNs) leading to upcoming 5G networks. Ternary CAM (TCAM) implements a routing table in a network router to classify and forward data packets where don’t care bits (X-bits) correspond to multiple addresses. FPGAs do not have a hard-core CAM, although it is a prime element in networking applications. This paper serves as a comprehensive survey on FPGA-based CAM/TCAMs implemented using block random-access memory (BRAM), lookup table RAM (LUTRAM), and flip-flops (FFs). BRAM-based TCAM suffers from the pre-processing of mapping data, requires the data to be in a specific order in some cases, and has a large SRAM/TCAM bit ratio. LUTRAM-based CAM/TCAM suffers from wide bit-wise ANDing, high routing complexity, but has a small SRAM/TCAM bit ratio of 14 compared to 16 in the case of BRAM-based TCAM. Shallow and wide RAM blocks are required to implement large-size RAM-based TCAMs (BRAM-based and LUTRAM-based TCAMs). FF-based TCAMs use FFs as their memory elements and have reduced hardware costs per TCAM bit. However, due to the routing complexity, it suffers from scalability and a large amount of power consumption. The update latency of BRAM-based TCAM and LUTRAM-based TCAM is proportional to the depth of BRAM and LUTRAM, respectively. However, FF-based CAM updates in 1 or 2 clock cycles depending on the availability of input/output pins on target FPGA.

In the missing item task, two short lists are presented. The test list contains all but one of the items from the study list in a new random order and the task is to report which item from the study list is missing. Murdock and Smith (2005) found that the time to correctly respond with the missing item was independent of the position of the missing item and was also independent of the list length. They argued that these data are difficult to accommodate by models that include a search process but are consistent with models that posit "direct access" such as the power set version of Theory of Distributed Associative Memory (TODAM). If direct access is occurring, redintegration cannot be occurring. Two experiments test the direct access account by determining whether two effects commonly ascribed to redintegration occur in the missing item task. Experiment 1 found a semantic relatedness effect and Experiment 2 found a word frequency effect. The presence of these effects is consistent with a redintegration account. Implications for TODAM and for an explanation based on the Feature Model are discussed. (PsycInfo Database Record (c) 2022 APA, all rights reserved).

GIRAF is a General purpose In-storage Resistive Associative Framework based on resistive content addressable memory (RCAM), which functions simultaneously as a storage and a massively parallel associative processor. GIRAF alleviates the bandwidth wall by connecting every memory bit to processing transistors and keeping computing inside the storage arrays, thus implementing deep in-data, rather than near-data, processing. We show that GIRAF outperformed a reference computer architecture with a bandwidth-limited external storage access on a variety of data-intensive workloads. The performance of GIRAF Dot Product and Sparse Matrix-Vector multiplication exceeds the attainable performance of a reference architecture by 1200 $ \;\times $ × and 130 $ \;\times $ × , respectively.

In this paper, a physical Sr 0.97 Ba 0.03 TiO 3 - x (SBT) memristor with the voltage threshold characteristic was prepared. For characterizing the electrical characteristics of SBT memristor accurately, an adaptive voltage threshold memristor model was proposed. The synaptic plasticity of SBT memristor with different pulse stimulation was analyzed. Moreover, a Pavlov associative memory circuit was designed in the LTSPICE environment, which is composed of neuron circuit and memristive synaptic circuit. The neuron circuit can generate spike signals when the input signals exceed the threshold, and the synaptic weight can be tunable continuously by spike signals. Different from other memristive synaptic circuits, the proposed memristive synaptic circuit is based on physical SBT memristor, and the change of synaptic weight can be truly reflected in the circuit. In Pavlov’s dog experiment, when the presynaptic neuron receives the conditioned stimulus (CS) before the unconditioned stimulus (US), the synaptic weight of SBT memristor is increasing and the associative memory is building. When the presynaptic neuron receives the CS alone, or presynaptic neuron receives the CS after the US, the synaptic weight of SBT memristor is decreasing and the associative memory is losing. This phenomenon is highly similar to the building and losing processes of biological associative memory. These experimental results verify the feasibility and applicability of SBT memristor as electronic synapse in neuromorphic applications, and pave the way towards further development of artificial neural networks.

Artificial Neural Network (ANN) is a form of computation inspired by the arrangement and purpose of the brain. Pattern Recognition is one of the demanding areas under Artificial Neural Network and pattern association is one of the major tasks through which pattern recognition is realized. Nowadays researchers are taking interest in the combination of evolutionary algorithms and ANN. In the present work, an attempt is being made to analyze the performance of Hopfield Associative Memory with Monte Carlo adaptation rule and evolutionary searching (Genetic Algorithm) for pattern storage and recall. The training pattern set has been taken a set of five Greek alphabet letters as different objects. The aim is to store Patterns with MC adaptation rule and get the best weight matrices for efficient recalling of any given set patterns. The neural networks architectures have been taken up for storing the given set of inputs, for which conventional Hebbian and Monte Carlo adaptation rule is considered. During the mutation process, various mutation probabilities are supposed to be evaluated. The detailed simulated results thus obtained will be presented with the help of tables and graph.

Many advances have been made in developing bio-inspired intelligent systems for performing important tasks like pattern association, which cannot be performed effectively by the conventional computer architectures. This paper presents a novel nonvolatile associative memory based on spintronic synapses utilizing magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistors (CNTFET)-based neurons. MTJs introduce fascinating features like reconfigurability, nonvolatility, and high endurance to the design, while CNTFETs compensate for the flaws of the conventional transistors in deep nanoscale nodes. The comprehensive simulations validate the functionality of the proposed synaptic cell, and neuron, even in the presence of major process variations. The application of the proposed synaptic cell and neuron in the hardware realization of multi-associative memories is also investigated. The simulation results indicate that the proposed hardware-based multi-associative memory performs similar to its ideal software-based counterpart with a less than 5% difference in the successful recall rate. The proposed multi-associative memory can be used as a neural network hardware accelerator alongside a conventional computing system with no need for any extra component, since its input and output are logical ‘0’ and ‘1’.

Brain-inspired architectures are gaining increased attention, especially for edge devices to perform cognitive tasks utilizing its limited energy budget and computing resources. Hyperdimensional computing (HDC) paradigm is an emerging framework inspired by an abstract representation of neuronal circuits’ attributes in the human brain. That includes a fully holographic random representation, high-dimension vectors representing data, and robustness to uncertainty. The basic HDC pipeline consists of an encoding, training and comparison stages. The encoding algorithm maps different representations of inputs into a single class and stores them in the associative memory (AM) throughout the training stage. Later, during the inference stage, the similarity is computed between the query vector, which is encoded using the same encoding model, and the stored classes in the AM. HDC has shown promising results for 1D applications using less power, and lower latency than state-of-the-art digital neural networks (DNN). While in 2D applications, convolutional neural network (CNN) still achieves higher classification accuracy at the expense of more computations. In this paper, a comprehensive study on the HDC paradigm, main algorithms, and its implementation is presented. Moreover, the main state-of-the-art HDC architectures for 1D and 2D applications are highlighted. The article also analyzes two competing paradigms, namely, HDC and CNN, in terms of accuracy, complexity, and the number of operations. The paper concluded by highlighting challenges and recommendations for future directions on the HDC framework.

Software defined networking (SDN) with separated control plane and data plane brings new opportunities for traffic measurement in data center networks. However, in the SDNenabled switches, available TCAM (Ternary Content Addressable Memory) resources for traffic measurement are limited. Thus, it is necessary to utilize traffic matrix (TM) estimation to derive a hybrid network monitoring scheme through combining the partial direct measurement offered by SDN with some inference techniques. Although large size flows play an important role in improving TM estimation accuracy, directly monitoring each flow and finding out large size flows consume massive channel bandwidth resource between control plane and data plane. Therefore, in this paper, we identify large size flows from multiple historical TMs instead of monitoring each flow. First, we analyze multiple historical TMs and observe that origin-todestination (OD) pair whose flow size is selected as large size flow at last time slot is most likely to be selected for per-flow monitoring at next time slot, so these OD pairs are identified by gradient boosting machine and are directly regarded as sampled OD pairs in order to reduce resource consumption. Then, we propose a greedy heuristic algorithm to solve SDN-enabled switch selection problem to best utilize the TCAM resources and guarantee that most of sampled OD pairs are measured in the flow table. We also present a source node prefix tree based bit merging aggregation (SPTBMA) scheme to design feasible forwarding rules to be inserted in TCAM of SDN-enabled switches and reserve more TCAM space for sampled OD pairs. Finally, the experimental results based on real traffic dataset demonstrate that our proposed scheme outperforms the existing algorithms in terms of improving TM estimation accuracy and overcoming limitation of TCAM resources.

This paper revisits the dense associative memory (DAM) networks and studies rigorously the capacity of the DAM networks. We present the capacity theorem of the DAM networks with an attraction radius or a noise level from the messages and prove that the probe can converge to the targeted message just after the one-step update. Under this convergence, the capacity of DAM networks is between a lower bound and an upper bound. Although when the attraction radius is 0.0 away from the messages, i.e. noiseless, previous literature provides an approximate result. However, a rigorous proof is not given in this study. In addition, we consider a more general notion of capacity which allows the retrieval of messages from noisy probes (the attraction radius is not 0.0 ). We demonstrates that the convergence result can be acquired just after the one-step update when the probe is a corrupted version with a Gaussian noise from one message. We further provide simulated experiments to validate theorems herein.

Memories play an essential role in computer systems as they store and retrieve data that may include instructions required for system operation. In the case of an assembler, the memory stores instructions such as the Opcode table (OPTAB), which contains the instructions in the form of machine language to implement the desired program. A search operation is required for the Opcode table to obtain the desired instruction. To improve the speed of search operations and overall system efficiency, there are various search operation algorithms and techniques available, including linear, binary, and hashing algorithms. However, they all share one critical aspect which is they rely on software-based techniques that counter difficulties with the von Neumann Model. In this paper, we introduce a hardware-based approach to enhance the search operation for OPTAB in assemblers, which is usually performed using software-based techniques. Our proposed method involves replacing the conventional Random Access Memory (RAM) with Binary Content-Addressable Memory (BiCAM), which enables parallel search operation within a single clock cycle. To demonstrate the effectiveness of our approach, we utilize the BZK.SAU.FPGA assembler as a case study. We provide a comparison of our proposed method with the RAM-based searching algorithm used in BZK.SAU.FPGA assembler. Time complexity analysis and a comparison of resource utilization and power efficiency are provided. Our results showed that the proposed method has a fixed time complexity of O(1) under all conditions, regardless of memory size or input size. An increase in both resource utilization and power efficiency has been observed in the BiCAM due to its hardware structure. However, it could still be considered a reasonable trade-off for time-sensitive applications. © 2023, The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature.

First, the cerebellar model articulation controller (CMAC), invented in the early 1970s by J S Albus, and the associative memory system (AMS), developed for learning control systems by H Tolle, E Ersu and J Militzer in the early 1980s, are briefly described. The underlying mathematics of the AMS learning or training algorithm is then given with a geometrical interpretation from which its convergence properties may be deduced. These are illustrated for some simple cases. The original algorithm devised by Albus is very simple to compute but is slow to converge, and the second part of the paper investigates various methods of speeding up the algorithm. From an application of these new algorithms to test cases one is strongly recommended for further evaluation. The results reported here are of relevance also to the topical and rapidly growing field of neural computing.

In this brief, we present FracTCAM, an efficient methodology for ternary content addressable memory (TCAM) emulation on Xilinx field-programmable gate arrays (FPGAs) by leveraging primitive architectural resources. The proposed methodology exploits the fracturable nature of lookup table random access memories (LUTRAMs) and built-in slice flip-flops for deeper pipelining. Multiple slices can be combined together to build deeper and wider TCAMs using ANDing operations. This results in TCAM implementations that achieve lower resources utilization, lower delay, and power consumption. A comparison with the existing schemes shows that FracTCAM consistently achieves the best performance per area (PA) and performance per area per watt (PAW).

Some aspects of our memory are enhanced by emotion, whereas other can be unaffected or even hinder. In particular, previous studies report impaired associative memory of emotional content, an effect termed associative 'emotional interference'. The current study utilized EEG and an associative recognition paradigm to investigate the cognitive and neural mechanisms associated with this effect. In two experiments, participants studied negative and neutral stimulus-pairs that were either semantically related or unrelated. In Experiment 1 emotions were relevant to the encoding task (valence judgment) whereas in Experiment 2 emotions were irrelevant (familiarity judgment). In a subsequent associative recognition test, EEG was recorded while participants discriminated between intact, rearranged, and new pairs. An associative emotional interference effect was observed in both experiments, but was attenuated for semantically related pairs when emotions were relevant to the study task. Moreover, a modulation of an early associative memory ERP component depended on task relevancy of emotions, and occurred for negative pairs when emotions were relevant, but for semantically related pairs when emotions were irrelevant. A later ERP component depicted a more general pattern, and was observed in all experimental conditions. These results suggest that both emotions and semantic relations can act as organizing principles that promote associative binding. Their ability to contribute to successful retrieval depends on specific task demands.

A new concept of a multi-valued associative memory is introduced, generalizing a similar one in fuzzy neural networks. We expand the results on fuzzy associative memory with thresholds, to the case of a multi-valued one: we introduce the novel concept of such a network without numbers, investigate its properties, and give a learning algorithm in the multi-valued case. We discovered conditions under which it is possible to store given pairs of network variable patterns in such a multi-valued associative memory. In the multi-valued neural network, all variables are not numbers, but elements or subsets of a lattice, i.e., they are all only partially-ordered. Lattice operations are used to build the network output by inputs. In this paper, the lattice is assumed to be Brouwer and determines the implication used, together with other lattice operations, to determine the neural network output. We gave the example of the network use to classify aircraft/spacecraft trajectories., Comment: This is a version with correct Theorem 3 (Theorem 2 in published variant)

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with Stanford Associative memory for Programmable, Integrated Edge iNtelligence via life-long learning and Search (SAPIENS), a resistive random access memory (RRAM)-based non-volatile associative memory (AM) chip that serves as the backend for memory-augmented neural networks (MANNs). The 64-kb fully integrated RRAM-CMOS AM chip performs long-term feature embedding and retrieval, demonstrated on a 32-way one-shot learning task on the Omniglot dataset. Using only one example per class for 32 unseen classes during on-chip learning, SAPIENS achieves 79% measured inference accuracy on Omniglot, comparable to edge software model accuracy using five-level quantization (82%). It achieves an energy efficiency of 118 GOPS/W at 200 MHz for in-memory L1 distance computation and prediction. Multi-bank measurements on the same chip show that increasing the capacity from three banks (24 kb) to eight banks (64 kb) improves the chip accuracy from 73.5% to 79%, while minimizing the accuracy excursion due to bank-to-bank variability.