Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application

A spectrum of emerging applications including edge artificial intelligence advocate the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this paper. Based on novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in layout. An analytical model is also presented which allows us for a systematic investigation on the energy reduction by adapting our design to various pre-search structures. Validated on a post-layout 32W64 ternary CAM in 28nm, our parallel-matching scheme performs at 2.6GHz with 0.42fJ/bit/search, and the (8-bit) pre-search scheme achieves 0.19fJ/bit/search at 1.1GHz, both under the 0.9V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45V with a minimum energy consumption of 0.06fJ/bit/search at 50MHz.