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This paper proposes a low-power charge pump PLL (CPPLL) with 1-V supply voltage in 180-nm CMOS technology, which serves as a low-cost clock generator for heterogeneous integration. Tradeoffs between power consumption, jitter performance and limited loop bandwidth in the conventional CPPLL have been analyzed first, followed by the explanations on reference spur issues in wide bandwidth architectures. A novel two-stage ring oscillator with low voltage capability and linear control gain has been proposed and analyzed in detail, which facilitates the implementation of this 1-V design. Fabricated in SMIC 180-nm technology, the designed PLL occupies a die area of 0.177 mm2 with an integrated loop filter. The PLL draws 1.8 mA when working at 480 MHz, and shows a rms jitter of 7.2 pS, which is 20 times more power efficient compared with PLLs with similar frequency and technology node. The design shows potential for heterogeneous integration. [ABSTRACT FROM AUTHOR]

A low power clock generator with self-calibration for UHF RFID tags compatible with the EPCglobal Class-1 Gen-2 (EPC Gen2) standard is presented. By utilizing the timing information of the reader to tag (R ⇒ T) link symbols, the frequency accuracy of the calibrated clock can meet the stringent requirement of the standard. Designed in a 0.18 μ m standard CMOS technology, simulation results show that the frequency error of the clock source is only from − 2.07 to + 1.4% of the target frequency of 2.56 MHz. The power consumption is only 720 nW. [ABSTRACT FROM AUTHOR]

A method of accuracy error compensation for the time interval is examined, allowing to decrease the dependence of accuracy error on the duration of measured intervals and minimising the influence of destabilising factors – ambient temperature changes and the initial deviation of the meter clock generator frequency from the nominal value. The compensation method is based on a calibration procedure that measures precise time intervals under conditions of changing ambient temperature. Then the dependence of the accuracy error on temperature for a particular meter is recorded. Based on these data, a correction table is compiled containing correction factors and temperature values at which these factors were determined. Under real measurement conditions, the correction factor corresponding to the current temperature is determined from the table for measured result correction. The table with correction factor values could be stored in the memory of the meter or processing computer. Experimental verification of the method showed that applying a correction for a meter with a standard XO class clock generator (certificated instability of ±50 ppm) could obtain an equivalent clock generator instability of ±0.15 ppm. The application of the method is efficient in cases where the use of high-end clocking to ensure the required measurement accuracy is not economically feasible. [ABSTRACT FROM AUTHOR]

The development of large-scale quantum computing has boosted an urgent desire for the advancement of cryogenic CMOS (cryo-CMOS), which is a promising scalable solution for the control and read-out interface of quantum bits. In the current work, 180 nm CMOS transistors were characterized and modeled down to 4 K, and the impact of low-temperature transistor performance variations on circuit design was also analyzed. Based on the proposed cryogenic model, a 180 nm CMOS-based 450 to 850 MHz clock generator operating at 4 K for quantum computing applications was presented. At the output frequency of 600 MHz, it achieved < 4.8 ps RMS jitter with 30 mW power consumption (with test buffer), corresponding to a −211.6 dB jitter-power FOM, which is suitable for providing a stable clock signal for the control and readout electronics of scalable quantum computers.

This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD) based on sub-multi-modulus dividers (SMMD) are developed for faster locking, lower jitter, and implementation of multi-protocol data communications applications. The clock generator is fabricated in 0.18 μm CMOS technology. The measured division ratio of the multi-modulus divider ranges from 1.875 to 25, and the output frequency is 46.875~625 MHz. The lock time does not exceed 30 μs, while jitter is less than 500 fs. [ABSTRACT FROM AUTHOR]

The purpose of the article is to study the possibility of compensating for the temperature instability of the quartz oscillator of an intelligent electronic device in case of loss of a synchronizing signal from a navigation satellite.An algorithm for software compensation of the temperature instability of a quartz oscillator has been developed and implemented. The author's implementation of temperature compensation of quartz oscillators is implemented as a program in the LabView FPGA environment, tested in a series of experiments using two CompactRIO controllers: a reference one and a device with software compensation. As a result of applying compensation, it was possible to linearize the dependence and reduce it from 0,65 cycles per degree Celsius to 0.04 cycles per degree Celsius for a 200 MHz generator. This compensation method does not require material costs or changes in the design of the measuring device and is ready for use in most measuring devices

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An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output clock frequency. The proposed MDLL has two operation modes: TDC tracking and sequential tracking. At the beginning of the operation, the MDLL utilizes a cyclic Vernier time-to-digital converter (TDC) to detect the initial phase error between the reference clock and the output clock. Then the TDC generates a digital code word (DCW) for controlling the digitally controlled oscillator (DCO) to achieve a fast lock time. The gains of TDC and DCO are designed to match well with each other, enabling phase and frequency locking in only two searches in the TDC tracking mode. After locking, the TDC is turned off, and the MDLL performs the sequential tracking mode and minimizes jitter by using the delta-sigma modulator (DSM)-based dithering jitter reduction scheme. The prototype all-digital MDLL is fabricated in a 40-nm CMOS process and achieves a fast lock time of less than six reference clock cycles at 1.6 GHz from a 100 MHz reference clock. Even when the 100 MHz reference clock has a relatively high RMS jitter of 2.19 ps (peak-to-peak jitter = 15.74 ps), the measured RMS and peak-to-peak jitter values of the 1.6 GHz MDLL output clock are only 2.75 ps and 23.01 ps, respectively. The proposed all-digital MDLL occupies an active area of only 0.024 mm2 and dissipates 3.56 mW at 1.6 GHz.

This paper proposes a 2.4-GHz fully-integrated single-frequency multi-channel RF energy harvesting (RFEH) system with increased harvested power density. The RFEH can produce an output power of ~423-μW in harvesting ambient RF energy. The front-end consists of an on-chip impedance matching network with a stacked rectifier concurrently matched to a 50 Ω input source. The circuit mitigates the "dead-zone" by enhancing the pumping efficiency, achieved through the increase of Vgs drivability of the proposed internal gate boosting 6-stage low-input voltage charge pump and the 5-stage shared-auxiliary-biasing ring-voltage-controlled-oscillator (VCO) integrated to improve the start-up. The RFEH system, simulated in 180-nm complementary metal–oxide–semiconductor (CMOS), occupies an active area of 1.02 mm2. Post-layout simulations show a peak power conversion efficiency(PCE) of 21.15%, driving a 3.3-kΩ load at an input power of 0 dBm and sensitivity of −14.1 dBm corresponding to an output voltage, Vout,RFEH of 1.25 V. [ABSTRACT FROM AUTHOR]

The data acquisition system is widely used in electronic measuring instruments, for example, the oscilloscope. The development direction of the oscilloscope reflects the research status and development trend of the data acquisition system. Currently, the index of oscilloscopes is progressing toward a high sampling rate, and the performance of the analog‐to‐digital converter (ADC) has become the main bottleneck to improve the sampling rate of the acquisition system. The alternate sampling technology entails multichannel low sampling rate ADCs to achieve high sampling rate data acquisition through parallel sampling and realize data reconstruction through software. The sampling clock is the most important and difficult part of the system. For ADCs with the 100‐GS/s sampling rate and 10‐bit resolution, the jitter of the sampling clock needs to be in sub‐100 fs along with multiple phases. Based on the principle of injection locking, a 150‐GS/s sampling clock is proposed in this paper, which is implemented in a 0.15‐μm GaAs process, and the 50‐GHz locking range is achieved. The measurement results show that the sampling frequency is 150 GS/s, the root mean square (RMS) jitter is 63 fs with the integrated range from 1 kHz to 10 MHz, and the phase noise can meet the sampling requirements of the 10‐bit oscilloscope, which can provide a clocking scheme for small and low‐power ultrahigh‐speed oscilloscope. [ABSTRACT FROM AUTHOR]

This paper proposes a 2.4-GHz fully-integrated single-frequency multi-channel RF energy harvesting (RFEH) system with increased harvested power density. The RFEH can produce an output power of ~423-μW in harvesting ambient RF energy. The front-end consists of an on-chip impedance matching network with a stacked rectifier concurrently matched to a 50 Ω input source. The circuit mitigates the “dead-zone” by enhancing the pumping efficiency, achieved through the increase of Vgs drivability of the proposed internal gate boosting 6-stage low-input voltage charge pump and the 5-stage shared-auxiliary-biasing ring-voltage-controlled-oscillator (VCO) integrated to improve the start-up. The RFEH system, simulated in 180-nm complementary metal–oxide–semiconductor (CMOS), occupies an active area of 1.02 mm2. Post-layout simulations show a peak power conversion efficiency(PCE) of 21.15%, driving a 3.3-kΩ load at an input power of 0 dBm and sensitivity of −14.1 dBm corresponding to an output voltage, Vout,RFEH of 1.25 V.

This paper proposes a low sub-gigahertz frequency generator with fine frequency resolution. An injection-locked ring oscillator (ILRO) is firstly adopted to obtain multiphase output at integer multiple times crystal oscillator (XO) frequency. Following that, a multiplexer (MUX) selects the output phase according to the output of a delta-sigma modulator (Δ Σ M) to achieve high frequency, low in-band noise fractional output. A hybrid type finite impulse response (FIR) filter, which is composed of some MUXs, flip-flops (FFs), digitally-controlled delay units (DCDUs), and a linear multiphase combiner (MPC), is employed in cascading to suppress the quantization noise (Q-noise) at high-frequency offset. An auto-calibration scheme for calibrating the DCDU's delay has been proposed as well. Simulated in 65 nm CMOS, the proposed fractional-N frequency generator exhibits a phase noise performance that is well below − 118 dBc/Hz from 100 kHz to 100 MHz offset. The simulation also shows that the power consumption and die area is 10.6 mW and 0.3 mm2, respectively, with the FIR filter consuming 4.3 mW and 0.041 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing the overall power consumption. A 0.18 µm complementary metal–oxide–semiconductor standard process was used for the design, and measurements showed that the chip had a minimum controllable timing resolution of 4.81 ps and power consumption of 142 µW with an output signal of 364 MHz. When compared with other designs using advanced processes, the proposed DCO demonstrated the best power-to-frequency ratio. Therefore, it can output a signal at the required frequency more efficiently in terms of power consumption. Additionally, because the proposed DCO uses digital logic gates only, a cell-based design flow can be implemented. Hence, the proposed DCO is not only easy to implement in different processes but also easy to integrate with other digital circuits.

An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and die sizes. The technology scaling followed Moore’s law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flip-flops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C2-DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Post-layout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1-5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs. [ABSTRACT FROM AUTHOR]

A PLL-based clock generator with an auto-calibration circuit is presented. The auto-calibration circuit employs an oscillator-based time-to-digital converter (TDC) to achieve a constant loop bandwidth and fast lock time. The TDC measures the operating frequency of -stage ring-VCO with a resolution of in a time period of . The measured frequency is utilized to calibrate loop bandwidth and VCO frequency. The clock generator is designed in 40nm CMOS process and operates from 1.2GHz to 3.6GHz with 8-phase outputs. The total lock time is less than 3s including calibration and PLL closed-loop locking processes. Operating at 3.2GHz, the in-band phase noise is better than dBc/Hz and root-mean square (RMS) jitter integrated from 10KHz to 100MHz is 2 ps. In the entire operating range, the RMS jitter and reference spur are better than 5.5ps and dBc/Hz, respectively. The clock generator consumes only 3mW from 1.1V supply at high-frequency end and 1.6mW at low-frequency end. The active area is only 0.04mm2 including on-chip loop filter and auto-calibration circuits. [ABSTRACT FROM AUTHOR]

The behaviour of the adiabatic logic in the near threshold regime has been analysed in depth in this study. Near threshold adiabatic logic (NTAL) style can perform efficiently using a single sinusoidal power supply which reduces the clock tree management and enhances the energy saving capability. Power dissipation, voltage swing, effect of load, temperature, frequency etc. of NTAL circuits have been detailed here. Extensive CADENCE simulations have been done in 22 nm technology node to verify the efficacy of the proposed model. A power clock has been generated based on a switched capacitor regulator to drive the complex NTAL circuits. Analytical and simulated data match with high accuracy which validates the proposed adiabatic logic style in the near threshold regime. A significant amount of energy can be saved by the adiabatic logic with or without considering the power dissipation of the clock generator. [ABSTRACT FROM AUTHOR]

This brief presents a wide frequency-range synthesizable multiplying delay-locked-loop with a proposed nested delay cell. Operating in two different modes, the clock generator synthesizes output frequency that ranges from 80 kHz to 680 MHz. Owing to the synthesized finely controlled charge pump and phase detector with background offset calibration, the prototype clock generator achieves a 5.2 ps integrated RMS jitter at 680 MHz output while consuming 0.5 mW under a 1.2 V supply. [ABSTRACT FROM PUBLISHER]

Sub-threshold operation of devices provides a promising approach to satisfy the ultra-low power demand of handheld products. However, in this domain, the drive current exponentially depends on temperature which makes the sub-threshold circuits more prone to temperature variations. This paper proposes a scheme to improve the thermal stability of an ultra low power clock generator circuit which is vital for reliable operation of portable synchronous digital VLSI chip applications. In this work, combination of temperature monitoring circuit and control circuit has been incorporated to develop a thermally robust clock generator. A novel control strategy is developed, wherein the control voltage is adaptively altered to combat the exponential change in the clock period with the variation in temperature, without use of any passive components like resistors and capacitors. Simulation results shows that the proposed circuit gives constant clock period against a wide range of temperature variations. The proposed oscillator operates at 0.37V, consumes 1.5µW power and provides a temperature coefficient of 290ppm/°C over a temperature range from 10°C to120°C without any external trimming. [ABSTRACT FROM AUTHOR]