A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output clock frequency. The proposed MDLL has two operation modes: TDC tracking and sequential tracking. At the beginning of the operation, the MDLL utilizes a cyclic Vernier time-to-digital converter (TDC) to detect the initial phase error between the reference clock and the output clock. Then the TDC generates a digital code word (DCW) for controlling the digitally controlled oscillator (DCO) to achieve a fast lock time. The gains of TDC and DCO are designed to match well with each other, enabling phase and frequency locking in only two searches in the TDC tracking mode. After locking, the TDC is turned off, and the MDLL performs the sequential tracking mode and minimizes jitter by using the delta-sigma modulator (DSM)-based dithering jitter reduction scheme. The prototype all-digital MDLL is fabricated in a 40-nm CMOS process and achieves a fast lock time of less than six reference clock cycles at 1.6 GHz from a 100 MHz reference clock. Even when the 100 MHz reference clock has a relatively high RMS jitter of 2.19 ps (peak-to-peak jitter = 15.74 ps), the measured RMS and peak-to-peak jitter values of the 1.6 GHz MDLL output clock are only 2.75 ps and 23.01 ps, respectively. The proposed all-digital MDLL occupies an active area of only 0.024 mm2 and dissipates 3.56 mW at 1.6 GHz.