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A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. We then performed 400 virtual experiments comprising seven sources of process variation. Using this virtual fabrication technique, we were able to identify a minimum gate-to-source/drain spacer thickness for a high-temperature post-EPI rapid thermal anneal (RTA) anneal process that avoided device subthreshold slope penalties. The model allowed us to determine the optimal Si recess depth target and process window prior to source/drain epitaxy. We obtained these results by reviewing device performance as a function of statistical process sensitivity and highlighting key process parameters requiring variation control. These experiments would have been impractical to perform in an actual fab, due to the time, cost, and equipment requirements of running 400 fab-based process variation experiments for each process parameter. This methodology can be used to avoid wafer-based testing during early technology development.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.

This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(\text{L}_{\text{G}}\sim 25\text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $\text{L}_{\text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.

The scaling of device dimensions has resulted in a need for high resolution metrology techniques capable of measuring small CDs with a high degree of precision and accuracy. Scanning transmission electron microscopy (STEM) has previously been demonstrated to be a metrology technique capable of measuring small CDs and gathering large volumes of accurate and precise metrology data. In addition, energy dispersive X-ray spectroscopy (EDS) metrology has also been demonstrated to be a powerful technique enabling the detection and measurement of low contrast layers, specifically for 3D NAND devices. Benchmarking EDS metrology against STEM metrology in terms of precision and accuracy is important to further investigate the capabilities of EDS metrology for the semiconductor industry. This study was performed using the latest technology in EDS detectors, along with automated acquisition and metrology software to generate large metrology data sets on horizontal nanowire structures. In this paper, we present data to support our finding that EDS metrology is well-matched with STEM metrology in terms of both precision and accuracy. In addition, we discuss the capability of EDS and STEM metrology to detect subtle process variations in next-generation logic devices.

Metrology of most advanced CMOS devices poses more and more challenges: lithography and etch patterning processes need to be controlled on critical parameters that -beyond critical dimensions (CD)- nowadays also include line width and line edge roughness (LWR/LER), multiple patterning induced pitch-walk and, due to the high aspect ratio of the patterned structures, also thermo-mechanical structural bending. In this paper, it is shown that sufficient sampling is required to ensure that scanning transmission electron microscopy (STEM) does provide relevant information about the dimensions and chemical composition of the advanced devices. While, in principle, STEM can measure device dimensions with Angstrom resolution and sub-nm precision, a single measurement will not be representative for the device dimensions that are known to vary statistically (LER/LWR) as well as systematically (Pitch-walk, structural bending). In this context, the metrology capabilities of a (calibrated) automated 80-200kV STEM with Cs aberration corrector and a high efficiency EDS detector have been evaluated for both STEM-EDS and STEM-HAADF acquisitions. It will be shown that, when measuring multiple (~ 400) individual FinFET structures (Silicon Fins / dummy Silicon gate lines), average CD, LER and LWR can be quantified from the distribution of measured line widths and line pitches, that SADP and SAQP induced pitch-walk may show up as multi-modal pitch distributions, and that pitch walking can be quantified if also structural bending, that is observed, is properly taken into account. Finally, the STEM and EDS metrology capabilities for FinFET and NanoWire (NW) device structures are reviewed for different use cases (statistical process control and technology development support) and with different indicators (Precision over Tolerance ratio (P/T) and Variability ratio (r = 1 – σ2 metrology / σ2 measured process )).

A tri-layered in situ grown RuTiN barrier system for advanced interconnects was developed using plasma-enhanced atomic layer deposition (PE-ALD) from tetrakis(dimethylamino)titanium, (pyrrolyl-methylcyclopentadienyl)ruthenium and N2/H2 plasma. The system consists of an ultrathin TiN nucleation layer to enable Ru growth on Si oxide substrates, a bulk RuTiN layer, and a top Ru film to ensure compatibility with Cu and electrochemical Cu deposition techniques. It is shown that the nucleation layer does not need to be continuous and that 0.6–0.7 nm is sufficient to enable Ru nucleation on oxides. Layer closure studies of a Ru cap grown on RuTiN films indicate that the minimal thickness to have a closed Ru layer at the top surface is around 1.0 nm. 3 nm RuTiN films show good oxidation resistance and Cu barrier properties for interconnect applications when compared to the well-known TaN barrier system. Furthermore, conformal deposition in narrow lines has been obtained. As such, we demonstrate that using the flexibility of the PE-ALD process, composition controllability of the bulk and interfaces can be achieved for sub 3 nm thin RuTiN barriers. The interface composition can be optimized for compatibility with bottom and top layers, which makes the system a viable candidate for future interconnect technologies.

Different metallization options that allow filling 30nm 1/2pitch interconnect trenches have been explored and their full reliability performance has been benchmarked to conventional PVD TaNTa/PVD Cu seed based metallizations. CVD Co as seed enhancement layer shows no deterioration in barrier performance and improved electromigration performance, but the activation energy for electromigration was 0.68+/-0.20eV, which is at the lower end of the expected value of 0.85-0.95eV for this parameter. When integrating our trenches in a k=3.2 non-porous SiCOH low-k material, PVD RuTa barriers with 90%Ru and 10%Ta show degraded barrier performance and significant lowering of activation energy for electromigration (0.59+/-0.05eV) while when using SiO"2 as intermetal dielectric, no significant reliability deterioration is observed. Finally, it is shown that, using an optimized PVD Cu seed, standard PVD TaNTa-barriers give excellent barrier performance and that typical electromigration lifetime specs can be met with this metallization scheme down to 30nm 1/2pitch.

Cu wire resistance reduction using CVD Mn-based Self-Formed Barrier (SFB) compared to conventional PVD barrier was investigated at 40 and 100nm half pitch (HP). Mn-based SFB leads to both (1) maximum fractional Cu area in the trenches and (2) Cu resistivity reduction at scaled dimensions. This represents a breakthrough for future interconnect scaling. Blanket Cu experiments suggest that the Cu resistivity reduction in the case of Mn-based SFB can be attributed to lower surface scattering at the dielectric/Cu interface. Finally, promising reliability has been demonstrated in 20nm HP single damascene (SD) SiO 2 trenches integrated with Mn-based SFB.

We discuss the selection criteria for alternative metals in order to fulfill the requirements necessary for interconnects at half pitch values below 10 nm. The performance of scaled interconnects using transition metal germanides and CoAl alloys as metallization are studied and compared to conventional Cu and W interconnects.

We investigate void nucleation and growth during electromigration in 30 nm half pitch Cu lines. Diffusion interfaces are varied a) by using SiCN dielectric cap or a CoWP metal cap and b) by tuning the thickness of TaN/Ta barrier metal. The developed local sense EM test method and in-situ EM observations allow understanding void nucleation and growth stages. For the SiCN cap, independent of barrier thickness, there are two void growth modes sensitive to grain structure. In contrast, for the CoWP cap, a single mode independent of the grain structure is observed, where a nucleated void is pinned in the test line. We also show that Co diffuses into the interface between the barrier metal and Cu, and suppresses Cu diffusivity at that interface. As both Cu diffusivities at the cap and barrier interfaces are suppressed by the presence of Co, a CoWP cap is beneficial to electromigration for advanced interconnects where thinner barrier metals are required.

CVD Mn-based self-formed barrier (SFB) has been evaluated and integrated for reliability and RC delay assessment. Intrinsic TDDB lifetimes were extracted from planar capacitor measurement. A comparable lifetime as the TaN/Ta reference was obtained on SiO2 and porous low-k with a thin oxide liner. Good reliability performance was demonstrated after integration. Compared to conventional barrier, significant RC reduction (up to 45% at 40nm half pitch) and lower via resistance which become more beneficial upon scaling present CVD Mn-based SFB as an attractive candidate for future interconnect technology.

The aim of this paper is to predict the performance of local interconnects, manufactured by advanced patterning options as double patterning and EUV lithography. Electrical wire parameters as resistance, capacitance, RC delay and coupling between adjacent wires are extracted by simulation from scaled 2-D interconnect models, calibrated with dimensions and electrical parameters measured on simple test structures. CD and overlay variations of each patterning option are estimated from experimental and ITRS data and are included in the models. The extracted wire parameters allow the comparison between the patterning options and indicate the optimal choice for the next technology nodes.

Electromigration failure times of 100 nm wide dual damascene Cu interconnects have been evaluated over a very wide range of different stages of void formation and growth. Voids that did not span the whole line width and height have been monitored using the so-called local sense structures, while standard single via structures were used to study fully grown voids. The activation energy E a did not change over the whole experimental range of failure times indicating that the main diffusion path during void formation and growth does not change in our semi-bamboo lines. The earlier reported increase in distributional spread σ after full void formation is less pronounced during void formation which is due to different kinetics before and after full void formation. The use of defining failure criteria before full void formation has been explored as a tool to reduce electromigration test times. Due to the constant E a , test times can be reduced by over a factor of two.

50% Line Edge Roughness (LER) correlation has been observed after spacer formation in 20nm half pitch (HP) interconnects using Spacer- Defined Double Patterning (SDDP) approach. This correlation has a positive impact on Time-Dependent Dielectric Breakdown (TDDB) lifetime, which was also predicted by simulations. Comparison of TDDB lifetime for SDDP patterned 20nm HP and Litho-Etch-Litho-Etch (LELE) patterned 35nm HP Cu interconnects confirms that the SDDP approach offers potential benefits for TDDB lifetime, which enable future interconnect scaling.

Metallization options to fill 30nm ½ pitch trenches have been explored and their Time-Dependent-Dielectric-Breakdown (TDDB) and electromigration (EM) performance have been benchmarked to the conventional PVD TaNTa / PVD Cu seed based metallization. CVD Co as seed enhancement layer shows no deterioration in TDDB performance and improved EM performance, but the activation energy for EM was 0.68±0.20eV, which is at the lower end of the expected value of 0.85–0.95eV for this parameter. PVD RuTa barriers with 90%Ru and 10%Ta show degraded barrier performance and significant lowering of activation energy for EM (0.59±0.05eV). Finally, it is shown that, using an optimized PVD Cu seed, standard PVD TaNTa-barriers give excellent TDDB performance and that typical EM lifetime specs can be met with this metallization scheme down to 30nm ½ pitch.

A test structure that allows the study of void formation kinetics during electromigration is proposed and characterized. Compared to a standard single-via electromigration test structure voltage-senses are placed near the via. This allows monitoring resistance changes before final void formation, while the void formation process is not affected. Part of the samples show single void formation, while for other samples, multiple voids are formed. For the single void case, a model is proposed to calculate void-depth as a function of time. Initially, voids grow faster and this growth slows down towards the end of the void formation process. Estimated velocities during void formation are in the same order of magnitude compared to literature results of drift velocities during void growth. Cases where multiple voids are formed show that voids which initially form further away from the via stop growing upon formation of a void closer to the via.

The spacer defined double patterning (SDDP) approach for 20nm half pitch (HP) single damascene Cu interconnect structures using immersion lithography is being reviewed. Final results on wafer will be shown, focusing on critical double patterning topics such as CD & overlay budget and line edge roughness (LER); and their impact on the electrical functioning of the back-end-of-line test structures. The feasibility of extending the SDDP technique down to 15nm HP structures is also discussed. The 30nm line/space structures patterned in resist, required as a starting point for this exercise, will be patterned using EUV lithography.

Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).

In this paper we report on the successful integration of a 90nm low-k full VIA-first dual damascene process architecture using carbon-doped-oxide (CDO) and SiC etch-stop-layer (ESL). One of the key features of the integration scheme is that the effects of photoresist poisoning have been eliminated by optimization of the low-k (k < 3.0) film stack deposition process. The mechanisms underlying photoresist poisoning have been investigated through detailed partition studies. Electrical yield and reliability data will be shown to demonstrate the performance of the overall integration approach.

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