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A 11.56-kbit one-time programmable secure array featuring Intel’s first high-volume manufacturing (HVM) ready anti-fuse memory using the 22FFL process technology is reported. First, design and process technology are co-optimized to minimize the operating voltage, peripheral reliability stress, and area with dual gate-oxide 2-transistor (2T) bit cells. Second, a best reported array density and 1-V sense endurance supported by a low-voltage dynamic scheme that meets on-demand read requirements at a yield of 99.99% are demonstrated. Third, this is the first demonstration of integrated power delivery for anti-fuse memory in FinFET technologies. With program voltage limited to 5 V, 2-stage 1.8-V charge pumps improve system area and integration.

This study determines the relationship between retention and endurance reliability for a HfOx-based resistive random access memory (ReRAM). A TiN (15 nm) / HfOx (6 nm) / Ti (10 nm) / TiN (40 nm) stacked structure is fabricated and tested to verify its basic characteristics and reliability. The high resistance states (HRS) retention behavior is characterized and is found to degrade over 100x on the endured bits because there is a sequential high temperature procedure. The degradation is reduced slightly to a ~30x drop for the endured devices with one single refresh cycle. During the endurance and retention test procedures, the HRS resistance decreases because neutral oxygen vacancy filaments grow and this cannot be reversed. The I-V characteristics for endured devices are also determined. The results show that isothermal treatment causes a gradual SET and RESET process with multiple feasible states. The thermally induced filament degradation model (isolated filament vs. continuous filament) is verified by the relationship between retention and endurance reliability. Design guidance is recommended for an improvement in ReRAM reliability.

In this Chapter, we review the recent progress on resistance drift mitigation techniques for resistive switching memory devices (specifically memristors) and its impact on the accuracy in deep neural network applications. In the first section of the chapter, we investigate the importance of soft errors and their detrimental impact on memristor-based vector–matrix multiplication (VMM) platforms performance specially the memristance state-drift induced by long-term recurring inference operations with sub-threshold stress voltage. Also, we briefly review some currently developed state-drift mitigation methods. In the next section of the chapter, we will discuss an adaptive inference technique with low hardware overhead to mitigate the memristance drift in memristive VMM platform by using optimization techniques to adjust the inference voltage characteristic associated with different network layers. Also, we present simulation results and performance improvements achieved by applying the proposed inference technique by considering non-idealities for various deep network applications on memristor crossbar arrays. This chapter suggests that a simple low overhead inference technique can revive the functionality, enhance the performance of memristor-based VMM arrays and significantly increases their lifetime which can be a very important factor toward making this technology as a main stream player in future in-memory computing platforms.

Resistive random-access memory (RRAM) devices have drawn increasing interest for the simplicity of its structure, low power consumption and applicability to neuromorphic computing. By combining analog computing and data storage at the device level, neuromorphic computing system has the potential to meet the demand of computing power in applications such as artificial intelligence (AI), machine learning (ML) and Internet of Things (IoT). Monolayer rhenium diselenide (ReSe2), as a two-dimensional (2D) material, has been reported to exhibit non-volatile resistive switching (NVRS) behavior in RRAM devices with sub-nanometer active layer thickness. In this paper, we demonstrate stable multiple-step RESET in ReSe2 RRAM devices by applying different levels of DC electrical bias. Pulse measurement has been conducted to study the neuromorphic characteristics. Under different height of stimuli, the ReSe2 RRAM devices have been found to switch to different resistance states, which shows the potentiation of synaptic applications. Long-term potentiation (LTP) and depression (LTD) have been demonstrated with the gradual resistance switching behaviors observed in long-term plasticity programming. A Verilog-A model is proposed based on the multiple-step resistive switching behavior. By implementing the LTP/LTD parameters, an artificial neural network (ANN) is constructed for the demonstration of handwriting classification using Modified National Institute of Standards and Technology (MNIST) dataset.

We studied the pseudo-homeothermic synaptic behaviors by integrating complimentary metal–oxide–semiconductor-compatible materials (hafnium oxide, aluminum oxide, and silicon substrate). A wide range of temperatures, from 25 °C up to 145 °C, in neuronal dynamics was achieved owing to the homeothermic properties and the possibility of spike-induced synaptic behaviors was demonstrated, both presenting critical milestones for the use of emerging memristor-type neuromorphic computing systems in the near future. Biological synaptic behaviors, such as long-term potentiation, long-term depression, and spike-timing-dependent plasticity, are developed systematically, and comprehensive neural network analysis is used for temperature changes and to conform spike-induced neuronal dynamics, providing a new research regime of neurocomputing for potentially harsh environments to overcome the self-heating issue in neuromorphic chips.

The dual functions in HfOx-based ReRAM and 2V-programmable via-fuse technology featuring in simple metal-insulator-metal BEOL process are presented, which can integrate with the current metal fuse technology. The impact of via-size, ReRAM, and via-fusing programming windows, stacked structures, and integration capability has been extensively studied. The performance and reliability risk assessments show that the ReRAM and via fuse can sustain at 438 K for 500 h without any degradation. Our results provide pathfinding of high density, integration capability, low programing voltage, multi-functionality between programmable read-only memory (PROM) and ReRAM co-existing in embedded applications.

For the first time, the impact of temperature instability of resistive memory switching on potential neuromorphic computing applications has been extensively studied using eNVM-R and eNVM-M technologies developed on Intel 22FFL process. The reliability risk assessment shows that the effects of ambient temperature (e.g. resistance or conductance shifting with varying temperature) can lead to potential degradation of the neural network accuracy. Our results provide additional insight into device-level physical models and circuit-level design guidance for potential AI hardware applications.

The sneak path current (SPC) is the inevitable issue in crossbar memory array while implementing high-density storage configuration. The crosstalks are attracting much attention, and the read accuracy in the crossbar architecture is deteriorated by the SPC. In this work, the sneak path current problem is observed and investigated by the electrical experimental measurements in the crossbar array structure with the half-read scheme. The read margin of the selected cell is improved by the bilayer stacked structure, and the sneak path current is reduced ~20% in the bilayer structure. The voltage-read stress-induced read margin degradation has also been investigated, and less voltage stress degradation is showed in bilayer structure due to the intrinsic nonlinearity. The oxide-based bilayer stacked resistive random access memory (RRAM) is presented to offer immunity toward sneak path currents in high-density memory integrations when implementing the future high-density storage and in-memory computing applications.

Anaerobic ammonium oxidation (ANAMMOX) granular sludge was cultured during different operating conditions by an expanded granular sludge bed (EGSB) reactor and up-flow anaerobic sludge bed (UASB) reactors, and the characteristics of the granular sludge and microbial community were compared. The results showed that the flocculent ANAMMOX sludge can be granulated after being operated for 384 days by the EGSB and UASB reactors. The average particle size reached 1.17 mm and 1.21 mm, respectively. The particle size ratio of each range (0.2, 0.2-1.5, 1.5-3, and3 mm) was 6.06%, 60.05%, 25.25%, and 8.64% in the EGSB reactor, and 7.40%, 58.90%, 32.04%, and 1.66% in the UASB reactor, respectively. The results of scanning electron microscopy showed that the bacterial flora during different operating conditions were mainly

The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities of the brain, may provide such a shift. Many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop neuromorphic computing platforms. These platforms are being designed using various hardware technologies, including the well‐established complementary metal‐oxide semiconductor (CMOS), and emerging memristive technologies such as SiOx‐based memristors. Herein, recent progress in CMOS, SiOx‐based memristive, and mixed CMOS‐memristive hardware for neuromorphic systems is highlighted. New and published results from various devices are provided that are developed to replicate selected functions of neurons, synapses, and simple spiking networks. It is shown that the CMOS and memristive devices are assembled in different neuromorphic learning platforms to perform simple cognitive tasks such as classification of spike rate‐based patterns or handwritten digits. Herein, it is envisioned that what is demonstrated is useful to the unconventional computing research community by providing insights into advances in neuromorphic hardware technologies.

In this paper, vanadium oxide (VO x ) was chosen for the resistive switching layer in a typical resistive random access memory (RRAM) structure. During negative forming bias, we found an initial selector property. This indicates the presence of metal–insulator-transition characteristics in the VO x layer even without an annealing process. In order to study this phenomenon, material analyses were conducted, with results indicating that there are V-O stretching bonds and an oxide/vanadium ratio of nearly 2.2 ( ${O}/{V} = {2.2}$ ). In addition, the experimental results of the dc sweeping test indicated that off-state current gradually decreased after each cycle, meaning that the selectivity characteristics in the VO x selector could be improved. Endurance performance of our experimental devices reached 108, sufficient for integration with RRAM devices in a 1S1R array. To further investigate this special phenomenon, current fitting analysis and simulation analyses were conducted. The results of the fitting analysis indicated that the conduction mechanism for off-state current was Schottky emission and the Schottky distance increased with increasing numbers of cycles. In other words, oxide ions migrate toward the filament at low negative voltage during dc sweeping, causing the formation of VO x . Furthermore, the results of thermal field simulation analysis indicated that there is a thermal concentration effect in and around the filament. Thus, oxide ions more easily migrate toward the vanadium filament when a stronger electrical field is present around the filament during dc sweeping cycles. Finally, stable vanadium selector characteristics are obtained and a conduction filament behavior model is proposed.

We explore overcoming the non-oxidizing environment requirement issues in silicon oxide (SiOx) based memristors and investigate potential next steps for use of SiOx as a memristor material. A SiOx/HfOx stacked material was engineered, developed and tested to verify operation of the SiOx-based memristors, and the stacked material exhibits interfacial proton accumulation leading to ultra-low-voltage operation (

Selectorless graphite-based resistive random-access memory (RRAM) has been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without an additional selector or transistor for low-power RRAM array application. The low effective dielectric constant value (k) layer of graphite or graphite oxide is utilized, which is beneficial in suppressing sneak-path currents in the crossbar RRAM array. The tail-bits with low nonlinearity can be manipulated by the positive voltage pulse, which in turn can alleviate variability and reliability issues. Our results provide additional insights for built-in nonlinearity in 1R-only selectorless RRAMs, which are applicable to the low-power memory array, ultrahigh density storage, and in-memory neuromorphic computational configurations.

Resistive random access memory (RRAM) using various metal oxides (i.e., SiO2[1], HfO2, NiO[2], Al2O3, NbO) have attracted much attentions since the current nonvolatile memory (NVM) has been approaching the scaling limit. Meanwhile, selector devices are essential to address the sneak path issue which causes reading errors and hinders the implementation of RRAM in high-density cross-bar array architecture [3-4]. However, additional selector devices, e.g. a commonly proposed one selector-one resistor (1S-1R) design, increases the process complexity and cost. In this work, selectorless 1R RRAM devices have been demonstrated by utilizing the nonlinear (NL) resistive switching (RS) characteristics. Pulse operation voltage variation tolerance on SiOx-based stacking structures has also been characterized. The starting substrates are heavily-doped N+ Si wafers, and titanium nitride of 200 nm thickness was deposited on N+ Si substrate as bottom electrode. Then, 9 nm of SiOx and 4 nm of HfOx were deposited as RS dielectric layers for bilayer (HfOx/SiOx) structures by RF sputtering method. Pt (165nm) was deposited as top electrodes for RRAM devices (Fig. 1). Fig. 2 shows bipolar RS I-V characteristics during DC voltage sweeps for single-layer HfOx and bilayer devices. Both SET and RESET voltages are lower in single-layer HfOx devices than in bilayer devices possibly due to higher oxygen concentration. The SET voltage of single-layer HfOx devices is about 0.2 V lower than of single-layer SiOx devices, and RESET voltage is reduced to half (~ 0.5 V) with inserting a HfOx stack layer, which is potentially beneficial for low voltage operating applications. Also, the RESET current is critical for overall switching power in RRAM applications, is ~1 mA and has been found to be independent of the thickness ratio of stacks. Comparing the bilayer structure to the single-layer HfOxstructure, the current at -0.2 V is reduced from ~10-4 to ~10-6 A. It depicts that there was significantly increased resistance at low voltage region, which is proposed as a solution for sneak path issue in crossbar array applications. Nonlinearity (NL) is defined as the ratio of the current at full read voltage (i.e. -0.6 V) to the current at 1/3 read voltage (-0.2 V). The higher nonlinearity, the better ability is to avoid the sneak current interference. The NL characteristics in ILRS of all the devices are showed in Fig. 3. With a thin SiOx layer (2 nm) on the bottom of HfOx (11 nm) layer, the NL is ~3x in comparison to the single-layer HfOx layer devices. Based on our results, the bilayer RRAM device has been found to show the highest NL among the SiOx-based stacking structures. This makes SiOx-based bilayer devices a potential candidate for 1R selectorless RRAMs. To evaluate the voltage variation tolerance in pulse operation, the reset stop voltage effect has been studied. The RS I-V was characterized with increasing RESET stop voltage from -1.4 to -2.6 V for the bilayer and trilayer devices (Fig. 4). For bilayer devices, the high resistance state (HRS) resistance and memory window increase with increasing RESET stop voltage (Fig. 5). The bilayer devices with higher SET/RESET voltage variation tolerance (less variation below stop voltage of 2.2 V) and have been found to exhibit better NL characteristics (~10) than the trilayer devices, which shows larger switching voltage variation with changing reset stop voltage (Fig.6). In this study, build-in nonlinear characteristics have been realized for the SiOx-based one-resistor (1R) device without an additional diode or a selector. The highly nonlinear characteristics observed in SiOx-based bilayer devices are desirable in avoiding the read error and preventing sneak-path currents in crossbar arrays. Our results show that SiOx-based bilayer devices are promising for high-density, low-power, selectorless RRAM applications. Figure 1

In this paper, implication (IMP) operations are demonstrated in a circuit with two SiOx-based memristors and a CMOS transistor. Specifically, a circuit with two one-diode and one-resistor (1D1R) memory elements and a transistor are designed to perform the IMP operations. A circuit consisting of a $4 \times 4$ crossbar 1D1R memristor array together with selection transistors is proposed and used to realize the functionality of a one-bit, full adder in 43 steps. Compared with CMOS logic circuits, the advantages and disadvantages of memristor-enabled logic circuits are discussed. This result suggests that the memristor-enabled logic circuit is most suitable for low-power and high-density applications, as well as a simple and robust approach to realize programmable memcomputing chips compatible with large-scale CMOS manufacturing technology.

This letter illustrates short-term relaxation in CeOx-based resistive random access memory (RRAM) devices. Our results suggest that the noise of the serial selector device can impact the short-term relaxation, reduce the operating window of the RRAM, and increase the read error. Our findings indicate that the application of longer initial forming pulses can mitigate the short-term relaxation issue.

Seismic wavelet estimation is an important part of seismic data processing and interpretation, whose reliability is directly related to the results of deconvolution and inversion. The methods for seismic wavelet estimation can be classified into two basic types: deterministic and statistical. By combining the deterministic spectral coherence method and the statistical skewness attribute method, the amplitude and phase of the time-varying wavelet are estimated separately. There is no assumption on the wavelet's time-independent nature or the phase characteristic. The advantage of this method is the ability to estimate time-varying phase. Phase-only corrections can then be applied by means of a time-varying phase rotation. Alternatively, amplitude and phase deconvolution can be achieved to enhance the resolution and support the fine reservoir prediction and description. We illustrate the method with both synthetic and real data examples. Synthetic examples certify its feasibility while real data example demonstrates the ability to estimate the time-varying characteristic of wavelets.

This study proposes a method for a HfO2-based device to exhibit both resistive switching (RS) characteristics as resistive random access memory (RRAM) and selector characteristics by introducing vanadium (V) as the top electrode. This simple V/HfO2/TiN structure can demonstrate these two different properties depending on forming polarities. The RS mechanism is activated by a positive forming bias. In contrast, the selector property is induced by a negative forming bias. The material analyses firstly confirm the existence of V in the top electrode. Then the electrical measurements for the same V/HfO2/TiN structures but with different forming polarities were carried out to further investigate their DC sweeping characteristics to act as either a selector or RRAM device. Furthermore, reliability tests for both selector and RRAM devices were also conducted to confirm their switching stabilities. Finally, current fitting methods and temperature influence experiments were performed to investigate the carrier transport mechanisms. Finally, physical models were proposed to illustrate the selector property and RS mechanism for selector and RRAM devices, respectively. This simple device structure with its easy operating method accomplishes a significant advancement of devices combining both selector properties and RRAM for remarkable real applications in the near future.

Here we demonstrate low-power resistive switching in a Ni/SiNy/SiNx/p++-Si device by proposing a double-layered structure (SiNy/SiNx), where the two SiN layers have different trap densities. The LRS was measured to be as low as 1 nA at a voltage of 1 V, because the SiNx layer maintains insulating properties for the LRS. The single-layered device suffers from uncontrollability of the conducting path, accompanied by the inherent randomness of switching parameters, weak immunity to breakdown during the reset process, and a high operating current. On the other hand, for a double-layered device, the effective conducting path in each layer, which can determine the operating current, can be well controlled by the ICC during the initial forming and set processes. A one-step forming and progressive reset process is observed for a low-power mode, which differs from the high-power switching mode that shows a two-step forming and reset process. Moreover, nonlinear behavior in the LRS, whose origin can be attributed to the P-F conduction and F-N tunneling driven by abundant traps in the silicon-rich SiNx layer, would be beneficial for next-generation nonvolatile memory applications by using a conventional passive SiNx layer as an active dielectric.

Characteristics of HfOx-based resistive switching memory (RRAM) in Al/HfOx/Al and Al/AlOx/HfOx/Al structures were studied using a dynamic conductance method. Step-like RESET behaviors as well as pre- and post-RESET regions of operation were characterized. The results indicated that defects at the oxide interface caused cycling issues in the Al/AlOx/HfOx/Al structure. No such RESET behavior was observed for the Al/HfOx/Al structure. Current induced over-heating, which caused an early RESET event, could be avoided using current-sweep technique that caused less electrical and thermal stress in localized regions. The experimental results not only provided insights into potential reliability issues and power management in HfOx-based RRAM, but also helped clarifying the resistive switching mechanisms.

In this work, we present silicon process compatible, stable and reliable (>108 cycles), high non-linearity ratio at a half-read voltage (>5 × 105), high speed (

Two resistive memory devices were prepared with different doping concentrations in the silicon bottom electrodes to explore the self-rectifying and nonlinear resistive switching characteristics of Ni/SiNx/p-Si devices. Due to the reduced current overshoot effect, using electroforming at a positive bias can produce bipolar-type resistive switching behavior. A higher self-rectification ratio in the Ni/SiNx/p+-Si device is achieved than in the Ni/SiNx/p++-Si device. The asymmetric I–V characteristics can be explained by the Schottky barrier that suppresses the reverse current, and it is controllable by the size of the conducting path. A conducting path with a high resistance value in a low resistance state is beneficial for a high selection ratio. Moreover, by controlling the compliance current, we demonstrate an improved self-rectifying and selection ratio. The results of our experiment provide a possible way to improve the nonlinear characteristics without the need for a selector device in CMOS compatible cross-point array applications.

This paper presents key specifications of RRAM-based nonvolatile memory embedded into Intel 22FFL FinFET Technology. 22FFL is a high performance, ultra low power technology developed for mobile and RF applications providing extensive high voltage and analog support and high design flexibility combined with low manufacturing costs [1]. Embedded RRAM technology presented in this paper achieves 104 cycle endurance combined with 85°C 10-year retention and high die yield. Technology data retention, endurance and yield are demonstrated on 7.2Mbit arrays. We describe device characteristics, bit cell integration into the logic flow, as well as key considerations for achieving high endurance and retention properties.

We studied the pseudo-homeothermic synaptic behaviors by integrating complimentary metal-oxide-semiconductor-compatible materials (hafnium oxide, aluminum oxide, and silicon substrate). A wide range of temperatures, from 25 °C up to 145 °C, in neuronal dynamics was achieved owing to the homeothermic properties and the possibility of spike-induced synaptic behaviors was demonstrated, both presenting critical milestones for the use of emerging memristor-type neuromorphic computing systems in the near future. Biological synaptic behaviors, such as long-term potentiation, long-term depression, and spike-timing-dependent plasticity, are developed systematically, and comprehensive neural network analysis is used for temperature changes and to conform spike-induced neuronal dynamics, providing a new research regime of neurocomputing for potentially harsh environments to overcome the self-heating issue in neuromorphic chips.

Oxide based resistive switching memory are the promising candidates for future non-volatile memory according to fast programing, low power operation, scalability and compatibility to the current CMOS process. Among, SiOx single layer resistive switching devices have been widely studied and characterized. The SiOx single layer resistive memory has good compatibility to CMOS fabrication process. However, it can only be programmed under the vacuum or non-oxidized ambient. Also, the previous results reported on SiOx-based memristors indicate that the electroforming and programming voltage is relatively higher than the other dielectric materials and obstructed for low-power applications. In this work, by using SiOx/HfOx stacking engineering, we have developed a low-voltage operation (< 2V) for SiOx-based ReRAM. The results show that with HfOx (3nm) on bottom, the metal-insulator-semiconductor (MIS) structures exhibit resistive switching at low voltage (x-based MIS devices which exhibit bipolar-type resistive switching behaviors with small memory window.Clearly, SiOx/HfOx stacking optimization not only maintains the RS behaviors even in air environment without any programming window degradation, but also further reduces the switching voltage below 2V. Figure 1 shows the results of three different structures, including SiOx single layer memristor, SiOx/HfOx bilayer memristor and HfOx single layer memristor. In terms of operation environment condition, inserting the HfOx layer would help the SiOx memristor to be able to programmed either under a pressure of 1E-4 torr or in the atmosphere. The HfOx single layer memristor has the lowest electroforming voltage of 2.3 V, and which in SiOx/HfOx stacks has been reduced significantly to 5 V comparing which of 14 V for SiOx single layer. For the SiOx/HfOx bilayer, a memory window of 4 decades is achieved and comparable to that of SiOx single layer, and larger than that of single layer HfOx by 2 decades. In terms of operation voltage, the set voltage is reduced from 4V to 2 V and the reset voltage is also suppressed significantly from 10 V to 0.3 V by inserting the 3 nm HfOx layer. Figure 2 shows the TEM images of both SiOx single layer memristor and SiOx/HfOx bilayer memristor. The 3 nm HfOx was deposited on N+ Si wafer at 250 oC by atomic layer deposition followed by 30 nm SiO2 deposition using e-beam evaporator and 160 nm TaN depositing by sputtering. Figure 3. The single layer HfOx-based MIS devices resistive switching behaviors. (a) The electroforming process, resistive switching behaviors in 20 times cycling. (b) The switching voltage (SET/RESET) and states (HRS/LRS) distribution. Figure 1