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We designed logic cells hardened for single-event upsets/single-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKI's 0.15 /spl mu/m fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. Our previous work demonstrates that SET-free inverters can be successfully applied as SEU-immune latches. In this paper, the native latches are redesigned using SET-free inverters not only for the inverter loop but also for several types of clock gates (L-SETfree-LoopCK, L-SETfree-LoopCK-SmallArea, and L-SETfree-LoopCK-AddTr.). In addition, the native combinational logic cells are redesigned using SET-free inverters as SET-free NAND and SET-free NOR . Excellent SEU/SET hardness of the HBD latches were achieved up to LET of 64 MeV/(mg/cm/sup 2/).

We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 /spl mu/m Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SEEs.

We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 /spl mu/m CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs.

Proton and heavy-ion SEU testing are performed on commercial 4 M bit-SRAMs and 64M bit-DRAMs. Correlation between proton and heavy-ion SEUs is examined and an empirical equation has been derived between proton SEU cross-section and heavy-ion threshold-LET.