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Single-event effects in 0.18 /spl mu/m CMOS commercial processes
- Source :
- IEEE Transactions on Nuclear Science. 50:2135-2138
- Publication Year :
- 2003
- Publisher :
- Institute of Electrical and Electronics Engineers (IEEE), 2003.
-
Abstract
- We evaluated SEEs in sample circuits fabricated at TSMC and Fujitsu with their 0.18 /spl mu/m CMOS commercial processes. The samples were designed with hardness-by-design methodology. The results were discussed for effective hardening design associated with SEEs.
- Subjects :
- Nuclear and High Energy Physics
Engineering
business.industry
Electrical engineering
Hardware_PERFORMANCEANDRELIABILITY
Nuclear Energy and Engineering
CMOS
Hardware_INTEGRATEDCIRCUITS
Electronic engineering
Hardware_ARITHMETICANDLOGICSTRUCTURES
Electrical and Electronic Engineering
business
Hardware_LOGICDESIGN
Electronic circuit
Subjects
Details
- ISSN :
- 15581578 and 00189499
- Volume :
- 50
- Database :
- OpenAIRE
- Journal :
- IEEE Transactions on Nuclear Science
- Accession number :
- edsair.doi...........98190ada306b47d743867c07bbdd159f
- Full Text :
- https://doi.org/10.1109/tns.2003.821830