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Although chip-level heterogeneous integration has high yield for production, low-throughput issue of chip-to-wafer bonding is necessary to be improved. Due to the uneven topography and small chip size, handling issue and alignment accuracy are important factors that impact the difficulty in heterogeneous integration. Self-assembly technology has a high potential to be applied in 3-D heterogeneous integration. By using hydrophobic film to define the stacking area, hydrophilic chips can be assembled to realize alignment process on these areas through wafer surface tension in a very short time. With this concept, double-self-assembly technology is accomplished to resolve both handling and alignment issues for uneven-topography-chip integration. In this paper, different chip sizes of $\mu $ -pillar are simulated to investigate the optimal water volume for double-self-assembly process. High alignment accuracy of misalignment measurement can be accomplished with the optimal water volume. Furthermore, microstructure of Cu/In bonded structures and corresponding electrical analyses are evaluated, while various reliability tests are investigated for bonding quality. Excellent results verify that the double-self-assembly technology could be applied to 3-D heterogeneous integration for uneven-topography-chip integration.

This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5- $\mu \text{m}$ -diameter/50- $\mu \text{m}$ -length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12- $\mu \text{m}$ diameter are bonded using three step temperature bonding profile. Further stacked DRAM/Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.

With increasing demand for mobile devices to be lighter and thinner and consume less power while operating at high speed and high bandwidth, many equipment suppliers and assembly participants have invested great efforts to achieve fine-line fan-out wafer-level packaging (FOWLP). However, the inherent warp of reconstituted wafers, which can contribute to poor die placement accuracy and/or delamination at the interface of the build-up layer and carrier, remains a major challenge. In this study, the interactions among laser release layer, glass carrier, and build-up layer were evaluated for optimization of redistribution layer (RDL)–first FOWLP as a foundation to move toward fine-line FOWLP. In this study, a series of experiments incorporating glass carrier, laser release layer, and build-up layers were carried out to determine the optimal setup for RDL-first FOWLP. First, glass carriers (300 mm × 300 mm × 0.7 mm) with coefficients of thermal expansion of 3 and 8 ppm/°C were treated with 150-nm laser release layers. After deposition of 0.1 μm of sacrificial material on the glass carrier, 8-μm build-up layers were coated and patterned by lithography to electroplate Cu interconnections with a density of approximately 10% of the surface area. Subsequent to die attachment, molding compound was applied on top to form a 200-μm protective overcoat. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 308-nm laser to complete the design of experiments (DOE). An experiment to study the correlation of glass carrier, laser release layer, build-up layers, and molding compound in RDL-first FOWLP processes is discussed to address full process integration on 300-mm glass substrates. The combination of glass carrier, laser release layer, build-up layer, and molding compound will pave the way for realizing cost-effective RDL-first FOWLP on panel-size substrates.

Fan-out wafer-level-packaging (FOWLP) technology has been developed with various advantages, such as smaller form factor, lower cost, and simplified supply chain for heterogeneous integration. There have been several process schemes like chip-first or chip-last FOWLP integration discussed widely in conferences in recent years. One process in all of these process schemes has in common is the use of a temporary carrier for subsequent redistribution layer (RDL) formation, chip stacking and molding processes. Although the separation of a temporary carrier from the reconstituted wafer could be achieved without significant hurdles, there were few studies addressing optimization of carrier separation for throughput enhancement. Thus, this paper is designed to address the needs in optimizing carrier separation process based upon laser ablation technology. Two phases of experiments were designed to select the appropriate laser release layer and define optimal laser settings. The first experiment was used to evaluate correlation of the laser absorption, laser energy, and spot pitch versus completeness of laser ablation. The second experiment included RDL-first FOWLP integration. At first, 300-mm glass carriers (1000 µm thick) with coefficient of thermal expansion of 8 ppm/oC were treated by selected laser release layers. After deposition of 0.05-µm Ti/0.15 µm Cu on the glass carrier, passivation of around 8 µm was coated and patterned by lithography for electroplating Cu interconnections with a density of approximately 10% of the surface area. Subsequently, die bonding, build-up layers, or molding compound were applied on top to form a 200-µm reconstituted wafer. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 355-nm laser to determine optimal throughput. Experiments to study correlation of laser release layer with laser settings along with a demonstration of full RDL-first FOWLP integration are discussed thoroughly to address the need of throughput enhancement, which could serve as cornerstone for realizing cost-effective RDL-first FOWLP.

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

During the field service of composite insulators, high temperature vulcanized (HTV) silicone rubber (SIR) material used for insulator’s sheath and sheds is gradually aging, and thus how to effectively evaluate its aging state has become an inevitable issue. In this paper, artificially corona-aged and naturally site-aged SIR materials are employed as samples, and their properties such as hydrophobicity, leakage current, trap density/energy level, surface microstructure and chemical composition are investigated for comparative study. With the increasing of corona aging intensity, the contact angle of SIR samples drops gradually and recovers more slowly. The hydrophobicity of site-aged insulators also declines, from HC1 for 2-year service to HC5 for 15-year service. The leakage current of corona-aged and site-aged samples both increase with aging, which indicates that aging induces the increase of surface conductivity of SIR material. The peak trap density of corona-aged and site-aged samples increases with the aging duration or service duration remarkably. The changes of these properties are attributed to the changes of micro-structures and compositions in the surface layer of SIR. The scanning electron microscope (SEM) and X-ray photoelectron spectroscopy (XPS) analysis results reflect that a hardened inorganic silica-like (SiO2) layer with many polar chemical groups and distributed micro-pores is formed on the surface of SIR material after corona aging. Because of this silica-like layer, the hydrophobicity decreases while surface conductivity and trap density of SIR material increases. Besides the traditional properties like hydrophobicity and surface conductivity, the trap density is expected to be a novel parameter for effective evaluation of aging state of HTV silicone rubber material.

Fan-out wafer-level-packaging (FO-WLP) technology is developed with the advantages of smaller package size, higher Input/Output (I/O) counts, lower cost, and better performance. In this study, the FO-WLP technology is applied to TSV-less inter-connection technology of 2.5D IC packaging and a novel RDL-first wafer level packaging is demonstrated. Firstly, a pre-coated laser release layer at the interface of RDL and carrier wafer is used for the separation of the reconfigured wafer and carrier wafer with laser de-bonding technology. Since release layer material is the key factor for de-bonding, these materials are evaluated to determine the quality. Test chips are flip-chip bonded onto a carrier wafer with 2 layers of RDL and passivation, following by wafer molding process. Wafers reveal a warp surface due to chemical material shrinkage and CTE mismatch during post mold curing. Warpage of molded wafer is needed to be optimized for equipment handling and the warpage characterization is collected to analyze by different processes. To examine the quality of the structure, electrical measurement is carried out and their respective results are presented.

Dielectric window is an important component of high-power microwave (HPM) devices. However, surface breakdown easily occurs at the vacuum/dielectric interface when HPM pass through the dielectric window. This greatly limits transmission of HPM and makes the window a bottle neck of HPM technology development. Secondary electron emission (SEE) from dielectric window plays an important role in its surface breakdown. This paper studies the total SEE (including true secondary electrons and backscattered electrons) coefficients of several inorganic and organic dielectric materials including polytetrafluoroethylene, polyethylene, alumina ceramic, and machinable ceramic. The measurements are implemented by using pulsed electron beam impacting the materials with energies from 200 eV to 5 keV. In addition, surface desorbed gas property is studied with the quadrupole mass spectrometer. The performances of different materials are evaluated. The obtained results are useful for the selection of HPM window materials.

In this paper, we investigate reliability testing for a glass interposer. The test vehicle is an assembled glass interposer with a chip, a BT substrate. The structure of a glass interposer with two redistribution layers (RDLs) on the front-side and one RDL on the back-side has been evaluated and developed. Key technologies, including via fabrication, front-side RDL formation, microbumping, temporary bonding, glass thinning, and back-side RDL formation, have been developed and integrated for high performance. The BT substrate design and PCB for electrical characterization of reliability tests are reported in this paper. The results indicate that this glass interposer can be integrated. The data show the feasibility of this glass interposer for electronics applications.

In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass thinning and backside RDL formation, were developed and integrated to perform well. The BT substrate design and PCB for electrical characterization of reliability tests are included as well. The results indicate that the device with the glass interposer can be integrated and there is also data showing the feasibility of the glass interposer for electronics applications.

This paper describes a handling process for a thin glass panel, 200 mm × 200 mm × 130 (im, through double-side redistribution layer (RDL) formation to enable cost-effective fabrication of through-glass-via (TGV) interposers. The integration scheme includes lamination of a low-temperature bonding material utilizing a lamination process temperature of less than 100°C to bond a thin (130-μm) glass panel onto a carrier glass panel 700 μm thick. The carrier glass panel is treated with a 150-nm laser release layer prior to lamination of the bonding film and subsequently the thin glass panel. Next, the RDL is formed, and the front side of the thin glass panel undergoes aluminum physical vapor deposition (PVD) and polymeric dielectric material deposition. Then a second carrier glass panel, treated with the laser release material and laminated with bonding film, is bonded on the front side of the thin glass panel. An excimer laser with an x-y scanning stage is rastered across the first carrier to ablate the laser release layer for separation of first carrier. Following laser separation, a solvent cleaning step is performed to remove bonding material from the backside of the thin glass panel. The process of applying metal PVD, lithography, and dielectric material is repeated on the backside of the thin glass panel. Finally, the thin glass panel is mounted to tape, and the second carrier glass panel is released using laser ablation to reveal the front side of the thin glass for solvent cleaning and final inspection. The integration of the dry bonding film, thin glass panel lamination, and selective laser debonding technology in this study will pave the way for realization of panel-level packaging in the near future.

In this paper, we investigated the assembly characterization for reliability test. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, glass thinning and backside RDL formation, were developed and integrated to perform well. The BT substrate design and PCB for electrical characterization of reliability tests are included as well. The results indicate that the device with the glass interposer can be integrated and there is also data showing the feasibility of the glass interposer for electronics applications.

Interposer fabrication processes are applied in three-dimensional (3-D) integrated circuit (IC) integration to shorten the interconnection among different stacked chips and substrates. Because Si is a common material in semiconductor technology, Si interposers have been widely studied in many research activities. Compared with a Si wafer, glass substrates have the advantages of high resistivity, low dielectric constant, low insertion loss, adjustable coefficient of thermal expansion (CTE), and the possibility to use panel-size substrates as well as thin glass substrates (100 µm) to avoid the costly thinning process for realization of low-cost 2.5-D ICs. Thus, glass interposer fabrication is studied thoroughly in this paper.

In this research, the wafer level Cu/BCB hybrid bonding with TSV for 3D integration by using fly cutting technology is proposed. As we know Cu bump surface is rough by electroplating, and BCB is spin-coated on Cu bump wafer induced high topography. Cu bump surface roughness and Cu/BCB co-planarization are improved by fly cutting to achieve good Cu to Cu and BCB to BCB bonding interface without any large bonding voids at 250°C for 30min, and the result of the bonding strength is evaluated by shear test. TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation are well developed and integrated to perform the 3D integration platform. Cu/BCB hybrid bonding with TSV for 3D integration is successfully developed and demonstrated in this paper.

Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with $\mu$ -probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of $\mu$ -probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 $\times$ 24 $\mu$ -probe array with embedded TSVs is fabricated on a $5\times 5\ {\rm mm}^{2}$ chip and bonded on the back side of the interposer. Thus, each channel contains 6 $\times$ 6 $\mu$ -probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus ( $\mu$ -SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 $\mu{\rm W}$ for 16-channel neural sensing.

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

In this research, a backside illuminated CMOS image sensor (BSI-CIS) without through-silicon via and TSV based Si interposer are developed with thin wafer handling technology. The BSI-CIS wafer is implemented front-side processes then temporary bonded on a Si carrier by using ZoneBOND™ technology. After thinning, the CIS backside is bonded with glass wafer, and the Si carrier is removed using solvent dipping for de-bonding. The thickness of BSI-CIS without TSV is less than 5um, which is visible light transparent to meet the back-side illumination requirement. TSV fabrication, void-free TSV filling, bumping, wafer thinning, thin wafer handling and backside RDL formation are well developed and 30um TSV, 60um thin wafer have been successfully integrated to Si interposer. Cu/Sn bumps with 50µm size are formed with the bump height uniformity less than 5% in wafer level. The wafer-level package of BSI-CIS and TSV based Si interposer have been successfully developed and demonstrated, the characterization results of three layer stacked module is also disclosed in the paper.

The charge accumulation on the surface of dielectric materials is a long-term academic research focus. As part of an effort to understand the origins of this behavior, surface charge distribution on silicon rubber under DC high voltage before and after flashover in atmosphere was measured by an electrostatic voltmeter with a vibrating Kelvin probe. Three types of electrode systems were employed in the study, i.e. circle-circle electrodes, ellipse-circle electrodes and tip-circle electrodes. The results showed that surface charging processes are close related with uniformity of electric field and voltage polarities. Once flashover happens, there exists a channel linking HV and grounded electrodes, which presents a low potential.

Through glass via (TGV) interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and substrate. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed and there are many challenges for processing. For process, the major differences between Glass and Si interposer are method for via formation and isolation. The test vehicle for Glass interposer is successfully processed. Glass material is composed with SiOx, it is good isolation for electrical current. The polymer-based PBO is used for passivation. For structure of glass interposer, there is one RDL on the front-side and backside, respectively. The other structure is 2 RDL on the front-side and one RDL one the backside. The CD of through glass via is 30 μm, it is formed by Corning Co. Cu overburden and Ti barrier are removed by wet etching process. For top RDL (line-width = 20μm), Cu plating process with seed layer (Ti/Cu) wet-etching process is applied. The PBO material is used for passivation, the process temperature is blow 200°C. Top UBM (15μm in diameter; 4μm/5μm-thick Cu/Sn) is formed with a top passivation opening (15μm). The structure is analyzed and demonstrated by SEM analysis. All the results indicate that the glass interposer with polymer passivation can be preceded and the cost for process is cheaper than Si interposer.

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristics and is potentially to be applied for 3D product applications.

Charge traps greatly affect the charge transport, trapping and recombination in solid dielectrics such as ceramics and polymers. This paper presents a novel method of measuring the surface trapping parameters such as trapping density and energy level of insulating materials. Based on the isothermal relaxation current (IRC) theory, the trap measurement and calculation formula is deduced and a non-contact measurement setup is specially designed, and electron or hole trap parameters can be determined by choosing negative or positive charging, respectively. Two kinds of materials are selected as the samples, i.e., high temperature vulcanized (HTV) silicone rubber and machinable ceramics (MCs). Experimental results indicate that, with extending duration of aging time, electron and hole trap density both increase, and gradually saturate. SEM and XPS analyses reflect that specimens after aging process appear many physical defects as holes and flaws and chemical defects as strong polar groups, which causes significant influence on surface trap characteristics. It is shown that the glass phase on the surface of MCs greatly influences the existing shallow traps, which in turn degrade the fla-shover characteristics. Removing the glass phase with HF treatment reduces the concentration of shallow traps and stabilizes the flashover voltage. It is considered that charge trap is expected to be as a novel indicator for effective evaluation of aging status and electric withstanding strength of insulating materials.

At present, composite insulator is widely used in the power system, and its safe operation is seriously affected by its aging condition. In order to research the aging feature of composite insulator material, this paper analyzes the surface characteristics of composite insulator after accelerated aging process via corona discharge, including surface hydrophobic, trap parameters and chemical components based on X-ray Photoelectron Spectroscopy (XPS), etc. It is revealed that, with the enhancement of corona discharge along with applied voltage and time etc, the hydrophobic property continuously decreases, trap parameters regularly changes, and surface chemical results show that content of hydrophobic micro groups decrease than before. The XPS analysis can be used to well explain the aging mechanism. With the aggravation of aging condition of composite insulator, its surface trap density gradually increases, which could be considered as a novel aging characterization parameter of composite insulator.

For identifying electron and hole traps in polymeric materials, we combine the isothermal relaxation current theory and surface potential decay together and present a model called isothermal surface potential decay (ISPD). A non-contact measurement setup is specially designed, which features that energy distribution of electron or hole-type traps can be discriminated with negative or positive corona charging, respectively. By measuring the ISPD characteristics of low-density polyethylene and polypropylene films, their trap distributions are obtained, revealing the different semi-crystalline morphology of these two materials. The results we obtained may imply the essentially distinct nature of electron/hole traps: inter-chain for electron-type traps and intra-chain for hole-type traps, which is in agreement with other researchers' molecular modeling results.

3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.