Search

Conventional di/dt and dv / dt control and gate protection techniques for gallium nitride (GaN) power transistors usually employ external controllers, isolation circuits, discrete pull-up, and pull-down resistors. With large number of components, power modules become more complex and may introduce additional parasitic. Gate driver ICs with segmented output stages and dynamic gate driving have been reported previously to be effective in simultaneously suppressing gate ringing and overshoot voltage while maintaining fast switching speed. However, the programming for dynamic gate driving is rather complicated, requiring the user to load a sequence of driving patterns obtained from trial and error ahead of time. This article presents a gate driver IC for E-mode GaN power transistors with seven segmented output stages. More importantly, it offers a simplified programming method for the dynamic gate driving pattern. The optimal gate drive pattern can be defined by simply adjusting one external bias resistor. The proposed method eliminates the complex trial and error digital control, and can potentially promoting the wider acceptance of dynamic gate driving by the industry. The timing resolution for the gate drive pattern can be varied in steps from 0.5 to 5 ns. It can also be used to drive many commercially available GaN power transistors.

The compare operation is widely used in many applications, from fundamental sorting to primitive operations in the database and AI systems. We present SRAM-based 3-D-CAM circuit designs using a monolithic 3-D (M3D) integration process for realizing beyond-Boolean in-memory compare operation without any area overheads. We also fabricated a processing-in-memory (PiM) macro with the same 3-D-CAM circuit using M3D for performing massively parallel compare operations used in the database, machine learning, and scientific applications. We show various system designs with the 3-D-CAM supporting operations, such as data filtering, sorting, and sparse matrix–matrix multiplication (SpGEMM). Our systems exhibit up to $272\times $ , $200\times $ , and $226\times $ speedups and $151\times $ , $37\times $ , and $156\times $ energy savings compared to systems using near memory compute for the data filtering, sorting, and SpGEMM applications, respectively.

With careful planning and a focus on developing expertise, government policy has helped Taiwan become a centre for semiconductor innovation.

Device degradation due to hot carrier injection (HCI) in multi-fin 20 nm and 10 nm N- and P-type FinFET devices are thoroughly analyzed. To further understand the HCI reliability of the four FinFET devices, the device is fabricated with a standard Vt base and low Vt base gate stacks with different work functions. It is evident that: (i) The standard Vt device sustains lower effective stress bias due to the difference in threshold voltage, resulting in a more stable threshold voltage than the low Vt base device, and (ii) the transconductance of the single N- and P-type FinFET is more severely degraded than the multi-fin N- and P-type FinFET, mainly because multi N- and P-type Finfet has coupe effect, which effectively reduces the impact of HCI.

Device degradation due to hot carrier injection (HCI) in different Y-gate HEMT devices is thoroughly analyzed. To further understand the HCI reliability of the Y-gate HEMT devices, the device is fabricated with AlGaN/GaN structure with different top lengths (Ltop). An HCI stress time of 6000 s was conducted on these devices, while V t stability in other stress time domains, leakage current, and transconductance degradation are also discussed. In this work, we have demonstrated that increasing the LTop length could avoid the virtual gate effect and disperse the influence of the electric field under HCI stress. Furthermore, the effects of trapping in various locations, such as in the bulk SiN or AlGaN/GaN interface has been discussed. These trapping effects caused by the HCI stress might be the source of the Vth shift. Overall, The large Y-gate HEMT showed the lowest degradation of DC characteristics after the long HCI stress test.

High-k metal gate technology improves the performance and reduces the gate leakage current of metal–oxide–semiconductor field-effect transistors (MOSFETs). This study investigated four different work function metal (WFM) stacks in the gate of fin field-effect transistors (FinFETs) on the same substrate. These devices not only successfully produced distinct levels of threshold voltages (|Vt|) but also converted n- to p-type features merely by adding p-type WFM in the gate of the MOSFETs. All of the devices satisfied short-channel effects with shrinking channel length. The gate-to-body electric field induced drain leakage due to the nature of bulk FinFETs. However, the n- and p-type gate stacks presented different gate current leakage. For reliability, hot carrier injection (HCI) could have a higher reliability impact than the negative-bias temperature instability (NBTI) for p-MOSFET, although the stress voltage of HCI was roughly half that of the NBTI test. This multi-threshold voltage tuning allows designers to design CMOS and choose the trade-off between low power consumption and high performance on the same platform.

In this study, the device characteristics of dual-gate GaN high-electron-mobility transistors (HEMTs) were determined. The research investigated an enhancement-mode (E-mode) GaN HEMT with a second gate connected to the source and located between the main gate and drain. Two dual-gate GaN HEMTs with different second-gate designs, using Schottky or metal–insulator–semiconductor (MIS) contacts, were simulated and fabricated, and the direct current of the devices was investigated. In device simulation, p-GaN gates were used to achieve E-mode operation in HEMTs. Technology computer-aided design (TCAD) simulation indicated that the saturation drain current (ID, sat) of devices with Schottky and MIS second gates was 88% and 38% lower than that of a single gate structure, while increasing on resistance (Ron) by 31% and 8%, respectively. In device fabrication, a Schottky and MIS second gate were respectively added to an E-mode p-GaN gate HEMT and an E-mode recesses-gate GaN MIS-HEMT. Compared with single-gate structures, the devices with a Schottky and MIS second gates reduced ID, sat by 75% and 32%, respectively, while increasing Ron by 25% and 6%, respectively. The measured electrical characteristics indicate the same trend obtained from TCAD simulation: The dual-gate design can improve the short-circuit capability of GaN HEMTs by reducing the ID, sat under on-state and high-current conditions.

AlGaN/GaN-HEMT with Single to Multi-step gate field plate is proposed in this work. The proposed device enhanced Drain current, breakdown voltage and shift in threshold voltage. The performance of proposed device is analyzed and compared with experimental step device with and without Field Plate (FP). Reduction of current collapse effects is proved with Multi Gate Step field Plate in AlGaN/GaN HEMTs. The performance of the devices is analyzed using Technological Computer Aided Design (TCAD). In the simulation, polarization, mobility, recombination and impact ionization models are used. The electric field, potential and current density of the GaN-HEMT are analyzed. From the TCAD simulation, GaN-HEMT with increment in-step FP yields higher breakdown voltage than that of other FP techniques. Hence, the proposed GaN-HEMT is an outstanding candidate for future high power application.

A high-quality HfGeOx interfacial layer (IL) was formed in a HfO₂/Al₂O₃/HfO₂/GeOx gate stack through thermal annealing. The diffusing of GeO into the HfO₂ layer led to the mixing of the GeOx and HfO₂ layers, as identified through energy-dispersive X-ray Spectroscopy (EDX). X-ray photo-electron spectroscopy (XPS) data for HfGeOx IL confirmed the formation of Ge-O-Hf bonds owing to the induced shift of the Ge3dox spectra to lower binding energies. The electrical and reliability data indicated that the capacitor with HfGeOx IL presented not only lower interface states density (Dit, approximately 7 × 1011 eV-1cm-2) but also less Dit increment (approximately 3 × 1011 eV-1cm-2) after stressing than did the capacitor without the HfGeOx IL. Moreover, the Ge p-metal-oxide-semiconductor field-effect transistor HfGeOx IL exhibited a high effective hole mobility (approximately 704 cm2/V s).

In this work, the components of fin top and fin sidewalls of tri-gate fin field-effect transistor (FinFET) were distinguished and extracted by a proposed method to find out the characteristic and reliability. Poor fresh characteristic could be found on fin sidewall area due to the existed surface defects after the fabrication the Si etching process. After NBTI stress, larger VTH shift and severe SS degradation reveals worse reliability on fin top area. The result indicates that the poor initial characteristics of the fin sidewalls will reduce the performance of tri-gate FinFETs, but the poor reliability of the fin top determines the overall degradation of the device.

In this paper, the effect of carrier quantization on device characteristics and stress-induced device degradation for multifin high- ${\boldsymbol \kappa }$ /metal tri-gate n-type and p-type fin field-effect transistors (FinFETs) were investigated through electrical characterization and simulation. Carrier conduction in the steep Si fins of FinFETs is different for devices with different numbers of fins and affects device performance and reliability. For n-type FinFETs, devices with fewer fins inhibited the coupling effect between fins to exhibit superior device performance but underwent more severe hot carrier–induced device degradation. The coupling effect between fins reduced the equivalent electric field in the multifin devices and further inhibited impact ionization; thus, devices with more fins achieved superior reliability to single-fin devices after hot-carrier stress. For p-type FinFETs, a similar effect on performance was demonstrated but with lower sensitivity to hot-carrier stress-induced device degradation caused by lower hole mobility within the Si fin channel.

Molecularly imprinted polymer (MIP)-based electrochemical sensors for the protein α-synuclein (a marker for Parkinson's disease) were developed using a peptide epitope from the protein. MIPs doped with various concentrations and species of transition metal dichalcogenides (TMDs) to enhance conductivity were electropolymerized with and without template molecules. The current during the electropolymerization was compared with that associated with the electrochemical response (at 0.24~0.29 V vs. ref. electrode) to target peptide molecules in the finished sensor. We found that this relationship can aid in the rational design of conductive MIPs for the recognition of biomarkers in biological fluids. The sensing range and limit of detection of TMD-doped imprinted poly(AN-co-MSAN)-coated electrodes were 0.001-100 pg/mL and 0.5 fg/mL (SNR = 3), respectively. To show the potential applicability of the MIP electrochemical sensor, cell culture medium from PD patient-specific midbrain organoids generated from induced pluripotent stem cells was analyzed. α-Synuclein levels were found to be significantly reduced in the organoids from PD patients, compared to those generated from age-matched controls. The relative standard deviation and recovery are less than 5% and 95-115%, respectively. Preparation of TMD-doped α-synuclein (SNCA) peptide-imprinted poly(AN-co-MSAN)-coated electrodes.

Stacked Ge nanosheets (NSs) GAA FET CMOS inverters are demonstrated for the first time. In this work, for formation of well-defined stacked Ge NSs, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material for the following better selective etching between Ge/Si. In order to avoid island growth, Ge/Si multilayers must be grown at a low temperature. For selective etching, we found that, at a proper temperature, the Si layers can be easily etched away over Ge layers with good selectivity by TMAH solution. Additionally we found the dislocations in suspended Ge sheets are more easily to be removed than the case that Ge layers are still tied with Si layers. Finally, a functional Ge NSs GAAFET CMOS inverter with maximum voltage gain of 25V/V was demonstrated.

A single-crystal-island (SCI) technique is demonstrated using low thermal budget pulse laser process to fabricate single-crystal islands for monolithic 3D back-end-of-line (BEOL) FinFET circuits. The single-crystallinity are verified with SECCO etch, HREM, TEM, and EBSD. BEOL FinFETs fabricated in the designed single-crystal Si islands exhibit excellent electrical performance and low intra-island variability. To mitigate the effects of island-to-island device variation due to random island crystal orientations, crystal-orientation-tolerant voltage regulator is further proposed by allocating power gating (PG) cells among multiple Si islands, and 42% power noise suppression can be achieved.

This paper demonstrates the first Monolithic 3D+-IC based Compute-in-Memory (CiM) Macro performing massively parallel beyond-Boolean operations targeting database and machine learning (ML) applications. The proposed CiM technique supports data filtering, sorting, and sparse matrix-matrix multiplication (SpGEMM) operations. Our system exhibits up to 272x speedup and 151x energy savings compared to the ASIC baseline.

For the first time, ultrafast laser annealed BEOL gate-all-around (GAA) transistor and FeFET memory were demonstrated with monolithic 3D near-memory-computing (NMC) circuit. The GAA MOSFETs employing ultrafast picosecond visible laser dopant activation exhibit record-high Ion (nFETs=407 uA/um, pFETs=345 uA/um). The BEOL FeFETs memory exhibits large memory window ΔV th = 1.2V, more than 106 cycle endurance. Moreover, the 3D stackability of the GAA MOSFETs and FeFET memory bit cell enable reduces the area of the NMC circuitry and improve the readout throughput.

For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.

In this work we propose a first attempt in the fabrication of a family of monolithic GaN-based quaternary multi-value logic gates (MVL), including QNOT, QNOR, and QNAND in a process flow compatible with enhancement mode (E-mode) power HEMT (BV > 650 V). Integration of MVL with GaN power HEMTs increases logic-state density and allows for the design of smart gate drive circuits with reduced switching loss and ringing when compared to circuits using discrete devices. Using TCAD and SPICE device models calibrated against experimental data we demonstrate the functionality of a quaternary inverter with noise margins NML and NMH above 60% and 50% of the logic state voltage range, respectively. Quaternary logic gates show an average reduction of 27% in area utilization when compared to binary logic gates. Additionally, the layout of a quaternary 16-bit DEMUX circuit is projected to occupy 22.5% less area than its binary equivalent. The application of quaternary MVL to digital control circuits for GaN power HEMTs is expected to reduce total circuit area and consume less power than a binary counterpart.

Horizontally stacked Ge nanosheet GAA FETs are demonstrated, although Si, SiGe and GeSn stacked nanosheet FETs have been reported. The problem for formation of stacked pure-Ge nanostructures is that the Ge material is weaker than other IV group materials, and securing Ge material by selective etching away other IV group materials is difficult. In this work, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material, because the large difference of material properties between Ge/Si is beneficial to the following selective etching process. In order to avoid island growth, Ge/Si multilayers must be grown at a low temperature. For selective etching, we found that, at a proper temperature and with assistance of megasonic agitation, the Si layers can be easily etched away over Ge layers with good selectivity by TMAH solution. Additionally we found the dislocations in suspended Ge sheets are more easily to remove than the case that Ge layers are still tied with Si layers. Finally, the devices with gate length of 80nm were fabricated, and current of over $1650\mu A/\mu m$ (per width of channel footprint) was achieved.

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 &deg, C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 &micro, A/&micro, m (n-type) and 297 &micro, m (p-type) @ Vth &plusmn, 0.8 V, and higher Ion/Ioff (&gt, 105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(&Omega, )-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $\mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3}\ \mathrm{A}/\mathrm{W})$ and tunable photogain (10 2 ~10 5 ) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.

Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

For the first time, below 400°C-fabricated poly-Si MOSFETs and 6T -SRAM fabrication process was demonstrated on polyimide (PI) substrate for flexible and transparent monolithic 3DIC. Key enablers are 400–900 nm transparent laser-stop layer (LsL), laser-crystallized/CMP-thinned poly Si channel and pulse UV-laser S/D activation. These advanced low thermal budget fabrication technologies enable stackable polySi MOSFETs on flexible 6” -wafer-scale PI substrate with high device uniformity $(\mathrm{V}_{\mathrm{th}}$ ‘SS~16.2%/16.6%) and bending stability $(\mathrm{V}_{\mathrm{th}}/\mathrm{SS}\sim 4.2\%/9.8\%)$ after cycle-bending at radius of 10mm. Such CMOS compatible technologies envision flexible 3D heterogeneous integration of circuits/optical sensors for human-skin adaptable Internet of Things (IoT) chips.

The performance of AlGaN/GaN High Electron Mobility Transistor (HEMT) has challenges to drive the drain current of the device. Varying device materials, Field plate structure, and current collapse degradation are some techniques involved in improving device capabilities. Strain-induced Ionic polarization utilizes the piezotronic effect for tuning the movement of charges with the induced charges at the semiconductor interfaces. In this paper, Stain- induced piezotronic effect is created at the AlGaN/GaN interface or the channel by applying external pressure on top of the HEMT device. Finite element analysis simulation (FEA), Schrodinger-Poisson equation models are used for the simulation of the carrier transport charges at the device. The DC Characteristics such as Transconductance(gm), IdVg are observed and the enhancement of drain current is observed at an applied external pressure of 0 N, 10 N, and 15 N at constant gate voltage(Vgs=0 V). Furthermore, improved drain current is observed by varying the gate drain-source voltage (Vds) for constantly applied pressure at 0 N and 15 N. This research confirms the influence between the piezo-electric effect and two-dimensional electron gas 2-DEG formation, which enhances the device performance in AlGaN/GaN Interface.

his paper investigates the substrate bias effects on a monolithically integrated half-bridge fabricated using lateral GaN-on-Si technology. The dynamic characteristics, including dynamic R on degradation and gate charge (Q g ) shift, are presented for both high- and low-side GaN power devices. Compared to the grounded substrate, significant dynamic R on degradations and decreased Q g are observed in high-side GaN power devices under negative DC substrate biases. Pulse-mode substrate biasing has also been studied with suppressed degradation by eliminating the cross-talk effect. The trade-off between dynamic R on degradation and Q g shift has been explored under different switching frequencies for a monolithically integrated GaN half-bridge.

Breakdown characteristic of GaN-HEMT with field plate (FP) technique is investigated. Source field plate length (LFP) is varied and its impact on breakdown voltage is studied. The investigation of GaN-HEMT is carried out using Technology Computer Aided Design (TCAD). Various physical models such as mobility, polarization and recombination models are used to tune the simulation. It is observed that breakdown voltage enhances source field plate length. It is also observed that VBR shows less dependency for LFP > 4µm.

This letter represents the first direct experimental demonstrations and mechanism proposal regarding abnormal palladium diffusion into germanium (Ge). Our experiments indicated that excess Ge atoms among palladium germanide alloy formation indirectly induce the abnormal out-diffusion of mass palladium atoms into Ge. Consequently, palladium germanide alloy on both n-type and p-type Ge form ohmic-like Schottky junctions. To identify this phenomenon, first-principle calculations and technology computer-aided design simulation were used to evaluate the electrical influence of palladium atoms in Ge. We discovered that the activated palladium atoms in Ge induce large midgap bulk-trap states, which contribute to a severe increment of trap-assisted tunneling current at the palladium germanide/Ge junction.

For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.

For the first time, below 400°C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I on /I off ratio (~108) with low I off (pFETs

Horizontally stacked Ge-nanosheet gate-all-around FETs (GAAFETs) are demonstrated for the first time. The Ge/Si multilayers instead of the typically used Ge/SiGe ones were epitaxially grown as the starting material. To avoid island growth, the Ge/Si multilayers were epitaxially grown at a low temperature. Using megasonic agitation, the Si in Ge/Si multilayers can be easily etched with good selectivity using a tetramethylammonium hydroxide water solution at an appropriate temperature. Finally, the p- and n-GAAFETs of gate length ( ${L}_{G})$ 90 nm were fabricated, and drive currents ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of 1650 and $1510~\mu \text{A}/\mu \text{m}$ (per width of channel footprint) were achieved, respectively.

Recent monolithic 3-D integrated-circuit (3D-IC) technology tends to induce stronger driving capability in pMOS transistors, compared to that obtained using existing processes. Thus, conventional 6T SRAMs suffer degradation in access speed and write margin when used in monolithic 3D-ICs. This letter proposes a dual-split-controlled 4P2N (DSC-4P2N) SRAM with corresponding read and write assist schemes capable of providing a larger cell read current and higher write margins compared to 4N2P SRAMs implemented in monolithic 3D-ICs. The proposed DSC scheme improves $4.8\times $ in read stability compared to 4P2N SRAM without DSC. A fabricated DSC-4P2N SRAM in monolithic 3D-IC was shown to outperform the previous 6T SRAMs.

We demonstrate a multi-threshold threshold gate (MTTG) based on a series and parallel connection of several MOS-NDR circuits. A MOS-NDR circuit is made of five standard Si-based metal–oxide–semiconductor field-effect-transistor (MOS) devices. It can show the negative-differential-resistance (NDR) characteristic in its current–voltage (I–V) curve by adjusting suitable parameters for the MOS transistors. The operation principle of this MTTG is based on the monostable-bistable transition logic element (MOBILE), which the output voltage goes to the low or high state depending on the relative current-peak conditions of the series-connected NDR circuits by supplying a clocked voltage. The weight of this MTTG is defined by the gate width of the MOS device in the MOS-NDR circuit. It is different from the design using the area of the resonant tunneling diode as the weight in the other NDR-based MTTG circuit. A great advantage of this MOS-NDR-based MTTG is that we can design the application using the standard CMOS technology without the need of compound semiconductor.