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Optical constant spectra for silicon and thermally grown silicon dioxide have been simultaneously determined using variable angle of incidence spectroscopic ellipsometry from 0.75 to 6.5 eV. Spectroscopic ellipsometric data sets acquired at multiple angles of incidence from seven samples with oxide thicknesses from 2 to 350 nm were analyzed using a self-contained multi-sample technique to obtain Kramers–Kronig consistent optical constant spectra. The investigation used a systematic approach utilizing optical models of increasing complexity in order to investigate the need for fitting the thermal SiO2 optical constants and including an interface layer between the silicon and SiO2 in modeling the data. A detailed study was made of parameter correlation effects involving the optical constants used for the interface layer. The resulting thermal silicon dioxide optical constants were shown to be independent of the precise substrate model used, and were found to be approximately 0.4% higher in index than publis...

Free carrier concentration profiles were determined by Fourier Transform Infrared (FTIR) variable angle spectroscopic ellipsometry. The technique exploits carrier absorption in the mid-infrared spectral range and combines the sensitivity of ellipsometry with a simple Drude free carrier absorption model to determine the carrier profile. In this study, the carrier profiles were modeled as graded multilayers that were constrained to a specific functional form (e.g. Gaussian, complementary error function) when appropriate. Carrier profiles from boron and arsenic ion-implanted that had been subjected to furnace or Rapid Thermal Annealing (RTA) annealed silicon wafers were compared to Spreading Resistance Probe and Secondary Ion Mass Spectrometry profiles. p−p+doped epitaxial silicon samples (before and after annealing) were also measured and the results were compared to theory.

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process. >

An advanced, high-performance, half-micrometer generation technology has been developed for fast CMOS SRAM circuits. This process features an aggressive interwell isolation module which allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m and an advanced framed-mask poly-buffered LOCOS isolation (FMPBL) which reduces field oxide encroachment and the transistor narrow-width effect and provides a 1.2- mu m active pitch. Transistors are fabricated with a 125-A gate oxide and a dual n/sup +//p/sup +/ source/drain implanted polysilicon gates to provide excellent short-channel behavior down to 0.3- mu m effective channel length. Transistor design is optimized to reduce the polysilicon gate bird's beak and lightly doped drain (LDD) underdiffusion. For PMOS transistors, boron diffusion through the gate oxide is minimized by replacing BF/sub 2/ with B/sup 11/ for the p/sup +/ S/D implant. A titanium salicide process provides strapping between n/sup +//p/sup +/ polysilicon gates and lower sheet and contact resistances. The back-end features three levels of metallization and polysilicon contact plugs. Discrete transistor lifetimes for DC hot-carrier degradation are in excess of 10 years at 3.3-V operation. A 16 K* 4 SRAM displayed no parametric shifts after hot-carrier stressing for 1000 h at 7-V and 0 degrees C. This is consistent with a lifetime of greater than 10 years at 3.3-V operation. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are achieved. >

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications.

The first functional 6 V, 4 Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90 nm and 0.25 /spl mu/m process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded flash at the 90 nm node and beyond.

This paper describes techniques to prepare integrated circuit (IC) samples, containing a Thick Organic Dielectric (TOD) over Cu inductors, for Scanning Electron Microscopy (SEM) or Focused Ion Beam (FIB) editing. Our technique utilizes mechanical polishing and UV laser ablation in lieu of chemical decapsulation and deprocessing.

Advanced RF IC’s incorporate numerous components along with the CMOS circuitry. One component is a metal-insulator-metal (MIM) capacitor. Test capacitors have been stressed using accelerated voltage and temperature conditions to assess the long-term reliability. This paper describes a methodology for evaluating the MIM capacitors that have failed during reliability testing. IR microthermography was developed to detect leakage locations in areas that are not visible to optical inspection or standard emission microscopes. These areas were deprocessed to correlate the IR emission and physical defect locations. This information is utilized to understand the failures and improve the reliability.

An advanced high-performance sub-half-micron technology for fast CMOS SRAMs (static RAMs) has been developed. Features of this thin-well process include: an aggressive interwell isolation module, framed-mask poly-buffered LOCOS isolation (FMPBL), a 125-AA gate oxide, dual n/sup +//p/sup +/ implanted polysilicon gates, titanium salicide, two levels of polysilicon, TiN metallization barriers, a poly plug option, and up to three layers of metallization. An interwell isolation process allows scaling of the n/sup +/ to p/sup +/ space to less than 2 mu m. Active transistor design is optimized to reduce the polysilicon gate bird's beak and LDD (lightly doped drain) underdiffusion. Discrete transistor lifetimes for hot carrier degradation are in excess of 10 years of 3.3-V operation. A 16 K*4 SRAM displays no parametric shifts after HCl stressing for 1000 h at 7 V and 0 degrees C. Ring oscillator delay times of 85 ps at 3.3-V and 65 ps at 5-V supply are obtained. >

A scalable submicron contact technology has been developed using a fully conformal LPCVD (low-pressure chemical vapor deposition) titanium nitride barrier metal that provides low contact resistance to salicide, low leakage, excellent adhesion, and high thermal stability. Owing to the uniform step coverage, especially in deep, straight wall contacts, the CVD TiN overcomes the metal reliability and junction leakage issues associated with the physical sputtering of metals in high-aspect-ratio, submicron contacts. LPCVD TiN withstands 550 degrees C thermal stress, maintaining low contact resistance and leakage, while physically deposited TiN fails at 500 degrees C. The applicability of CVD TiN barrier technology to VLSI devices has been successfully demonstrated on production circuits. >

The triple-level-metal (TLM) module of a submicron CMOS technology with (titanium) salicided devices is discussed. The key technology features of the module include the use of conformal BPSG for enhanced planarization, a TiN barrier layer under M1, plasma-dry-tapered contacts and vias, and TiN antireflection coatings for metal patterning. Large-area test structures for each TLM component were used to develop and evaluate the processes. Electrical measurements and physical analysis are presented for these components. >

This paper reports the investigation of low pressure chemical vapor deposition of SiN/sub X/ film for bottom antireflective coating (BARC) application in 0.35 /spl mu/m lithography and below. The SiN/sub X/ material was successfully designed to provide excellent anti-reflective layer which meets various advanced device integration requirements. This BARC process has been found to be manufacturable for deep-UV and I-line lithography.

High quality interpoly dielectrics are required for non-volatile memories (NVM) in order to achieve long term data retention and endurance over many program/erase cycles. LPCVD high temperature oxide (HTO) deposited at 800°C-900°C is investigated for use in oxide-nitride-oxide (ONO) interpoly dielectric stacks. HTO allows for reduced thermal budgets, improved conformal coverage at edge features and more flexibility in scaling the ONO stack compared to thermal oxide layers. SIMS and atomic force microscopy results indicate that smooth, high quality films are deposited with a rms roughness of 0.12nm. Etch rates of as-deposited films are lowered 35% following several densification anneals. Field strengths (at 1μA) of 7-8MV/cm and leakage currents in the pA range are measured. Centroid measurements on sressed oxides show traps to be located at the HTO/polysilicon interfaces. Finally, double poly flash memory cells fabricated with ONO stacks containing HTO top oxide show improved field strength and data retention.

We have performed a detailed optical study of phosphorus-doped polycrystalline silicon films (prepared by amorphous deposition with in situ doping and annealing by thermal oxidation up to 1000 °C) using Raman spectroscopy and variable-angle spectroscopic ellipsometry from 0.7 to 5 eV. We focus on the determination of strain and grain size using optical techniques and compare with results of a structural analysis using plan-view transmission electron microscopy and atomic force microscopy. We analyze the derivatives of our ellipsometry data (peak shifts and broadenings) using analytical lineshapes, which are affected by grain size, film thickness, doping, and inhomogeneity, but only minimally by macroscopic biaxial strain.

Gate dielectrics for advanced ULSI circuits are rapidly scaling below 10 nm. Thinner dielectrics and smaller lateral dimensions are essential to produce high performance transistors for memories, microprocessors and microcontrollers. In this overview we will discuss the factors that affect the performance and reliability of scaled gate dielectrics. Process parameters that affect oxide and oxynitride dielectrics include substrates, pre-gate cleaning, growth parameters and growth techniques as well as oxide and oxynitride dielectric materials. Thin dielectrics require new or modified measurement methods and extensive use of physical analysis techniques such as SIMS, XPS, AFM and TEM to characterize these materials. Boron diffusion through thin gate oxides, HCI stress, and process induced damage can degrade dielectric quality and affect long term reliability. These factors will affect the performance and reliability of circuits with scaled gate dielectrics.

The nucleation and growth of in situ doped, LPCVD silicon films was analyzed using atomic force microscopy, variable-angle spectroscopie ellipsometry, and transmission electron microscopy. The RMS surface roughness initially increases from 0.5 to 5.7 nm with increasing deposition times and then rapidly decreases to 0.5 nm for longer times. Ellipsometry data was modeled using two layers where the top layer consists of a mixture of amorphous Si plus voids and the bottom layer is a continuous amorphous Si layer. Cross-section TEM reveals the nuclei size and structure for these silicon films and confirms the results of the other techniques.

We have characterized the surface topography of silicon films from different deposition and doping process sequences using AFM and optical reflectivity. The resulting surface structures after deposition, doping, oxide growth, and oxide removal correlate with the electrical leakage currents and breakdown voltages of double polysilicon capacitors. As-deposited amorphous films had smoother surfaces than those deposited in the crystalline state. Gas-phase diffusion doping increases the surface roughness. Only the amorphous in situ doped films retained a smooth surface following oxidation, yielding low leakage capacitors with breakdown fields above 8 MV/cm. Surprisingly, implanted amorphous films exhibited the roughest interfaces, resulting in lower breakdown fields. This study has shown that AFM provides an effective, quick, non-destructive diagnostic technique for semiconductor processing.

We have developed a process sequence for a flash EEPROM memory embedded in an advanced microcontroller circuit. This process simultaneously forms a thick top oxide on the interpoly ONO dielectric in the memory array and a stacked gate-oxide for the logic transistors. We have fabricated one-transistor, flash bit-cells with good data retention characteristics that incorporate a 17 nm ONO film along with high-quality stacked gate oxides. >

An ellipsometric method is demonstrated for the assessment of the amount of N in nitrided silicon oxides. The method utilizes the immersion of the film covered sample in a liquid that refractive index matches to the bulk film index. Thus, the overlayer is optically removed yielding greater measurement sensitivity to the interface region where the N is concentrated and is therefore optically distinct. A simple optical model is used and the ellipsometric results are compared with and found in concordance with secondary ion mass spectroscopy N profile measurements made on nitrided oxides that were prepared using N2O and NO. In addition, the interfacial roughness has been found to decrease with increasing N content also in agreement with a literature report. The new method called ‘‘spectroscopic immersion ellipsometry’’ is compared with conventional spectroscopic ellipsometry for the same samples and found to be superior.

The surface topography of doped polysilicon films was investigated by atomic force microscopy for a wide range of doping and process conditions. These low‐pressure chemical vapor deposition silicon films were approximately 350 nm thick. The amorphous films were in situ phosphorus doped during deposition at 550 °C, while the crystalline films were deposited at 625 °C and subsequently diffusion doped using either PH3 or POCl3 gases. Measured resistivities ranged from 700 to 10 000 μΩ cm corresponding to secondary ion mass spectrometry phosphorus concentrations that ranged from 8.45 to 0.95×1020 cm−3. In situ doped films exhibited the smoothest surface topography with a peak‐to‐valley surface roughness of 11 nm. The surface roughness values were 50 nm for PH3 doped poly films, and as high as 135 nm for the POCl3 doped films. Atomic force microscopy grain size analysis showed uniform distributions for the in situ and PH3 doped films with grain sizes of 130 and 200 nm, respectively. POCl3 doped poly‐Si showed ...

Rapid thermal annealing (RTA) technology offers potential advantages for GaAs MESFET device technology such as reducing dopant diffusion and minimizing the redistribution of background impurities. LEC semi-insulating GaAs substrates were implanted with Si at energies from 100 to 400 keV to doses from 1 × 1012 to 1 × 1014/cm2. The wafers were encapsulated with Si3N4 and then annealed at temperatures from 850-1000° C in a commercial RTA system. Wafers were also annealed using a conventional furnace cycle at 850° C to provide a comparison with the RTA wafers. These implanted layers were evaluated using capacitance-voltage and Hall effect measurements. In addition, FET’s were fabricated using selective implants that were annealed with either RTA or furnace cycles. The effects of anneal temperature and anneal time were determined. For a dose of 4 × 1012/cm2 at 150 keV with anneal times of 5 seconds at 850, 900, 950 and 1000° C the activation steadily increased in the peak of the implant with overlapping profiles in the tail of the profiles, showing that no significant diffusion occurs. In addition, the same activation could be obtained by adjusting the anneal times. A plot of the equivalent anneal times versus 1/T gives an activation energy of 2.3 eV. At a higher dose of 3 × 1013 an activation energy of 1.7 eV was obtained. For a dose of 4 × 1012 at 150 keV both the RTA and furnace annealing give similar activations with mobilities between 4700 and 5000 cm2/V-s. Mobilities decrease to 4000 at a dose of 1 × 1013 and to 2500 cm2/V-s at 1 × 1014/cm2. At doses above 1 × 1013 the RTA cycles gave better activation than furnace annealed wafers. The MESFET parameters for both RTA and furnace annealed wafers were nearly identical. The average gain and noise figure at 8 GHz were 7.5 and 2.0, respectively, for packaged die from either RTA or furnace annealed materials.

Single‐crystal silicon wafers have been implanted with As, P, and B to doses of 1×1013–1×1016/cm2 and given a transient anneal using a Varian IA‐200 Rapid Isothermal Annealer. The system uses infrared radiation to heat the wafers to temperatures in excess of 1000 °C for times on the order of 10 sec. Sheet resistance and Hall measurements have been used to determine the effect of the anneal on the electrical properties of the wafers. Rutherford backscattering and secondary ion mass spectroscopy have been used to measure lattice damage and dopant profiles before and after annealing. As and P are lost during the anneal unless the wafer is capped. Complete activation can be achieved with very little dopant diffusion. Residual damage is minimal in (100) oriented wafers that had been implanted with As. However, for (111) wafers damage is less in (111) wafers implanted to doses ≥5.0×1015/cm2, than in (111) wafers implanted to doses ≤5.0×1015/cm2. The diffusion of As during this transient anneal has been modeled ...

The effects on Si wafers of (1) Ge or Si amorphization implants, (2) B or BF2 dopant implants at low energies (15 keV through 16 nm of screen oxide) and (3) rapid thermal processing (RTP) at 800–1050° have been systematically studied. Sheet resistance (Rs), spreading resistance probe (SRP), Rutherford backscattering (RBS) and ultrahigh vacuum secondary ion mass spectrometry (SIMS) have been used to study the resulting electrical and materials properties of these wafers. Values for Rs versus junction depth are below any results reported in the literature. The Rs maps show lower Rs and better uniformity in the wafers that were amorphized with Ge or Si and received a B rather than a BF2 implant. The effects of channeling, molecular breakup of BF2, B solid solubility, and annealer uniformity are discussed.

Both pulsed and CW lasers have been used to anneal ion implanted single crystal silicon, polysilicon and ion implanted devices. The advantages and limitations of each type of laser and laser processing in general is discussed. Our results and those in the literature are compared to conventional thermal anneals. The thermal stability of ion-implanted, laser-annealed, single crystal silicon and polysilicon is reported.

Vapor‐deposited Cu‐Au thin films were produced containing composition modulations with wavelengths between 8 and 26 A. The modulations produced satellite peaks in the x‐ray diffraction patterns. Amplification factors and the corresponding diffusion coefficients were obtained by measuring the decay rate of the satellite intensities. The amplification factor reached a maximum at 17 A and decreased at both shorter and longer wavelengths. Interdiffusion coefficients between 10−21 and 10−19 cm2/sec were measured over the temperature range 200–260 °C. The effective diffusion coefficient is linearly dependent on the function B2(λ) for λ≳10 A. From the wavelength dependence of the measured diffusivities, a gradient‐energy coefficient of −4.7×10−6 erg/cm was obtained and is in good agreement with theoretical estimates. These experimental results were compared with the predictions from a proposed model for diffusion on cubic lattices.

Polysilicon films were deposited on the following four dielectric layers: 0.10 μm Si02, 0.10 μm Si3N4, 1.0 μm Si02 and a dual layer of 0.10 μm Si3N4 over 1.0 μm Si02. The films were doped with As or P and then annealed with a scanning CW-argon laser. The resulting sheet resistance at a given laser power depends upon both the dielectric material and its thickness. The threshold power, that causes complete melting of the polysilicon, is inversely proportional to the thermal resistance of the underlying dielectric layers. With certain laser parameters and substrate film combinations, excessive thermal stresses cause cracking of the polysilicon films. The laser annealing process is also influenced by the net optical reflectance of the polysilicon/ dielectric multilayer films.

A Varian IA-200 isothermal annealer has been used to anneal ion implantation damage and electrically activate dopants in As and B implanted silicon with minimal redistribution of the impurity. The anneal occurs in vacuum using infrared radiation from a resistively heated sheet of graphite. Good quality anneals of /sup 11/B implanted samples have been obtained with minimal boron diffusion. Arsenic implanted wafers have also be annealed with excellent results except for a substantial loss of As which occurs unless the wafer has an SiO/sub 2/ cap. The anneal quality of (100) wafers was independent of dose, however, the anneal quality of the (111) wafers improved with increasing As dose.

Presentation des variations des proprietes electriques en fonction du temps d'exposition, de la temperature de chauffe et de l'espece dopant. Correlation de ces effets a la croissance de grain et a la diffusion du dopant

The corrosion performance of both unencapsulated and plastic encapsulated parts has been studied under temperature-humidity-bias (THB) stresses using a patterned test chip with aluminum metallization. The effect of encapsulation materials and ionic contaminants purposely introduced on the chip surface has been determined for both accelerated THB and severe, real life conditions. Unencapsulated test chips exhibited very different THB performance characteristics from encapsulated parts including a near-zero induction time and a shallow post-induction slope on the % failures vs time curve. The induction time and mean-time-to-failure (MTF) for encapsulated devices were strong functions of both the polymeric class of encapsulant and the particular compound employed. At least part of the difference in performance between molding compounds has been attributed to impurities inherent in the compounds. Impurities contributed from conductive epoxies used for die attach also adversely affect the device's MTF, as do normal contaminants present on as-plated leadframes. The environmental factors of temperature, relative humidity and bias greatly affect the performance of encapsulated devices. In this study, the MTF decreased dramatically with bias between 5 and 30 volts, the range over which most devices operate. The acceleration factors relating device performance in an 85°C/85%RH environment to severe, real life conditions were surprisingly small and somewhat dependent on the encapsulant.

The diffusion of As in polycrystalline silicon films subjected to rapid thermal annealing has been studied using sheet resistance and Rutherford backscattering. The polycrystalline Si films were deposited on oxidized silicon wafers, implanted with As, and annealed with a Varian IA‐200 isothermal annealer. Infrared radiation from a resistively heated sheet of graphite heats the wafer, in a vacuum, to temperatures >1000 °C for times on the order of a few seconds. The rate of diffusion and rate of loss of As from the polycrystalline Si is much faster than the diffusion rate and loss rate in single crystal Si annealed with identical conditions. Diffusion prior to grain growth agrees with previously reported results for As in polycrystalline Si. However, grain growth appears to enhance As diffusion.

Polycrystalline Si films on oxidized Si wafers have been subjected to a rapid thermal processing anneal prior to As ion implantation. After ion implantation the films are given another rapid thermal processing anneal to activate the As. The preimplant anneal causes the as‐deposited grain size to increase by ∼ a factor of 10. These films have a 20–30% lower sheet resistance than films that were post‐implant annealed only. The increase in grain size by the preimplant anneal reduces the grain boundary area and therefore, minimizes the amount of dopant in the grain boundary relative to the grain.

Polycrystalline silicon films deposited on oxidized wafer surfaces were implanted with As and annealed on a Varian IA‐200 rapid thermal annealer. The effects of annealing conditions on resultant grain size of original as‐deposited columnar grains are presented with a modified model for interfacially driven grain growth. During an initial temperature rise to 910 °C the original grain size (39 nm) and dopant profile are not significantly altered. At 1145 °C the grains have grown to 90 nm and the As is uniformly distributed throughout the film. Additional annealing to 1300 °C in 20 s causes grains to grow to 260 nm. Further grain growth is retarded due to the 300‐nm film thickness. During annealing of unencapsulated films a substantial loss of As results in a lower rate of grain growth. When grain size increases, Hall mobility increases and resistivity decreases.

Silicon wafers implanted with 75As have been annealed with a Varian IA‐200 isothermal annealer. The anneal occurs in vacuum using radiation from a resistively heated sheet of graphite. The anneal quality depends on the graphite heater temperature and exposure time. If the anneal time is too short implantation damage remains and if the time is too long measurable losses of As occur causing the sheet resistance to increase. The loss of As can be prevented by depositing 0.05 μm of SiO2 on the wafer before annealing.

The purpose of this study is to analyze ion implant damage profile using RBS and ellipsometry. Silicon wafers were implanted with 75As at 100, 200 or 300 keV; doses were chosen to generate constant peak impurity concentrations at each energy. The samples were then analyzed using RBS to obtain damage- depth profiles and ellipsometry to obtain Δ,ψ parameters. At light doses decreasingΔ values correspond to increased scattering yield; at higher doses ψ increases rapidly as the scattering yield approaches the random value. The higher energy implants shift the Δ-ψ curves to larger ψ values. Multilayer structures, that include lightly damaged silicon on either side of the project range as well as more damaged near the projected range, are required to model the ellipsometer parameters.

Five different RTP units have been examined. These are the Varian RTP-800, the Eaton ROA-400, the A.G. Associates 2101/2106, the Tamarack 180A-C and the Varian IA-200. Each system is a cassette-to-cassette serial processor designed for use in a high volume semiconductor fabrication line. These units will heat a wafer from room temperature to 400–1400C in times on the order of a few seconds. Each unit uses radiation to heat and cool the wafer. The different radiation sources, wafer handling systems, temperature measurements and control computers are discussed. The control of slip and nonuniform temperatures is presented as well as information regarding the types of ambients that can be used in each system.

Electrical measurements and Rutherford backscattering have been used to evaluate the thermal stability of single crystal and polycrystalline Si films that were ion implanted and laser annealed. The films were implanted with 75As or 31p and annealed with either a pulsed ruby, a pulsed Nd:YAG or a CW­Ar+ laser. The samples were then thermally annealed at temperatures between 450 and 900°C. The single crystal samples implanted with arsenic below 1 × 10-15 cm−2 were thermally stable. For higher doses the electrical concentration reaches a minimum at 800°C. The same trends are observed in the polysilicon films for sufficiently high doping levels. RBS shows that As is precipitating at 700°C in single crystal material and has begun to go back into solution at 900°C for concentrations of ∼7 × 1020 cm−3. Similar trends are observed for 31P implanted samples.

Polycrystalline silicon films on oxidized silicon wafers have been subjected to rapid thermal processing before arsenic or boron ion implantation (pre-implant anneal). The films have then been ion implanted and given another rapid thermal process step to activate the dopant and repair the implant damage. The pre-implant anneal has caused the as-deposited grain size to increase by approximately a factor of ten. After the activation anneal these films have shown a 10 to 100% lower sheet resistance than films which did not receive a pre-implant anneal. The increase in grain size by the pre-implant anneal reduced the grain boundary area and as a result reduced the amount of dopant trapped in the grain boundaries relative to that which was actually inside the grains.

Polycrystalline silicon films of 300 nm thickness were deposited on oxidized wafer surfaces, implanted with As, and annealed on a Varian IA 200 rapid thermal annealer. Transmission electron microscopy was used to study through-thickness and cross sectional views of grain size and morphology of as-deposited and of transient annealed films. A bimoda] distribution of grain sizes was present in as-deposited polycrystalline silicon films. The first population was due to columnar growth of some grains to a final average diameter of 20 rm. The second population of small equiaxed grains of 5 nm average diameter were formed early in the deposition process. During transient annealing grains in the first population grew rapidly up to 280-nm equiaxed grains. After this the growth rate decreased due to the grain size reaching the thickness of the film. Grains in the second population grew rapidly up to a size of 150 nm, after which the growth rate was lowered due to grains impinging upon one another. The grain growth processes for both populations have been described with a modified model for interfacially driven grain growth. This model accounts for diffusion and grain growth which occur with rapidly rising and falling temperatures during short annealing times characteristic of transient annealing processes.

Ohmic contacts to GaAs have been studied using a high resolution TEM, an SEM and a STEM with an energy dispersive x-ray attachment. Two different deposition sequences of the constituent Au-Ge-Ni metals yielded specific contact resistivities that varied by one order of magnitude. Crosssection images of the interface between the GaAs and the metal Au-Ge-Ni layers following alloying showed protrusions at the interface. Contacts with low specific resistivities showed deeper protrusion and also significantly more Ge and Ni in the GaAs.

Rapid thermal annealing (RTA) technology offers potential advantages for the processing of ion implanted GaAs. High energy implants of 300 keV or above are used for power MESFETs as well as in the ohmic contacts for low noise devices. The purpose of this paper is to investigate and characterize the RTA of Si implants into LEC GaAs using implant energies of 300keV and above, and a range of doses from 2.3 ×1012 to 3×1014 /cm2. The wafers were analyzed using capacitance-voltage and Hall measurements. Factors which cause variability in pinchoff voltage are identified and an RTA process comparable to conventional furnace annealing is presented for low dose implants. Superior implant activation is observed for higher dose implants through the use of higher annealing temperature.

Polycrystalline silicon films were transient preannealed, As implanted, and transient post-annealed at peak temperatures up to 1250°C for times up to 17.5 seconds. Structural changes occurring during post-annealing were examined by transmission electron microscopy. These results were correlated to Rutherford Backscattering and sheet resistance results. The grain size, which increased from 5–20 to 150–300 nm during preannealing, did not increase during post-annealing. During early stages of post-annealing, As diffused along grain boundaries and generated dislocation sources at grain boundary surfaces. Subsequently, as annealing progressed, a fine, As-rich cellular network structure propagated into the grains until the structure of an entire grain was transformed into a fine cellular network at the longest annealing times. Residual stresses in the film were relieved during formation of the network structure. The sheet resistance of preannealed samples, in comparison with non-preannealed samples with similar implantation and final transient anneals, was lower at shorter annealing times due to the larger grain size, which increased mobility, and the reduced grain boundary area, which trapped less As. It was also lower at longer annealing times due to the formation of the cellular network structure. In subsequent furnace stability tests for 30 minutes at 700–900°C, the sheet resistance increased less for preannealed than for non-preannealed samples.

The reliability of thin-film Ni-Cr resistors was studied with respect to the effects of corrosion, oxidation and interdiffusion. Water on unpassivated films resulted in anodic dissolution at potentials above 2.5 volts. Oxidation increased the resistivity and lowered the T.C.R. to 20 ppm/°C. Aluminum diffused into the NiCr with an activation energy of 96 kcal/mole.

Phosphorus-doped poly-Si films were studied with Raman spectroscopy and spectroscopic ellipsometry. We determine strain and grain size and compare with a structural analysis using plan-view transmission electron microscopy and atomic force microscopy. We analyze the derivatives of our ellipsometry data (peak shifts and broadenings) using analytical lineshapes, which are affected by grain size, film thickness, doping, and inhomogeneity, but only minimally by macroscopic biaxial strain.