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This paper presents the design exploration and applications of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. Furthermore, this paper proposes an original glitch-diminishing technique to filter out useless switching power by asserting the data signals after the data transient period. This paper adopts two multimedia/DSP design examples, i.e., a multitransform design for H.264 and a versatile multimedia functional unit (VMFU), to evaluate the proposed SPST. These two design examples have quite different hardware configurations, thus, the realization issues of the SPST on every design also remarkably differ from each other. The multitransform design can compute three transforms which are required in H.264 encoding while the VMFU possesses six commonly used multimedia/DSP functions, namely, addition, subtraction, multiplication, MAC, interpolation, and sum-of-absolute-difference. After optimizing the design elaborately, we find that the proposed SPST can, respectively, save 27% and 24% power dissipation on average of the H.264 multitransform design and the VMFU at the expense of less than 20% area augmentation. Index Terms--Digital-signal processing chips, image coding, low-power design, video coding.

Wide-angle cameras are widely used in surveillance and medical imaging applications nowadays. Images captured by wide-angle lens suffer from barrel distortion which means that the outer regions of the image are compressed more than the inner one. A low-cost high-speed VLSI implementation for barrel distortion correction is presented in this brief. In our simulation, the proposed circuit can achieve 200 MHz with 45 K gate counts by using TSMC 0.18 [micro]m technology. Compared with the previous distortion correction design, our circuit requires less hardware cost and achieves faster working speed. Index Terms--Barrel distortion correction, VLSI architecture, wide-angle.

This paper presents a new efficient architecture for the design of fast low-cost single-clock-cycle binary comparators. The proposed 64-bit circuit requires only 1051 transistors and, when implemented by using the ST 90-nm 1-V CMOS technology, it exhibits a running frequency higher than 4 GHz with an average power dissipation of only ~4 mW. Comparison with the fastest comparator known in the literature demonstrates that, at a parity of technology used, the novel architecture is ~12% faster and requires ~69% less transistors. Index Terms--CMOS dynamic circuits, comparator, digital arithmetic, VLSI circuits.

In this paper, a low latency angle recoding method for the higher bit-width parallel coordinate rotation digital computer (CORDIC) rotator implementations is proposed. In previous studies, parallel CORDIC (para-CORDIC) rotators have been used to reduce the computational bottleneck by precomputing the required rotation directions. However, the number of required microrotations increases with the bit-width of the input angle, leading to extra stages compared to the conventional CORDIC. To overcome this, our proposed method can obtain a reduced number of microrotations for larger bit-width implementations by recoding two bits of the input angle in the first few area-consuming stages concurrently. This leads to above 21% area/delay reduction compared to previously reported 64-bit para-CORDIC methods. We have implemented our proposed 64-bit para-CORDIC rotator implementations using 0.13-[micro]m CMOS technology, and the operating speed can achieve 250 MHz. Index Terms--Coordinate rotation digital computer (CORDIC), signal processing, very large-scale integration (VLSI) design.

This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this data-path relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13-[micro]m CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation. Index Terms--Convolutional codes, flexibility, quantization, subset decoding, Trellis-coded modulation (TCM), Viterbi decoding, VLSI, wireless personal area network (WPAN).

In deep-submicrometer technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis of the entire die. This work proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study delay and contention time in the presence of process variability. The methodology is employed for yield analysis of two typical wide-NOR circuits: one with a static keeper and another without the keeper. Since we use a general numerical approach for the calculation of derivatives and error propagation, the proposed yield analysis methodology may be applied to a wide range of dynamic gates (for instance pre-charge dynamic gates using dynamic keeper). The proposed methodology results in errors less than 2% when compared to Monte Carlo simulation, while increasing computational efficiency up to 100 x. Index Terms--Design for yield, Monte Carlo methods, probabilistic analysis, process variability, VLSI, yield estimation.

This brief proposes a multiplierless VLSI architecture for the famous 9/7 wavelet filters. The novelty of this architecture is the possibility to compute the 5/3 wavelet results into the 9/7 data path with a reduced number of adders compared to other solutions. The multiplierless architecture has been characterized in terms of performance through simulations into a JPEG2000 environment and compared to other solutions. Implementation on a 0.13-[micro]m standard cell technology shows that the proposed architecture compared to other multiplierless architectures requires a reduced amount of logic with excellent performance. Index Terms--Filter bank (FB), JPEG2000, muitiplierless implementation, VLSI, wavelet.

We present the architecture and VLSI circuit implementation of a BiCMOS potentiostat bank for monitoring neurotransmitter concentration on a screen-printed carbon electrode array. The potentiostat performs simultaneous acquisition of bidirectional reduction-oxidation currents proportional to neurotransmitter concentration on 16 independent channels at controlled redox potentials. Programmable current gain control yields over 100-dB cross-scale dynamic range with 46-pA input-referred rms noise over 12-kHz bandwidth. The cutoff frequency of a second-order log-domain anti-aliasing filter ranges from 50 Hz to 400 kHz. Track-and-hold current integration is triggered at the sampling rate between dc and 200 kHz. A 2.25-mm x 2.25-mm prototype was fabricated in a 1.2-[micro]m VLSI technology and dissipates 12.5 mW. Chronoamperometry dopamine concentration measurements results are given. Other types of neurotransmitters can be selected by adjusting the redox potential on the electrodes and the surface properties of the sensor coating. Index Terms--Analog VLSI, biomedical instrumentation, current-mode circuits, dopamine sensor arrays, log-domain signal processing, neurotransmitters, potentiostat.

We present a novel analog VLSI implementation of visual motion computation based on the lateral inhibition and positive feedback mechanisms that are inherent in the hysteretic winner-take-all circuit. By use of an input-dependent bias current and threshold mechanism, the circuit resets itself to prepare for another motion computation. This implementation was inspired by the Barlow-Levick model of direction selectivity in the rabbit retina. Each pixel uses 33 transistors and two small capacitors to detect the direction of motion and can be altered with the addition of six more transistors to measure the interpixel transit time. Simulation results and measurements from fabricated VLSI designs are presented to show the operation of the circuits. Index Terms--Analog VLSI, motion, pixel parallel, vision chips, VLSI design.

In this paper, we present a design framework for scalable memory-based implementation of the discrete Hartley transform (DHT) using simple and efficient systolic and systolic-like structures for short and prime transform lengths, as well as, for lengths 4 and 8. We have used the proposed short-length structures to construct highly modular architectures for higher transform lengths by a new prime-factor implementation approach. The structures proposed for the prime-factor DHT, interestingly, do not involve any transposition hardware/time. Besides, it is shown here that an N-point DHT can be computed efficiently from two (N/2)-point DHTs of its even- and odd-indexed input subsequences in a recursive manner using a ROM-based multiplication stage. Apart from flexibility of implementation, the proposed structures offer significantly lower area-time complexity compared with the existing structures. The proposed schemes of computation of the DHT can conveniently be scaled not only for higher transform lengths but also according to the hardware constraint or the throughput requirement of the application. Index Terms--Dicrete Fourier transform (DFT), discrete Hartley transform (DHT), distributed arithmetic, ROM-based architecture, systolic arrays, VLSI.

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory. Index Terms--Block matching, H.264/AVC, motion estimation (ME), variable block size, very large scale integration (VLSI) architecture.

The parameters that are required to specify logic gates that are technology and fabrication process independent are investigated. Ways of automating the optimization of the logic gates for implementation in new technologies, and automating the layout of logic cells for new design rules or new fabrication processes are described.

Abstract: Design complexity has been increasing exponentially this last decade. In order to cope with such an increase and to keep up designers' productivity, higher level specifications were required. Moreover [...]

Visual motion information provides a variety of clues that enable biological organisms from insects to primates to efficiently navigate in unstructured environments. We present modular mixed-signal very large-scale integration (VLSI) implementations of the three most prominent biological models of visual motion detection. A novel feature of these designs is the use of spike integration circuitry to implement the necessary temporal filtering. We show how such modular VLSI building blocks make it possible to build highly powerful and flexible vision systems. These three biomimetic motion algorithms are fully characterized and compared in performance. The visual motion detection models are each implemented on separate VLSI chips, but utilize a common silicon retina chip to transmit changes in contrast, and thus four separate mixed-signal VLSI designs are described. Characterization results of these sensors show that each has a saturating response to contrast to moving stimuli, and that the direction of motion of a sinusoidal grating can be detected down to less than 5 % contrast, and over more than an order of magnitude in velocity, while retaining modest power consumption. Index Terms--Address-Event Representation (AER), analog very large-scale integration (VLSI), biomimetic, modular, neuromorphic, visual motion.

Hardware designers need effective techniques for early evaluation of the hardening mechanisms adopted in safety-critical VLSI circuits. We propose field-programmable gate-array based circuit emulation for performing fault-injection campaigns. Experimental results show that the new technique is about four orders of magnitude faster than simulation-based fault injection. Index Terms--Fault-injection, FPGA, safety-critical applications, single-event upset (SEU).

A VLSI architecture is proposed for the realization of real-time two-dimensional (2-D) image filtering in an address-event-representation (AER) vision system. The architecture is capable of implementing any convolutional kernel F(x, y) as long as it is decomposable into x-axis and y-axis components, i.e., F(x, y) = H(x) V(y), for some rotated coordinate system {x, y} and if this product can be approximated safely by a signed minimum operation. The proposed architecture is intended to be used in a complete vision system, known as the boundary contour system and feature contour system (BCS-FCS) vision model, proposed by Grossberg and collaborators. The present paper proposes the architecture, provides a circuit implementation using MOS transistors operated in weak inversion, and shows behavioral simulation results at the system level operation and some electrical simulations. Index Terms - Analog integrated circuits, communication systems, convolution circuits, Gabor filters, image analysis, image segmentation, neural networks, nonlinear circuits, subthreshold circuits.

In this paper, parallel recombinative simulated annealing (PRSA), a hybrid method with features of simulated annealing and genetic algorithms, is examined. PRSA inherits the global convergence property from simulated annealing and the parallelism property from genetic algorithms. PRSA was implemented on a monoprocessor system as well as on a transputer. The algorithm, its parallel implementation, and its application to an NP-hard problem, namely standard cell placement in very large scale integration (VLSI) chip design, are described. PRSA was run for a large range of test cases. Since its performance depends on many parameters, the effects of parameter variations are studied in detail. Some important parameters are migration of individuals to other transputer nodes and selection strategies for constructing new populations. In comparison with simulated annealing and genetic algorithms, PRSA was found to produce better solutions.

We present an area-efficient parallel architecture that implements the constant-geometry, in-place Fast Fourier Transform. It consists of a specific-purpose processor array interconnected by means of a perfect unshuffle network. For a radix r transform of N = [r.sup.N] data of size D and a column of P = [r.sup.P] processors, each processor has only one local memory of N/rP words of size rD, with only one read port and one write port that, nevertheless, make it possible to read the r inputs of a butterfly and write r intermediate results in each memory cycle. The address generating circuit that permits the in-place implementation is simple and the same for all the local memories. The data flow has been designed to efficiently exploit the pipelining of the processing section with no cycle loss. This architecture reduces the area by almost 50% of other designs with a similar performance.

A novel neural network approach called "Evolutionary Neural Network (ENN)" is presented for the module orientation problem. The goal of this NP-complete problem is to minimize the total wire length by flipping circuit modules with respect to their vertical and/or horizontal axes of symmetry. In order to achieve high quality VLSI systems, it is strongly desired to solve the problem as quickly as possible in the design cycle. based on the concept of the genetic algorithm, the evolutionary initialization scheme on neuron states is introduced so as to provide a high quality solution within a very short time. The performance of ENN is compared with three heuristic algorithms through simulations on 20 examples with up to 500 modules. The results show that ENN can find the best solutions in the shortest time. Index Terms - Evolutionary initialization scheme, module orientation, neural network, NP-complete, VLSI design.

A high-precision Time-to-Digital-Converter VLSI, TMC-PHX1, was developed for the PHENIX drift chamber. The chip contains 4 channels of TDC with two stages of data buffering and one level of trigger buffering required in very high rate experiments. In addition to a fixed data size readout, the chip also supports a zero-suppression mode readout. The chip records both rising and falling edge timings, and has a least timing count of 0.83 ns/bit and 1.66 ns/bit respectively. A level 1 buffer has a recording depth of 6.8 [micro]sec and a readout FIFO has a depth of 128 words. High precision timing was derived from an asymmetric ring oscillator stabilized with a PLL. The chip runs at 4 times faster clock (37.6 MHz) of the RHIC bunch clock, and was fabricated with 0.5 [[micro]meter] CMOS gate-array technology.

A full-search block-matching architecture which features high throughput, low data input lines, and low memory bandwidth is proposed. It reduces memory I/O requirements by the maximum reuse of search data using on-chip memory. It also promises a high throughput rate by the continuous calculation of all block distortions in a search area using two search data input flows without processing any invalid block distortion, and by the continuous process of the neighbored reference blocks removing the initialization period between blocks. The processor for -16/+15 search ranges, implemented in the total 220k gates using 0.6 [[micro]meter] triple-metal CMOS technology, can operate at a 66 MHz clock rate, and therefore is capable of encoding H.263(4CIF), MPEG2(MP@ML), and other multimedia applications.