Fast low-cost implementation of single-clock-cycle binary comparator

This paper presents a new efficient architecture for the design of fast low-cost single-clock-cycle binary comparators. The proposed 64-bit circuit requires only 1051 transistors and, when implemented by using the ST 90-nm 1-V CMOS technology, it exhibits a running frequency higher than 4 GHz with an average power dissipation of only ~4 mW. Comparison with the fastest comparator known in the literature demonstrates that, at a parity of technology used, the novel architecture is ~12% faster and requires ~69% less transistors. Index Terms--CMOS dynamic circuits, comparator, digital arithmetic, VLSI circuits.