Exploiting circuit emulation for fast hardness evaluation

Hardware designers need effective techniques for early evaluation of the hardening mechanisms adopted in safety-critical VLSI circuits. We propose field-programmable gate-array based circuit emulation for performing fault-injection campaigns. Experimental results show that the new technique is about four orders of magnitude faster than simulation-based fault injection. Index Terms--Fault-injection, FPGA, safety-critical applications, single-event upset (SEU).