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Insight in the thermal degradation phenomena and the relation to phase transformation is presented for cobalt disilicide (CoSi2) on narrow polysilicon lines (linewidth ranging from 30 nm to 1 μm) using electrical and morphological analysis in the temperature range 650–900 °C. When polysilicon lines are scaled laterally to 30 nm, an abrupt CoSi2 sheet resistance increase (>1000 Ω/sq) is observed, which is attributed to silicide agglomeration. At localized positions along the 30-nm Co-silicided lines, Si/silicide layer inversion is observed. At low formation temperature (650 °C), no agglomeration phenomena occur, but incidentally the transition from CoSi into CoSi2 is delayed on the 30-nm-wide polysilicon structures to such an extent that the CoSi2 growth virtually stops. Only using nitrogen implantation through CoSi and a CoSi2 formation temperature of 900 °C, low sheet resistance values are obtained for 35-nm-wide polysilicon lines. Based on the results obtained in the present work, we propose that the abrupt increase in the CoSi2 sheet resistance for the narrow polysilicon lines is a consequence of a decrease in the availability of nucleation sites leading to the reduction of the CoSi/CoSi2 transformation rate, which, in turn, results in the agglomeration of Co silicide at elevated temperature. [ABSTRACT FROM AUTHOR]

We present the data on specific suicide-to-silicon con- tact resistance (ρc) obtained using optimized transmission-line model structures, processed for a broad range of various n- and p-type Si doping levels, with NiSi and PtSi as the suicides. These structures, despite being attractive candidates for embedding in the CMOS processes, have not been used for NiSi, which is the material of choice in modem technologies. In addition, no data-base for NiSi-silicon contact resistance exists, particularly for a broad range of doping levels. This letter provides such a database, using PtSi extensively studied earlier as a reference. [ABSTRACT FROM AUTHOR]

The authors investigate the implications of amorphizing ion implants on the crystalline integrity of sub-20 nm wide fin field-effect transistors (FinFETs). Recrystallization of thin body silicon is not as straightforward as that of bulk silicon because the regrowth direction may be parallel to the silicon surface rather than terminating at it. In sub-20 nm wide FinFETs surface proximity suppresses crystal regrowth and promotes the formation of twin boundary defects in the implanted regions. In the case of a 50 nm amorphization depth, random nucleation and growth leads to polycrystalline silicon formation in the top ∼25 nm of the fin, despite being only ∼25 nm from the crystalline silicon seed. [ABSTRACT FROM AUTHOR]

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni31Si12 FUSI gates on p-channel MOS (PMOS) with good Vt control to short gate lengths (LG = 50 nm, linear Vt of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NISi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni2Si or Ni31Si12 on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni2Si or Ni31Si12 FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% Ion improvement at Ioff = 100 nA/µm) was obtained for Ni31Si12 compared to Ni2Si FUSI gates, as well as a Vt reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS. [ABSTRACT FROM AUTHOR]

Short gate-length Pt full-silicidation (FUSI) (PtSi and Pt2Si) pMOSFETs were fabricated for the first time using a self-aligned Pt-FUSI process, demonstrating scalability (with no linewidth effects) down to ∼ 60-nm gate lengths. The electrical results are compared to the Ni-FUSI (NiSi and Ni31Si12) pMOSFET devices. A low threshold voltage ≤ ∣ -0.29 V∣ was obtained for the Pt2Si-FUSI pMOSFETs on SiON and HfSiON indicating that the Pt2Si FUSI does not suffer from the Fermi-level pinning or gate-dielectric-charge effects on the HfSiON. [ABSTRACT FROM AUTHOR]

The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni2Si, and Ni31Si12. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and Vt control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni2Si processes with excessive thermal budgets, resulting in significant Vt shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth Vt rolloff characteristics was demonstrated for NiSi, Ni2Si, and Ni31Si12 FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni2Si are less than or equal to 25 °C, whereas a single-phase Ni31Si12 is obtained over an ∼ 200 °C temperature range. [ABSTRACT FROM AUTHOR]

In this letter, an n-type near-band edge fully silicided (FUSI) material-Yb-doped Ni FUSI is demonstrated for the first time. By doping Yb into Ni FUSI, it is shown that while maintaining the same equivalent oxide thickness and the similar device reliability, the work function of Ni FUSI (on SiON dielectrics) could .be tuned from 4.72 to 4.22 eV. Yb-doped Ni FUSI is promising for the gate electrode application in n-MOSFETs. [ABSTRACT FROM AUTHOR]

A complete determination of the effective work functions (WF) of NiSi Ni2Si, Ni31Si12 and Ni3Si on HfSiON and on SiO2 is presented. Conditions for formation of fully silicided (FUSI) gates for NiSi2, NiSi, Ni3Si2, Ni2Si, Ni31Si12 and Ni3Si crystalline phases were identified. A double thickness series (HfSiON/SiO2) was used to extract WF on HfSiON accounting for charge effects. A strong effect on WF of Ni content is observed for HfSiON, with higher WF for the Ni-rich silicides suggesting unpinning of the Fermi level. A mild dependence is observed for SiO2. While all Ni-rich silicides have adequate WF for pMOS applications, Ni2Si is most attractive due to its low formation temperature, lower volume expansion and ease of integration. Similar threshold voltages (-0.3 V) were obtained on Ni2Si and Ni31Si12 FUSI HfSiON pMOSFETS. [ABSTRACT FROM AUTHOR]