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The bulge test is a standard technique to characterise thin films, but rarely has it been used to impose fatigue damage and extract subcritical thermo-mechanical data. It features, in contrast to many other methods a biaxial stress state. Since bulge testers have usually been used for static tests, dynamic characterisations of such test stands are widely missing. In this paper, we present and discuss the design of a minimized bulge tester for use at elevated temperatures. We measure and discuss the characteristics of the dynamic pressure loading behaviour and provide curves for pressure amplitudes as well as offset pressures. We investigate oscillating membranes with IR cameras and discuss thermal oscillations and cold spots at cracked membranes.

Thin metal layers, especially those made of copper, are omnipresent in today’s packaging applications as e.g. RDL structures, conductor traces on flexible and stretchable substrates, chip finishes or terminal metallisation, serving electrical, thermal or mechanical purposes. As Cu is very process and size dependent, especially thin layers will display residual stresses, textures, inhomogeneity or damage, all of which determine its properties as e.g. elastic and (visco-)plastic behaviour, fatigue resistance etc. As thin layers are extremely difficult to handle, a characterisation method to examine thermo-mechanical properties of thin metal films within a specimen centred approach (no transfer, no clamping of samples, customised testing equipment) is proposed based on dynamic thin film membrane excitation and resonance spectrum analysis by a simple, fast and low cost method involving electrodynamic excitation. The method produces very good accuracy when benchmarked against scanning laser Doppler vibrometry.

Integration of more functionality and smaller chips into decreasing package volume leads to increasing heat generation. In addition, the use of new compound semiconductors like SiC and GaN require a high thermal conductivity of the interconnect materials. One of the promising solutions is a layer of sintered silver between semiconductor and substrate. The advantages compared to conventional solders are significant. A higher thermal and electrical conductivity in combination with a higher duty temperature due to a higher melting point should enhance the reliability of the package. However, even as the large scale commercial usage of the material has been started by the industry recently, many important details of the mechanical properties and the reliability behavior are still unknown. While the thermal properties could be characterized relatively easy and are quite repeatable and stable, the mechanical properties - important for the reliability - are extremely process-dependent and wide-spreading. The hunt for lowest feasible sintering process parameters - such as temperature, time and especially pressure - even amplify that behavior and led to an impasse in some cases. Also their failure mechanisms, to be identified in lifetime investigations, are yet unknown as well as their stability and predictability. In order to enable prolonged function of these interfaces, thermo-mechanical reliability has to be assured. Within this paper, we show the status of silver sintering and the problems regarding mechanical material characterization found in literature. Additionally, we present a guideline for the mechanical acceleration of reliability experiments by isothermal bending tests. Finally a proof of concept by failure analysis will be presented.

The increased attention for sintered silver as die attach attracts also interest in its reliability assessment. Since the porous joint material shows rate-dependent behaviour at elevated temperature, its visco-plastic behaviour needs to be quantified. Though tensile tests are frequently used for that task is still a challenge to manufacture homogeneous specimens large enough to be safely handled and tensile tested. In this paper the we have presented a comprehensive technology for manufacturing sintered silver specimen for micro bending test. The sample length is about 10 mm but can still be tested with nanoindenter equipment. These specimens were bent at 25 °C at different strain rates. The corresponding stress-strain curves were obtained with transformation functions computed by a FE model. Tensile specimens of sintered silver were manufactured and tensile tested at 25, 100 and 175 °C for investigation of rate dependency and relaxation behaviour. For 25 °C no rate dependency was observed. At 100 °C and 175 °C significant reduction of tensile strength and increase of tensile strain was observed at smaller strain rates. The creep was caused by thermal activation of inner surface diffusion.

Self-assembled Swiss-roll microstructures (SRMs) are widely explored to build up microelectronic devices such as capacitors, transistors, or inductors as well as sensors and lab-in-a-tube systems. These devices often need to be transferred to a special position on a microchip or printed circuit board for the final application. Such a device transfer is typically conducted by a pick-and-place process exerting enormous mechanical loads onto the 3D components that may cause catastrophic failure of the device. Herein, the mechanical deformation behavior of SRMs using experiments and simulations is investigated. SRMs using in situ scanning electron microscopy (SEM) combined with nanoindentation are characterized. This allows us to mimic and characterize mechanical loads as they occur in a pick-and-place process. The deformation response of SRMs depends on three geometrical factors, i.e., the number of windings, compactness of consecutive windings, and inner diameter of the microtube. Nonlinear finite element analysis (FEA) showing good agreement with experiments is performed. It is believed that the insights into the mechanical loading of 3D self-assembled architectures will lead to novel techniques suitable for a new generation of pick-and-place machines operating at the microscale. �� 2021 The Authors. Advanced Engineering Materials published by Wiley-VCH GmbH

Cu sintering is one of the emerging technologies in the field of micro- and power electronics where operating temperatures higher than 150°C are required. At these temperatures, solder joints reach their limits due to high homologous temperatures. Hence, Cu sintered joints can serve as a substitute for these soft solder joints, being advantageous also with respect to thermo-dynamic stability, fatigue resistance, electrical conductance and cost. This paper addresses failure analysis of sintered (neck-based) All-Cu electrical interconnects (NEI) along with soldered SnAg3.5 and transient liquid phase bonded (TLPB) specimens which form an SnCu intermetallic (IMC) and are used in a homogenous Si-Si flip chip assembly for fine pitch interconnects. The SnAg3.5 solder serves as a benchmark for the NEIs and the TLPB joints. All the flip chip specimens were free of underfill material. The test samples were assembled on spring steel substrates using a Silicone-based adhesive for a low stress bond and then put under isothermal accelerated fatigue tests using 4-point bending at low-homologous temperatures (R.T.). The reliability investigation involves monitoring of electrical resistance as a failure indicator for interconnect fatigue. A failure criterion at 20% increase in resistance is defined to establish a correlation between the experimental failure times and resistance. The fatigue behaviour of the joints was also studied using Finite Elements analysis (FEA). The focus of the modelling was towards the behaviour of the critical joint. Cross-sections were prepared and analysed using optical microscopy and SEM to investigate the failure mode and mechanism.

Thin metal layers, especially those made of copper, are omnipresent in today's packaging applications as e.g. RDL structures, conductor traces on flexible and stretchable substrates, chip finishes or terminal metallisation, serving electrical, thermal or mechanical purposes. During operation, thermo-mechanical stress will cause failures in the Cu layers and interfaces over time. As Cu is very process and size dependent, its resistance to fatigue failure needs to be characterised with samples which have undergone identical processing steps as those in the real application. For that purpose, simple specimens and fast testing routines are necessary, some of which may need special loading stages for varying the load variables of interest such as stress amplitude and temperature. This paper addresses fatigue characterisation of thin Cu films on silicon under typical processing conditions on simple and inexpensive but industry-grade samples. Along with them, custom built test stands have been used to handle those specimens appropriately within a specimen-centred approach.

Three-dimensional (3D) electronic systems enable higher integration densities compared to their 2D counterparts, a gain required to meet the demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile devices and other emerging technologies. Through-silicon vias (TSVs) open a pathway to integrate electrical connections for signaling and power delivery through the silicon (Si) carrier used in 3D-stacked microstructures. As a limitation, TSVs induce locally thermomechanical stress in the Si lattice due to a mismatch in the coefficients of thermal expansion between Si and the TSV-filling metals and therefore enforce temperature related expansion and shrinkage during the annealing cycle. This temperature-induced crowding and relaxation of the Si lattice in proximity of the TSV (called “keep-out-zone” forbidden for active device positioning) can cause a variety of issues ranging from stress-induced device performance degradation, interfacial delamination or interconnect failures due to cracking of the bond or even of the entire Si microstructures at stress hotspots upon assembly or operation. Additionally also the interconnect structures induce stress that will overlap with the TSV induced stress.

Heat dissipation from three-dimensional (3D) chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m K and 2.8 W/m K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m K). Critical parameters in the formation of sequential thermal underfills will be discussed, such as the material choice and refinement, as well as the characteristics and limitations of the individual process steps. Guidelines are provided on dry versus wet filling of filler particles, the optimal bimodal nanosuspension formulation and matrix material feed, and the over-pressure cure to mitigate voids in the underfill during backfilling. Finally, the sequential filling process is successfully applied on microprocessor demonstrator modules, without any detectable sign of degradation after 1500 thermal cycles, as well as to a two-die chip stack. The morphology and performance of the novel underfills are further discussed, ranging from particle arrangements in the filler particle bed, to cracks formed in the necks. The thermal and mechanical performance is benchmarked with respect to the capillary thermal and mechanical underfills. Finally, the thermal improvements within a chip stack are discussed. An 8 - or 16-die chip stack can dissipate 46% and 65% more power with the optimized neck-based thermal underfill than with a state-of-the-artcapillary thermal underfill.

Flip chip interconnects purely made out of Cu, so-called all-Cu interconnects, have the potential to overcome the present current capacity limit of state-of-the-art solder based interconnects, while meeting the demand for ever decreasing interconnect pitches. Parasitic effects in solder based interconnects, caused by interdiffusion of various metals, are mitigated in all-Cu interconnects. In this work, all-Cu interconnects were formed by the use of low temperature and pressureless sintering of Cu nanoparticles. Thereby, a Cu paste material was applied between the Cu pillars of a silicon chip and the Cu pads on a silicon substrate by a dip transfer method. The electrical and mechanical properties of sintered Cu were characterized on films of the same Cu pastes. The porous films resulted in 4.4 times higher electrical resistivity and one order of magnitude reduced mechanical stiffness and tensile strength compared to bulk Cu. All-Cu interconnects with a diameter of 30 µm and a pitch of 100 µm were formed with an optimized Cu particle distribution and sintering procedure. Resistances down to 1.7 ± 0.5 mO were measured for these all-Cu interconnects which is comparable to solder based benchmark interconnects. However, the porosity of the sintered Cu interconnect results in lower shear strength compared to the solder benchmark.

Heat dissipation from 3D chip stacks can cause large thermal gradients due to the accumulation of dissipated heat and thermal interfaces from each integrated die. To reduce the overall thermal resistance and thereby the thermal gradients, this publication will provide an overview of several studies on the formation of sequential thermal underfills that result in percolation and quasi-areal thermal contacts between the filler particles in the composite material. The quasi-areal contacts are formed from nanoparticles self-assembled by capillary bridging, so-called necks. Thermal conductivities of up to 2.5 W/m-K and 2.8 W/m-K were demonstrated experimentally for the percolating and the neck-based underfills, respectively. This is a substantial improvement with respect to a state-of-the-art capillary thermal underfill (0.7 W/m-K).

The cost and the package size driven size reduction of semiconductors lead to much higher heat generation. Also the use of new high power technologies on the basis of SiC produces is a need for high conductivity of the interconnect materials. Therefore the requirements for mechanical, thermal and electrical properties of interconnect materials increase compared to existing eutectic solder and glue materials. One of the promising solutions is a sintered layer between semiconductor and substrate. Especially from sintered layers one expects very high thermal conductivity and good mechanical properties in the package. Therefore, new materials with advanced behavior exploiting nano-effects have been developed in the last years. However, processes to use such materials as TIM-material for power applications are still to be optimized for e.g. zero pressure processing. So also their failure mechanisms, to be identified in lifetime investigations, are yet unknown as well as their stability. In order to enable prolonged function of these interfaces, thermo-mechanical reliability has to be assured. Dedicated fatigue tests have to be conducted to evaluate lifetime under relevant testing conditions, then failure mechanisms such as delamination or cracking have to be identified, understood and quantitatively condensed into a lifetime model to predict reliability for future designs. Within this paper, we present a guideline for the mechanical acceleration of reliability experiments for end-of-lifetime prognostics as well as the state of the art regarding reliability and mechanical characterization of sintered silver.

This paper addresses both, the thermal and the thermo-mechanical performance of percolating thermal underfill applied flip-chip packages. We present a thermal test platform in flip-chip package design allowing the thermal conductivity of any underfill to be measured at package scale. We give details about design technology and current fabrication status. We benchmarked the thermal performance of the platform with percolated thermal underfill against the capillary thermal underfill case. In a layout with peripheral solder bumps the performance benefit related to heat dissipation of an overall system with percolating thermal underfill can be over 50% for liquid cooling and over 25% for enforced convection. The improvement for natural convection, typical in mobile environment, is 5% in the best considered case. We also present a study of the thermo-mechanical performance of the flip chip test platform during thermo-shock cycling by the aid of finite element (FE) tools at the critical regions of interest. We benchmarked the percolating thermal underfill against capillary mechanical underfill and capillary thermal underfill. For that investigation we used an effective material merging a visco-elastic polymer and a visco-plastic solder for saving computation time. In the percolating thermal underfill applied package, we've found slightly higher risk of delamination at the die | underfill interface but very low fillet loads compared to conventional underfill. The risk of solder fatigue is significantly lower and the risk of die cracking is 25% higher for percolating than for the capillary underfills.

Internal stresses are very important for the performance of protective hard coatings. Tensile stresses favour the formation and propagation of cracks, inducing fracture and corrosion. Medium compressive stresses hinder fatigue. But high compressive stresses, typically for hard coatings produced by PVD (physical vapour deposition) processes, support delamination in order to relax the stored elastic energy. However notwithstanding its relevance, the internal stresses are only seldom used for the optimisation and quality control of hard coatings in industry. This unsatisfying situation is caused by the deficit in efficient measuring methods. The results of thin sheets, where the stresses can be simply measured by their curvature, are not necessarily representative for the coating of thicker parts. The conventional XRD (X-ray Diffraction), based on angle-dispersive evaluation needs expensive devices and is rather time consuming. The energy-dispersive technique opens new possibilities. It is based on polychromatic radiation. The interference of the lattice plane reflections corresponding to the Bragg-equation is investigated by the diffraction intensity of the different wavelength (or photon energies), not by varying the Bragg-angle as in conventional XRD. Hence, the whole diffraction pattern can be obtained in one shoot without the use of any goniometer. This allows the construction of small and compact measuring devices and the reduction of measuring time to a few minutes. The capability of the ED-XRD (Energy Dispersive X-ray Diffraction) is demonstrated for titanium nitride and chromium nitride films deposited by cathodic vacuum arc with varying parameters. Comparisons were made with the much more time-consuming AD-XRD (Angle Dispersive X-ray Diffraction) for residual stress analysis. The results of both methods are in good agreement.

A dual-side cooling topology is proposed that is achieved by embedding a power insert into the organic substrate of a chip or chip stack. The power insert consists of vertical copper lamellas supporting lateral current feed in addition to vertical heat dissipation at minimal electrical and thermal gradients. The lateral current feed capability is key to enable the introduction of the cold plate on the bottom side of the substrate.

To satisfy the increasing need in today's industry for high performance, more complex chips are being designed. These chips, when integrated in 3D packages, have a high energy density and require new and innovative cooling strategies as many of them are designed as flip-chip assemblies, usually requiring back-side cooling. Classical underfills currently used offer poor thermal conductivity. But cooling through the underfill would enable cost-efficient and low complexity cooling solutions. For this purpose, thermal underfills with percolating fillers and necks are currently under development. They are to provide a significant improvement in thermal conductivity to classical capillary underfills and will find applications in, for example, 3D integrated packages to improve heat dissipation. The idea behind the percolating thermal underfill (PTU) comprises a sequential joint forming process ensuring a high fill fraction. Although flip chip technology has been well described, the addition of the neck based percolating underfill could entail several new thermo-mechanical reliability concerns that need to be studied using a physics of failure approach, since the PTU exhibits vastly different thermo-mechanical behavior, giving rise to possible new failure mechanisms and locations. This paper in particular deals with FE simulations carried out to understand different key aspects of the thermal underfill and to study the effects of the increased underfill stiffness at these locations. The simulations are implemented using detailed elastic, plastic, visco-elastic and visco-plastic material data. In case of larger models a complexity reduction is required and implemented by using effective material data to improve computational time.

This paper covers a detailed preliminary study to micro bending tests used to obtain the mechanical properties of nanoparticles as used in advanced electrical or thermal joints. A method for direct, easy, fast and highly accurate transformation of an experimental force-displacement-curve into the corresponding σ-e-curve is presented. That gives access to the elastic and plastic properties of the material. No additional profiling measurements are necessary. The authors focus on the theoretical background of both, the bending test itself as well as the transformation. Both is discussed in detail by utilizing the results of a finite elements model which simulates a micro bending test.

Three different experimental methods have been used to determine mechanical stresses in silicon nearby tungsten TSVs - HR-XRD performed at a synchrotron beamline, microRaman spectroscopy and stress relief techniques put into effect by FIB ion milling. All methods possess, to a different extend, high spatial resolution capabilities. However they differ in their sensitivity and response to the particular stress tensor components relevant for the residual stress state nearby TSV structures. Stress measurements were performed on test samples with TSVs in thinned dies, which were SLID bonded to a thicker Si substrate die. The measurements captured stresses introduced by the W-TSV as well as by the wafer bonding process. A stress range from several MPa to hundreds of MPa could have been covered with a spatial allocation ranging from 100 nm to tens of microns. Measurement results were compared to each other and to simulated stresses from finite element analysis.

In this paper a simulation is presented which tracks photons through complex material systems. Besides the usual Compton and Rayleigh scattering that is covered in high energy radiography simulations the presented model considers Bragg-Laue diffraction. The implementation bases on a Monte Carlo code to account for the scattering during radiography. In this paper first results of the simulation are presented. A simple radiation as well as a diffraction experiment was setup. The attenuation coefficient and the position of the diffraction peaks drawn out of the simulation were in good agreement with the literature.