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Here, we report on the growth of GeTe2 thin films, a metastable phase. The GeTe2 film was found to be a semiconductor with a layered structure.

We have developed a simple and straightforward way to realize controlled postdoping toward 2D transition metal dichalcogenides (TMDs). The key idea is to use low-kinetic-energy dopant beams and a high-flux chalcogen beam simultaneously, leading to substitutional doping with controlled dopant densities. Atomic-resolution transmission electron microscopy has revealed that dopant atoms injected toward TMDs are incorporated substitutionally into the hexagonal framework of TMDs. The electronic properties of doped TMDs (Nb-doped WSe2) have shown drastic change and p-type action with more than 2 orders of magnitude increase in current. Position-selective doping has also been demonstrated by the postdoping toward TMDs with a patterned mask on the surface. The postdoping method developed in this work can be a versatile tool for 2D-based next-generation electronics in the future.

The control of crystal polymorphism and exploration of metastable, two-dimensional, 1T'-phase, transition-metal dichalcogenides (TMDs) have received considerable research attention. 1T'-phase TMDs are expected to offer various opportunities for the study of basic condensed matter physics and for its use in important applications, such as devices with topological states for quantum computing, low-resistance contact for semiconducting TMDs, energy storage devices, and as hydrogen evolution catalysts. However, due to the high energy difference and phase change barrier between 1T' and the more stable 2H-phase, there are few methods that can be used to obtain monolayer 1T'-phase TMDs. Here, we report on the chemical vapor deposition (CVD) growth of 1T'-phase WS

Continuous scaling of device dimension pushed Si channel to its physical limit, alternative high mobility channels such as (Si)Ge and (In)GaAs have been considered to replace Si to further enhance CMOS performance. In the meantime, ultrathin body (UTB) semiconductor-on-insulator is compulsory structure for improved gate control and immunity against short channel effects in the ultimately scaled high performance and low power dissipation CMOS. To realize stacked multi- channel semiconductor-on-insulator platform on current mainstream Si wafers, layer transfer technology [1-3] utilizing direct bonding and selective etching was developed to integrate (Si)Ge or (In)GaAs channels on Si, showing great potential for ultimate device structures with heterogeneous integration. Figure 1(a) is the process flow for integrating InGaAs channel onto SiGe-on-insulator (SGOI) structure utilizing layer transfer technology [4]. It started with bottom SGOI pMOSFET fabrication. The SGOI structure was realized by 2-step Ge condensation technique, resulting in Ge content of 70%. After high k metal gate process, self-aligned Ni-SiGe alloy was formed as S/D metal. Subsequently, SiO2 interlayer was deposited by CVD, followed by CMP planarization. Then, InGaAs grown on InP was directly bonded onto SiO2 and InP substrates were selectively etched away. Finally, the top InGaAsOI nMOSFET fabrication and metal interconnection completed the CMOS fabrication. Fig. 1(b) shows the cross-sectional TEM images of fabricated InGaAs/SiGe channel stacked CMOS. Well aligned top and bottom devices are seen without any distinct defects. Figures 2 is a schematic flow for fabricating Ge/Si double channel-on-insulator structure by low temperature hetero-layer bonding technology (LT-HBT). The technology starts with the preparation of donor wafers (Fig. 2(a)) for the top Ge channel layer and host wafers (Fig. 2(b)) for the bottom Si channel layer. For donor wafers, a 200-nm-thick Ge was epitaxially grown on SOI wafer by reduced pressure CVD. After CMP planarization, ALD SiO2 is deposited onto Ge. For host wafers, implantation and dopant activation were carried out, followed by chemical treatment for Si oxidation. After surface activation by room temperature chemical treatment (Fig. 2(c)), the direct wafer bonding of both SiO2 surface was performed at 200 °C in a press machine (Fig. 2(d)). Then, the Si substrate of the donor wafer was removed with deep RIE. At this time, the BOX layer of the donor wafer serves as an etch-stop layer. Subsequently, the BOX layer and thin Si layer of the donor wafer were removed selectively in HF and TMAH solution, respectively (Fig. 2(f)). To precise control the top Ge channel thickness, a series of low damage etching process was adapted to thin down Ge (Fig. 2(g)). The realized double channel structure is fully isolated with an insulating insertion layer,[5] which is very promising for realizing novel complementary FET (CFET) with minimum process steps. The cross-sectional TEM image of Ge/Si stacked channel of CFET after high k metal gate process is demonstrated in Fig. 2(h). Even more multiple stacks can be realized by using LT-HBT. A vertically stacked three-layer structure with 2 bottom Si layers and 1 top Ge layers is also demonstrated using SOI-based donor wafers in Fig. 3, indicating the highly integrated density channel structure is possible. The feasibility of layer transfer technology has been proved for multi-channel structure with high mobility channels for N2 node and beyond. Acknowledgement This work was supported by JST Japan-Taiwan Collaborative Research Program, Grant Number JPMJKB1902, Japan and the Ministry of Science and Technology under Grant Number MOST-109-2628-E-492-001-MY3, 109-2923-E-492-001-MY3, 107-2221-E-492-016-MY3. References [1] T. Maeda et al., Appl. Phys. Lett. 109, 262104 (2016). [2] W. H. Chang et al., Mater. Sci. Semicond. Process 70, 123 (2017). [3]W. H. Chang et al., IEEE Trans. Electron Device 64, 4615 (2017). [4] T. Irisawa et al., VLSI 146 (2014). [5] T. Z. Hong et al., IEDM (2020) Figure 1

Monolithic 3D (M3D) integration has been thought of as an attractive idea to realize multi-functional heterogeneous integration devices. M3D integration enables us to combine logic devices with different functional devices such as memory, sensor, or optics to create extremely compact and efficient system-on-chips. Ge and III-V compound semiconductors are expected to be implemented as high mobility channel materials and optical components which cannot be realized with Si. The layer transfer technique with low processing temperature has great potential for stacking non-lattice-matched crystalline materials for M3D ICs. Here, we discuss the layer transfer technology utilizing high quality epitaxial growth, low-temperature direct bonding and advanced epitaxial lift-off (ELO) process, which reveals the applicability of transferred layers for heterogeneous integration. The low temperature ELO process is essential for realizing reliable layer transfer with different materials because the process is almost free from the issues of thermal expansion mismatch. Process flow of GaAs or Ge layer transfer with ELO process is described in Fig. 1. First of all, a lattice-matched single crystal GaAs or Ge layer is epitaxially grown on GaAs substrate with an AlAs release layer by MOCVD. Subsequently, Al2O3 layer is deposited on the epitaxial layer by atomic layer deposition (ALD). ALD Al2O3 layer serves as the buried oxide (BOX) and the passivation layer for Ge or GaAs surface. Then, Ge or GaAs layer is patterned using photolithography. The patterned GaAs or Ge/AlAs/GaAs donor wafer is then bonded on host substrate by direct bonding technique with wet activation process. Finally, the epitaxial GaAs or Ge layer is transferred on host substrates by splitting GaAs donor wafer from AlAs layer with HCl side etching thanks to extremely high etching selectivity. Note that the fabrication of patterned transfer layer is effective in shortening the required time of ELO process. In this ELO process, the thickness of a transferred layer can be control by epitaxial layer thickness. After the layer transfer process, the released donor GaAs wafer can be reclaimed and reused for the subsequent re-epitaxial growth to reduce the process cost. Figs. 2 (a) and (b) show cross-sectional SEM and TEM images of fabricated GeOI substrate with different BOX structures. Ge pattern edge shows no peeling from SiO2(100nm)/Si substrate, indicating strong bonding strength at the pattern edge. In Fig. 2 (b), the bonding interface is clearly observed at Al2O3(5nm)/SiO2(50nm) interface formed by the wet activation process. The bonding interface exhibits very smooth and no defect. There is no observable defect in transferred Ge layer, suggesting dislocation density is below TEM detection limit. Compared to Smart-CutTM technique, ELO process has significant advantages in terms of crystal quality, thickness control and the surface flatness thanks to totally low temperature processing. To reduce wafer-scale thickness variation, etching stopper (ES) technique with high etching selectivity is quite useful. As a donor wafer, we prepare Ge active layer (20nm)/SiGe ES layer (5nm)/Ge buffer layer/AlAs/GaAs structures. Here, the SiGe layer serves as ES against the etching of Ge buffer layer to control the final GeOI thickness and attain the wafer-scale thickness uniformity. In addition, Si passivation on Ge surface was performed during initial epitaxial growth of donor wafer since Si passivation was proved to be effective in reducing interfacial trap density (D it) between Ge and oxide. After ELO process, Ge buffer layer /SiGe ES layer/Ge active layer / Al2O3 /SiO2/Si heterostructure was obtained. Then, the top Ge buffer layer was removed in HCl/H2O2 solution. We found the etching selectivity was more than 30 between Ge and SiGe layer, which is high enough to yield very smooth SiGe surface. Finally, SiGe layer was removed by TMAH preferentially. Further conformal thinning of Ge active layer was performed by the cyclic dry oxidation/wet digital etching (DE) at room temperature. In addition to thickness control with the etching rate of about 0.8 nm/cycle, it is found that dozens digital etching (DDE) process is effective for reducing Ge surface roughness. Finally, UTB GeOI substrates with high crystal quality down to 3 nm have been successfully fabricated through SiGe ES and DDE processes. Ultra-smooth GeOI surface with reduced thickness fluctuation was confirmed after DDE by TEM cross-sectional images, resulting in significant improvement of device performances. Figure 1

Current nanodevices face many difficulties, one of which is the well-known issue of short-channel effects (SCEs). SCEs cause significant degradation in device characteristics. To overcome this issue, 2D materials have been studied since 2000. This article reveals the motivation for research on 2D materials for device application.

Advanced channel formation technologies called HEtero-layer-lift-off utilizing SiGe heteroepitaxy have been realized for fabricating ultrathin body (UTB) Ge-on-insulator (GeOI) structures. Insertion of SiGe etching stop layer was found to be effective for reducing GeOI body thickness ( $T_{\mathrm {body}}$ ) fluctuation. Backside Si passivation for Ge/buried oxide interface has been verified to suppress backside Coulomb scattering and help to induce volume inversion effect. With improvement of backside interfacial quality and precise control of GeOI $T_{\mathrm {body}}$ , primary carrier scattering factors in GeOI channel have been effectively reduced, resulting in significant improvement of hole mobility. High hole mobility of ~150 cm2/Vs in UTB GeOI pMOSFETs without strain technology has been demonstrated, which also outperformed Si universal mobility by 1.5 times even under $T_{\mathrm {body}}$ of 9 nm. With low-thermal-budget process compatibility, UTB GeOI platform is very promising for future Ge large-scale integrated circuits devices used in monolithic 3-D integration scheme.

Atomically thin transition-metal dichalcogenides (TMDs) are attracting great interest for future electronic applications. Even though much effort has been devoted to preparing large-area, high-quality TMDs over the past few years, the samples are usually grown on substrate surfaces. Here, we demonstrate the direct growth of a MoS2 monolayer at the interface between a Au film and a SiO2 substrate. MoS2 grains were nucleated below Au films deposited on SiO2via interface diffusion and then grown into a continuous MoS2 film. By programming the Au pattern deposited, controlled growth of MoS2 with the desired size and geometry was achieved over preferred locations, facilitating its integration into functional field-effect transistors. Our findings elucidate the fabrication of a two-dimensional semiconductor at the interface of bulk three-dimensional solids, providing a novel means for establishing a clean interface junction. It also offers a promising alternative to the site-selective synthesis of TMDs, which is expected to aid the fabrication of TMD-based nanodevices.

Nanoelectronics require semiconductor nanomaterials with high electron mobility like Ge nanolayers. Phonon and electron states in nanolayers undergo size-dependent changes induced by confinement and surface effects. Confined electrons and acoustic phonons determine layer optical, electric and thermal properties. Despite scientific and practical significance, their experimental studies in individual nanolayers are still lacking. Thanks to recent progress in the fabrication of high-quality nanolayers, here, we report the thickness dependencies of Raman spectra of acoustic phonons and optical spectra of electrons confined in germanium-on-insulator (GeOI) nanolayers with thicknesses TGeOI = 1–20 nm. We show that for TGeOI > 5 nm, both GeOI acoustic phonon Raman spectra and the E1 electron energy gap display dependencies on TGeOI which are reasonably described by the corresponding phonon and electron confinement theories. Accordingly, TGeOI can be probed using acoustic phonon Raman spectra at TGeOI > 5 nm. However, both confinement theories fail to describe GeOI thickness dependencies at TGeOI < 5 nm. We attribute this discrepancy to an increased influence of the Ge–GeO2 interface disorder with TGeOI reduction. The acoustic phonon data suggest a decrease of Ge normal-to-the-layer longitudinal sound velocity. Generation of interface-disorder-induced dispersionless phonons might contribute to this. The change in GeOI phonon properties at TGeOI < 5 nm might influence E1(TGeOI) dependence via a change in the GeOI electron–phonon interaction. We demonstrate that the Al2O3 coating improves the agreement between experimental and confinement theories, probably, via reduction of disorder at the Ge–GeOx–Al2O3-interface. Our results are important for control of nanolayer-confined electrons and phonons with benefits for modern and future nanoelectronic devices.

To maximize the potential of transition-metal dichalcogenides (TMDCs) in device applications, the development of a sophisticated technique for stable and highly efficient carrier doping is critical. Here, we report the efficient n-type doping of monolayer MoS2 using KOH/benzo-18-crown-6, resulting in a doped TMDC that is air-stable. MoS2 field-effect transistors show an increase in on-current of three orders of magnitude and degenerate the n-type behaviour with high air-stability for ∼1 month as the dopant concentration increases. Transport measurements indicate a high electron density of 3.4 × 1013 cm-2 and metallic-type temperature dependence for highly doped MoS2. First-principles calculations support electron doping via surface charge transfer from the K/benzo-18-crown-6 complex to monolayer MoS2. Patterned doping is demonstrated to improve the contact resistance in MoS2-based devices.

For the first time, we demonstrate heterogeneous complementary FETs (hCFETs) with Ge and Si channels fabricated with a layer transfer technique. The 3D channel stacking integration particularly employs a low-temperature (200 °C) hetero-layers bonding technique (LT-HBT) realized by a surface activating chemical treatment at room temperature, enabling Ge channels bonded onto Si wafers. Furthermore, to obtain symmetric performance in n/p FETs, a multi-channel structure of two-channel Si and one-channel Ge is also implemented. Wafer-scale LT-HBT is demonstrated successfully, showing new opportunities for the ultimate device footprint scaling with heterogeneous integration.

The impact of channel flattening process, dozen digital etching (DDE), on device performance and reliability of Ge nMOSFETs with different surfaces of (100), (110) and (111) has been systematically investigated. It was found, for the first time, that DDE improves not only electron mobility but also gate oxide reliability, especially on Ge (100). Decrease of surface roughness, as well as interfacial/bulk trap densities in gate oxide could explain these phenomena. Thanks to DDE, the electron mobility of Ge (100) devices can compete with those of Ge (111) devices while possessing higher reliability.

Germanium-on-insulator (GeOI) structures with a surface orientation of (111) have been successfully fabricated by using low thermal budget epitaxial-lift-off (ELO) technology via direct bonding and selective etching. The material characteristics and transport properties of the Ge(111)OI structure have been systematically investigated through secondary-ion mass spectrometry, Raman spectroscopy, X-ray diffraction, high-resolution transmission electron microscope, and Hall measurement. The transferred Ge (111) layer remained almost intact from the as-grown epitaxial layers, indicating the benefits of ELO technology. The low thermal budget ELO technology demonstrated in this work is promising to integrate Ge channels with different surface orientations on Si (100) substrates for future monolithic 3D applications.

High quality ultrathin body (UTB)-Ge-on-insulator (GeOI) substrates have been fabricated with advanced layer transfer technology called HEtero-Layer-Lift-Off. With precise control of interfacial qualities, Ge crystallinity and thickness fluctuation in GeOI substrates, electron mobility of UTB-GeOI nMOSFETs with body thickness ( $T_{\text {body}}$ ) from 20 to 3 nm has been systematically investigated. A significant electron mobility enhancement as $T_{\text {body}}$ scaling below 13 nm has been observed. This newly found mobility enhancement induced by channel thickness scaling could be attributed to the modulation of energy band structure in (001) confined UTB GeOI, where electron effective mass reduction is predicted by first-principle calculation.

The ultra thin body (UTB) SiGe on insulator (SGOI) substrate with body thickness of only 5 nm has been fabricated by hetero-layer transfer technique with highly selective wet etching. According to Raman spectroscopy, UTB-SiGe layer with Ge fraction of 67% and +1% partially tensile strain was transferred onto the SiO2/Si host substrate without the strain degradation. To present the feasibility of UTB-SGOI substrate, a well-behaved performance of 2-μm-gate-length normally off UTB-SGOI nMOSFET has also been demonstrated.

Two-dimensional (2D) transition-metal dichalcogenides have attracted a considerable amount of attention because of their potential for post-silicon device applications, as well as for exploring fundamental physics in an ideal 2D system. We tested the chemical vapour deposition (CVD) of WS2 using the gaseous precursors WF6 and H2S, augmented by the Na-assistance method. When Na was present during growth, the process created triangle-shaped WS2 crystals that were 10 μm in size and exhibited semiconducting characteristics. By contrast, the Na-free growth of WS2 resulted in a continuous film with metallic behaviour. These results clearly demonstrate that alkali-metal assistance is valid even in applications of gas-source CVD without oxygen-containing species, where intermediates comprising Na, W, and S can play an important role. We observed that the WS2 crystals grown by gas-source CVD exhibited a narrow size distribution when compared with crystals grown by conventional solid-source CVD, indicating that the crystal nucleation occurred almost simultaneously across the substrate, and that uniform lateral growth was dominant afterwards. This phenomenon was attributed to the suppression of inhomogeneous nucleation through the fast and uniform diffusion of the gas-phase precursors, supported by the Na-assisted suppression of the fast reactions between WF6 and H2S.

Atomically thin transition-metal dichalcogenides (TMDs) are attracting great interest for future electronic applications. Even though much effort has been devoted to preparing large-area, high-quality TMDs over the past few years, the samples are usually grown on substrate surfaces. Here, we demonstrate the direct growth of a MoS

We perform Technology computer-aided (TCAD) simulations for 2D material based Junctionless FET (JLFET) and investigate the effect of the fringe-field interaction between the source/drain (S/D) electrodes and the 2D channel. We find that subthreshold slope (SS) gets worse by the fringe-field interaction, and the degradation of the SS becomes serious when the work function difference becomes large. Interestingly, we also find that high drain voltage recovers the degradation of the SS.

We demonstrated high-quality single crystal Germanium (Ge) layer transferred on arbitrary substrates, such as Si, glass, and flexible plastic substrates utilizing direct bonding and epitaxial lift-off (ELO) techniques. Owing to Ge epitaxial growth on GaAs substrates with AlAs release layer, we successfully transferred epitaxial Ge layers on arbitrary substrates with a wide range of thickness from several um to $\sim 1$ nm. This layer tranfer approach enables us to realize Ge-based monolithic 3D devices without degradation of Ge crystalline quality.

High-k dielectrics of Al 2 O 3 , HfO 2 and ZrO 2 have been directly deposited on MoS 2 through plasma enhanced atomic layer deposition (PEALD). Among them, PEALD-ZrO 2 /MoS 2 has shown the highest interfacial quality with high dielectric constant and sharp interface, characterized by CV, XPS and TEM measurements. Dual gate CVD-grown MoS 2 MOSFETs using PEALD-ZrO 2 as a top-gate dielectric has also been demonstrated.

Backside Si passivation for ultrathin boy (UTB) GeOI has been verified to suppress Coulomb scattering from Ge/buried oxide (BOX) interface. With improvement of backside interfacial quality, primary carrier scattering factors in GeOI channel have been effectively reduced, resulting in significant enhancement of hole mobility. The hole mobility improvement has been proved through device characterizations of UTB GeOI $p$ MOSFETs and Hall measurements. UTB GeOI platform formed by only low thermal budget processes is very promising for future Ge large scale integrated (LSI) circuits devices in monolithic 3D (M3D) integration scheme.

Scalable chemical vapor deposition (CVD) of two-dimensional semiconducting materials such as MoS2 and WS2 is a key technology for the application of these materials in real devices. In this work, we demonstrate the growth behavior of WS2 crystals from gaseous precursors, i.e. H2S and WF6, under alkali-metal-free conditions. The WS2 crystal growth exhibits layer-by-layer growth, and its behaviors, such as nucleation and lateral growth, are a thermally activated process: the temperature-dependent grain size and density are well fitted by the Arrhenius equation. The obtained WS2 crystal shows quality comparable to that obtained from metal oxides: the WS2 film shows sharp photoluminescence with a peak width of 54 meV and n-type field-effect transistor operation. Optimizing the growth conditions enabled us to obtain WS2 crystals with a grain size of ∼1.5 μm, which is the largest size ever reported for a transition-metal dichalcogenide grown by gas-source CVD without an alkali-metal promotor.

To enhance the feasibility of 2-dimensional transition metal dichalcogenides (TMDCs) channels in future nano-electronic and optoelectronic devices, a top gate device structure fabricated with very-large-scale-integration compatible process is mandatory. High-κ dielectric ZrO2 has been directly deposited on MoS2 through low-temperature atomic layer deposition (ALD) without any surface protection layers. The uniform growth of ZrO2 on MoS2 was confirmed to be caused by the physical adsorption, resulting in the suppressed interfacial oxidation and the reduced damage of monolayer (1L) MoS2 channel. Low thermal budget post-deposition annealing was found to be effective for reducing interfacial traps between ZrO2 and MoS2 interface, thus enhancing the device performances of 1L MoS2 nMOSFETs. Low capacitance equivalent thickness (CET) of ZrO2 of 2.3 nm has been achieved while maintaining decent device performance, indicating low-temperature ALD is promising for future TMDC top gate devices with a high-quality interface and thin CET.

The impact of channel flattening process, dozen digital etching (DDE), which is several dozen cyclic treatments of plasma oxidation and oxide wet etching, on device performance and reliability of Ge(1 0 0) nMOSFETs has been systematically investigated. It was found that DDE improves not only electron mobility but also Positive Bias Temperature Instability (PBTI). The PBTI degradation was found related to the pre-existing bulk traps inside gate stack instead of interfacial traps generation. DDE is considered a promising technique for constructing ultra-scaled Ge 3D channel architecture such as nanowire or nanosheet for high performance CMOS devices.

Bilayer WSe2/MoSe2 van der Waals heterostructures have been directly grown on SiO2/Si substrates by 2-step chemical vapor deposition method. Bilayer nature with well aligned in-plane crystal orientation has been confirmed by Raman and transmission electron microscopy characterizations. Back gate transistors having bilayer WSe2/MoSe2 in the source side have been fabricated and high on/off ratio larger than 106 have been obtained. Gate-induced modulation of electron direct tunneling from source metal to the bottom MoSe2 layer and band to band tunneling from the valence band of WSe2 to the conduction band of MoSe2 can be an operation mechanism. Thanks to the drastic reduction of contact resistance due to the change of electron injection configuration, from edge to area injection at the source electrode, much higher on/off ratio with steeper switching was obtained in the WSe2/MoSe2 bilayer device as compared with the monolayer MoSe2 and WSe2 devices.

International audience; Recent findings show significant enhancement of both the 488nm-excitation Raman signal and the electron mobility as ultrathin-body Ge-on-insulator (UTB GeOI) thickness (TGeOI) scaling below 13nm [1,2]. These phenomena could be attributed to a quantum size effect causing a change in the Ge energy band structure. Here, we study the characteristics of electron and acoustic phonon confinement in UTB GeOI with TGeOI = 1-20 nm. We observe electron band gap enlargement with a decrease in TGeOI and extract E1 exciton transverse effective mass value ~ 0.07 m0. Another size effect is the GeOI absorption enhancement associated with the increase in the electron density of states (DOS). For TGeOI < 5 nm, the E1(TGeOI) dependence suggests the influence of size-induced changes in the electron-phonon interaction on the E1 gap. This idea is supported by low-frequency Raman spectroscopy of GeOI confined acoustic phonons showing a significant change in acoustic phonon spectrum at TGeOI < 5 nm

Advanced channel formation technologies, such as precise control of GeOI body thickness (T body ), surface roughness and interfacial quality, utilizing Si-passivation/Ge-channel/SiGe hetero-epitaxy and Ge digital etching (DE) techniques were implemented for UTB GeOI structure. Si passivation for Ge/BOX interface has been verified to suppress Coulomb scattering owing to better interfacial quality. Insertion of SiGe etching stop (ES) layer and dozens DE (DDE) were found to be quite effective to reduce T body fluctuation as well as surface roughness, resulting in the significant improvement of mobility. As a result, we have demonstrated record high hole mobility of ~200 cm2/Vs in UTB GeOI pMOSFETs without the strain technology, which outperforms Si universal mobility by 2 times even under T body of 9 nm.

Ultra-thin-body (UTB) germanium-on-insulator (GeOI) substrates have been fabricated utilizing advanced HEtero- Layer-Lift-Off (HELLO) technology. HELLO technology is effective in mitigating thickness fluctuation issue in UTB GeOI during Ge thinning process. As a result, well-known hole mobility degradation while scaling body thickness (t body ) in UTB GeOI pMOSFETs has been suppressed. The mechanism of enhanced hole mobility in UTB GeOI pMOSFETs was also investigated through low temperature electrical measurement. The hole mobility in 9-nm-thick GeOI devices fabricated with HELLO technology showed larger temperature dependence, indicating the release of thickness fluctuation scattering.

We have demonstrated position controlled CVD growth of metal dichacogenide (WS 2 and SnS 2 ) by using patterned Si substrates. It was found that step edges effectively induced crystal nucleation and lateral crystal growth of 2D materials proceeded from there. Gas source CVD system applicable to industrial production has also been developed and WS 2 and SnS 2 synthesis have been confirmed.

Electron mobility of ultra thin body (UTB) GeOI «MOSFETs with body thickness (T body ) down to 3 nm has been systematically investigated and significant mobility enhancement with decreasing T body has been observed for the first time. This channel thickness scaling induced mobility enhancement can be attributed to the unique physical property of ultra thin Ge where the electron effective mass reduces with scaling T body through the band structure modification.

Ion implantation after germanidation (IAG) technique has been implemented for low thermal budget bulk Ge and UTB-GeOI n- and p-MOSFETs. Dopant segregation at NiGe/Ge interface by low temperature drive-in annealing has an advantage in forming an abrupt metallic source/drain (S/D) junction, which is not only effective for bulk Ge but also for UTB-GeOI substrate. IAG technique is proved to be a low thermal budget process for both Ge n- and p-MOSFETs with a high I on -I off ratio and low parasitic resistance.

Germanium is recognized as new channel material to be introduced in near future CMOS technologies. The advantages are the high hole mobility, the high p-type dopant activation and the low contact resistivity, whereas the smaller band gap results in higher off state current than Si devices. Therefore, Ge-MOSFETs are considered to be most promising to use as a pMOS counterpart of III-V nMOSFETs for high-performance CMOS devices. In order to suppress the off leakage current, Ge-on-insulator (GeOI) substrates may be preferable than bulk substrates. On the other hand, the low thermal budget of the fabrication processes can provide another opportunity for Ge devices. Sequentially stackable COMS devices may be a possible application for 3D-LSIs instead of a TSV technology. Poly-Ge CMOS devices on insulating layers may be one of solutions for the 3D-LSIs. In this paper, electrical properties and processes of high performance strained Ge nanowire pMOSFETs and poly-Ge trigate pFETs both on buried oxide (SiO2) layers, which are dedicated for the former and the latter applications, respectively, are presented. The Ge nanowire devices were formed by a two-step Ge condensation technique for the channels and a self-aligned NiGe process for the source and drain [1]. A compressive strain of around 4% along the channel direction of was observed after the condensation process, suggesting that no relaxation of the misfit strain between Si and Ge was occurred. A significantly high-hole mobility of 1922 cm2/Vs has been achieved thanks to the high strain and the good interfacial quality between the gate insulator and the Ge channel. Ion/Ioff over 105 has also been attained for the Ge nanowire pMOSFET with a gate length (Lg ) of 45 nm. Poly-Ge junction-less (JL) pFETs with a Lg down to 40 nm were formed on a SiO2 layer on a Si substrate [2]. The poly-Ge channel was naturally p-type with a hole concentration around 5x1018 cm-3 presumably due to the crystalline defects. No additional doping has been done. A high Ion/Ioff of around 105 was observed for narrow fin (7 nm) devices, although wider devices (>11 nm) exhibited degraded cut-off characteristics. We also found that the current drivability was drastically improved by using a flash lamp annealing (FLA) method due to the high hole mobility in the poly-Ge channel. A drain current value of 280 μA/μm was achieved at Vd =-1 V for the Lg =80 nm device [3], which is comparable with that of a mono-crystalline Si-pMOSFET of 130-nm technology node. In summary, two types of GeOI pMOSFETs for near-future high-performance logic CMOS-ICs and low-cost stackable applications were demonstrated. In both types of devices, the GeOI platform and non-planar gate configurations are key technologies to achieve sufficiently high Ion/Ioff values, which is one of major concerns to implement Ge devices into markets. Acknowledgement This work was granted by JSPS through FIRST Program initiated by the Council for Science and Technology Policy (CSTP). References [1] K. Ikeda et al., Symp. VLSI Tech., (2013), T30 [2] Y. Kamata et al., Symp. VLSI Tech., (2013), T94 [3] K. Usuda, ISDRS 2013 WP3-04

Fabrication of bonded Germanium on insulator (GeOI) substrates with thin Al 2 O 3 /SiO 2 buried oxide layers was demonstrated for the first time. Thin Al 2 O 3 layers grown by an atomic-layer deposition method, which have hydroxyl groups on their surfaces, were inserted to Ge/SiO 2 interfaces to strengthen the adhesion between them. The interface bonded in the atmosphere at room temperature without post-anneal processes is flat and exhibits no additional interface. After the wafer bonding, thick GeOI layers were thinned by mechanical polishing, chemical mechanical polishing and O 3 water etching. The flatness of the surface is equivalent to that of commercially available Ge substrates. The interface state density ( D it ) of the Ge/Al 2 O 3 interface is estimated with low-temperature conductance technique and the D it of as low as 3.9 × 10 11 eV −1 cm −2 at the interface is obtained. This value is almost one order of magnitude lower than previously reported D it of Ge/SiO 2 interfaces. These results suggest that negligible negative impact on carrier mobility and sub-threshold characteristics is expected for the back-side interface in the GeOI substrate with thin Al 2 O 3 /SiO 2 BOX layers.

While there have been many demonstrations on n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) in III-V semiconductors showing excellent electron mobility and high drive currents, hole mobility in III-V p-channel MOSFETs (pMOSFETs) has traditionally lagged in comparison to silicon. GaSb is an attractive candidate for high-performance III-V pMOSFETs due to its high bulk hole mobility. We fabricate and study GaSb pMOSFETs with an atomic layer deposition Al2O3 gate dielectric and a self-aligned source/drain formed by ion implantation. The band offsets of Al2O3 on GaSb were measured using synchrotron radiation photoemission spectroscopy. The use of a forming gas anneal to passivate the dangling bonds in the bulk of the dielectric was demonstrated. The density of interface states Dit was measured across the GaSb band gap using conductance measurements, and a midband-gap Dit of 3 × 1011/cm2 eV was achieved. This enabled pMOSFETs with a peak hole mobility value of 290 cm2/Vs.

In X Ga 1− X Sb has the highest hole mobility amongst all III–V semiconductors which can be enhanced further with the use of strain. The use of confinement and strain in In X Ga 1− X Sb quantum wells lifts the degeneracy between the light and heavy hole bands which leads to reduction in the hole effective mass in the lowest occupied band and an increase in the mobility. We present magnetotransport measurements on compressively strained In X Ga 1− X Sb and GaSb quantum wells. Hall-bar and Van de Pauw structures were fabricated and Shubnikov–de Haas oscillations in the temperature range of T = 2–10 K for magnetic fields of B = 0–9 T were measured. The reduction of effective hole mass with strain was quantified. These results are in excellent agreement with modeling results from band structure calculations of the effective hole mass in the presence of strain and confinement.