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This article examines the complex production and exchange networks through which Central Chiapas polities manufactured and imported fine orange pottery. The Jovel Valley of highland Chiapas formed part of the western frontier of the Maya area, traditionally considered a relatively isolated periphery zone. Conversely, the neighboring Central Depression is considered by many scholars to be a corridor for trade, transportation and cultural contact, inhabited by Zoque cultural groups prior to occupation by Chiapanec-speaking people during the Postclassic period. Instrumental Neutron Activation Analysis (INAA) of fine orange pottery samples from sites in the Jovel Valley and Central Depression revealed that they were locally-produced imitations of Balancan Fine Orange ceramic serving dishes from the Lower Usumacinta River region, rather than imported vessels. Our results suggest that potters working independently in the Jovel Valley and Central Depression were making and locally exchanging imitation Balancan ceramics, using many different clay sources/recipes. An interpretive framework of isomorphism adapted from new institutional theory is useful for distinguishing the production of a standardized, elite-attributed, God-N-decorated set of vessels, from multiple, independent potters’ communities, all under the widespread stylistic influence of Balancan-style Fine Orange wares.

This study investigates changes in strategies ofrulership at the early Zoque polity ofChiapa de Corzo, Chiapas, Mexico, from its inception in the Middle Formative period through its peak of political power during the Terminal Formative period. Incorporating data from my survey ofChiapa de Corzo and its hinterland with excavation data from the center, I contrast changes in the organization of ceremonial activity and in the establishment of status differences at the site with strategies employed in the governance of the polity at large. The initial rulers ofChiapa de Corzo adopted civic-ceremonial conventions shared with the Olmec site of La Venta, including the E-Group architectural pattern repeated at a number of sites in Chiapas. In the Late Formative, rulers integrated the E-Group into an architectural template adopted from contemporary capitals in the Maya Lowlands. This new space was less accessible than the earlier Middle Formative ceremonial zone. The adoption of these new traditions was accompanied by increased status differentiation between rulers and subjects. At the same time, there was a reduction in the elaboration of the regional political hierarchy and a decrease in the practice of forced resettlement. The results of this study indicate that the novel ceremonial practices and changes in status differentiation at the capital were accompanied unevenly by interference of rulers in the daily life of the hinterland.

Chip level electromigration (EM) reliability is determined by: 1) the element level EM failure probability used for design guideline generation; and 2) the distribution of EM elements against design limits. Balancing these two factors is critical for a chip design to achieve the best performance while maintaining chip level EM reliability. This paper discusses the relationship between element level and chip level EM failure probability and provides examples of EM evaluation of chip designs.

Understanding and managing both chip-to-package interaction (CPI) and solder bump electromigration (EM) in new designs is becoming an increasing challenge for flip chip plastic ball grid array (FCPBGA) packaging. Requirements for state-of-the-art device technologies drive smaller features, higher power and RoHS compliance (Pb-free product). It will be shown that the optimal attributes for Pb-free solder bump EM performance often are diametrically opposed to the design parameters that improve CPI robustness in structures comprised of low-k dielectric materials.

Stress-induced voids can form in Cu interconnects, due to either thermal expansion mismatch between the metal and the dielectric or due to confined grain growth in the Cu. The fail rate due to stress-induced voids increases as device dimensions decrease, because the critical void size to cause a fail decreases. Good process control is required for trench and via profiles, barrier and seed layer coverage, Cu fill, and cap layer adhesion, to prevent fails from stress-induced voids.

Reliability monitoring is an important part of process control in high-volume production. For metallization, a wafer-level electromigration (WL-EM) test is usually the method of choice to get a good indication of process variation. Different WL-EM methods have been reported, including a constant current method, the SWEAT test, the isothermal test, and the breakdown energy of metal test. The method used in this paper uses the ramping procedure for the isothermal test to achieve the target temperature, but then hold the current constant without feedback correction once the target temperature has been achieved. We present practical normalization procedures to ensure an appropriate wafer-to-wafer comparison that is independent of variation in cross-sectional area as well as of the initial resistance spread. The measurements were performed on a commercially available 200-mm multiside probe station using custom software to implement the current ramp and resistance measurement. Test conditions were achieved through Joule heating; the test structures used were 800-mum-long single lines (no vias) in metal 1 to metal 3, varying in width from 0.14 to 10 mum. Due to variations in the hardware and in the temperature coefficient of resistance (TCR), several normalization steps (described below) were necessary in demonstrating reasonable and expected trends in the data. Results of the analysis suggest that the appropriate value for the current density exponent for this test methodology is two, and they also verify that the TCR varies with linewidth, decreasing as linewidth decreases.

The increasing use of low- k dielectrics as inter/intralevel insulation materials and the aggressive scaling of advanced interconnects generate new challenges for thermal and electromigration (EM) solutions. Accurate specification of design rules and EM reliability modeling for interconnect systems require knowledge of the thermal behavior of the systems. A key parameter that characterizes thermal behavior is the thermal conductivity of the inter/intralevel dielectric (ILD). In practical, very large scale integration (VLSI) applications, the metal interconnects are fully embedded in a stacked, composite ILD media, which present challenges for the accurate determination of thermal conductivity. This article uses the “effective thermal conductivity” concept to model such complicated composite media, and to introduce a simple methodology that accurately measures effective and bulk thermal conductivities of various thin dielectric layers in integrated circuits (IC). We present measured effective conductivities of several composite media, including various Cu/low- k dielectric configurations: Cu/SiCOH, Cu/spin-on organic dielectric (SOD), Cu/fluorinated silicate glass (FSG), and a hybrid stack with Cu lines in SOD and Cu vias in undoped silicate glass (USG). Recorded temperature measurements ranged from 30 to 120 °C using a unique combination of fully embedded Cu lines as heater/thermometers, wafer-level temperature–voltage–power measurements, and the Harmon–Gill (H–G) quasi-analytical heat conduction model. We demonstrated optimal agreement between an experimental method and a finite element simulation, which suggests that this unique technique yields accurate and simple thermal conductivity measurements for complicated systems. Our observations show that thermal conductivities of all films in this study increased with rising substrate temperature.

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low- k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.

Specific details of both fabrication process and geometry of Cu interconnects result in different electromigration (EM) fail modes. This paper discusses EM characteristics of line depletion stress, i.e., for the case of electrons flowing from a via above into a Cu line through a Cu diffusion barrier to cause voiding in the line. For electrons flowing from a W via, for example to a Cu line above, electrical redundancy (i.e., a current shunt layer) exists due to the overlap of line bottom liner over the top of the via, such that a current path still exists in the event that the Cu is removed. When electrons flow from a via above down to a Cu line, the redundancy characteristics can be very different for different via/line layouts, and can result in different EM fail distributions. The solid contact between via above and the liner of the line below can result in tight fail distributions, while weak contact or lack of contact between the via above and the liner of the line below can cause broad (high sigma), or even multimode fail distributions. A few examples and their implications on robust interconnect design are presented. The relation between void size and liner redundancy characteristics is also discussed.

A method is described for making direct characterizations of the early part of the intrinsic electromigration fail-time distribution of interconnects. The method involves stressing a large number of test lines only long enough for a relatively few lines to fail, enough to characterize the percentile of interest. Groups of test lines are electrically monitored to detect failures without having to measure individually the many lines on test. Two types of deep censoring (DC) are described: DC without removals (where more than one line failure in a group can be detected with confidence) and DC with removals (where, when one failure occurs, the other lines in the group are removed from the test). Sample estimates of sigma and of one or more early percentiles of the distribution are corrected for bias and their confidence limits calculated. DC offers important benefits over the present practice of placing tens of test lines on test to obtain sample estimates of t50 and σ that are used to extrapolate to the early part of the loge(fail-time) distribution. The benefits are reduced testing times, better confidence of the sample estimates of early percentages of the distribution, and the ability to detect extrinsic fail-time populations. A detailed procedure to implement the method is provided in the appendix.

Resistance saturation as a function of current density, stripe length, stripe width, and temperature is investigated for a two-level structure with Ti/AlCu/Ti/TiN stripes and interlevel W stud vias. A simple model based on first principles is presented, which relates the maximum fractional resistance change to the current density and stripe length. Experimental results for stripe lengths of 30, 50, 70, and 100 μm are in good agreement with the model predictions. Estimated void sizes based on the resistance saturation data are consistent with the actual void sizes determined from scanning electron microscopy analysis. A weak temperature dependence is found for 0.33 μm-wide samples in the range 170–250°C, while a strong width dependence is observed between 0.33 and 1.50 μm- wide samples. The width dependence is qualitatively explained in terms of a relaxed bulk modulus that depends on the aspect ratio of the interconnect lines.

The electromigration behavior and microstructural features of AlCu Dual Damascene lines are compared to those of AlCu metal reactively ion etched (RIE) lines. Test structures consist of 0.18-, 0.35- and 1.33-μm-wide lines terminated by W diffusion barriers, and are tested at 250°C. A remarkable finding for the 0.18-μm-wide Damascene samples is a threshold-length product of nearly 40 000 A/cm. Different failure mechanisms are revealed for Dual Damascene and metal RIE structures by observing the resistance shift vs. time as well as the lifetime vs. current density behaviors. It is found that the Damascene structures exhibit a long resistance incubation period followed by a rapid increase in resistance, while the RIE structures show a short resistance incubation period followed by a gradual increase in resistance. The current density exponent is found to be close to 2 for the Damascene process and close to 1 for the RIE process. The Damascene samples show a significant lifetime improvement over the RIE samples for low levels of resistance change, while the relative lifetime improvement decreases as the maximum allowed resistance shift increases. In order to understand the electromigration performance of each metallization system, various physical analysis techniques are implemented. The average grain size, determined from transmission electron microscopy (TEM), is found to be significantly larger for Damascene lines due to a higher AlCu deposition temperature. Both TEM and scanning electron microscopy (SEM) analyses indicate that TiAl3 intermetallic formation occurs in both Dual Damascene and RIE lines, but is much more prevalent in the RIE case. Electron backscatter analysis reveals a weak Al crystallographic texture in sub-micron Dual Damascene samples and a strong (111) fiber texture in RIE samples. Optical and SEM inspections illustrate different failure signatures for 0.18 and 0.35 μm Dual Damascene and RIE lines.

Extrusions are a well-known phenomenon in Al interconnect stacks. We review experimental approaches to mitigate extrusions including depositing a low temperature oxide (LTO) on the film stack, modulation of the metal anneal conditions, and moving the anneal step from post-metal etch to post-metal deposition. After evaluation of the three potential solutions we determined that the movement of the anneal step from post-metal etch to post-metal deposition is the most manufacturable process.

Vias are formed in interconnect structures using a polymerizing chemistry in order to avoid etching the underlying metal wires. However, a drawback of the polymerizing chemistry is that etch residues can remain in the via opening, resulting in high via resistance and possible degradation of circuit performance. Although it is well known that etch residues in vias can cause yield loss, the effect on reliability has not been reported for submicron vias. In this paper, the effect of etch residues on via reliability is studied. Vias with etch residues showed no degradation in reliability after a thermal cycle stress, high temperature storage, or humidity stress. However, vias with etch residues fail at a lower current during a wafer level voltage ramp electromigration stress, compared to residue-free vias, suggesting that etch residues will reduce the electromigration lifetime of interconnect structures.

Stress-induced voiding in microelectronic metallization is reviewed with an emphasis on void growth models. Growth models are separated into two classes, those based upon the diffusion equation, and those based on stress uraised to some power n and called power law models. Power law models have been successfully used to describe lifetime dependence on stress and linewidth using n greater or equal to 4, whereas diffusion models have not. By including an exponential dependence of diffusivity on stress of the form exp(dlkr) and by adjusting the metal zero-stress temperature by including the metal deposition temperature, a diffusion model is shown to describe lifetime dependence. on stress, linewidth, and line thickness as well. Advantages and drawbacks to both approaches are discussed. Areas for further work to improve modeling and to improve understanding of void nucleation are suggested.

Physical phenomena underlying failure due to electromigration and stress-induced voiding in fine Al and Al-alloy thin-film conducting lines are examined in the context of accelerated testing methods and structures. Aspects examined include effects due to line isolation (the absence of reservoirs at conductor ends), solute and precipitate phenomena, conductor critical (Blech) length, microstructure, film deposition conditions, and thermal processing subsequent to film deposition. Emphasis is on the isolated, submicron-wide, Al(Cu)-based thin-film interconnection lines of IBM VLSI logic and memory chips.

Summary form only given. The set of traditional back-end-of-line (BEOL) reliability concerns includes electromigration (EM), mechanical stability, stress-induced voiding (SV) and corrosion for aluminum (Al) metallizations. With the introduction of dual-damascene Cu and low-k BEOL dielectric materials, combined with continued reduction in dimensions required for increased circuit density, time-dependent dielectric breakdown (TDDB) of both inter- and intra-level dielectric has become an additional concern. All of the standard testing is still carried on for each of these failure mechanisms, but trends to include large features, such as inductors for RF parts and through-Si vias (TSV's) for chip stacking, in combination with progressively smaller minimum line widths and pitches have lead to a divergence in both testing requirements and test structures to ensure chip reliability. In addition, emerging applications using high voltages, thick wiring levels and thick dielectric layers are requiring much greater test voltages and currents in order to produce failure distributions adequate for lifetime projections. These challenges promise to provide continued entertainment for BEOL Reliability engineers for the next few years.

Two key C4 reliability concerns for the current and next generation integrated circuits are electromigration (EM) and “white C4” bumps caused by the stresses induced by die-package interactions. This paper discusses novel design and integration changes in the final polymeric passivation via (FV) in order to mitigate white bump and chip-package interaction (CPI) stresses in the ultra-low k (ULK) BEOL levels and also meet lead-free C4 EM requirements. FV design changes such as strategically offsetting a single or multiple FV vias towards the center of the chip and thus to the compressive side of the C4 bump has been shown to reduce the stresses in the ULK levels due to chip package interactions and hence significantly reduce the number of white bump fails. Changing the shape of the FV via to strategically distribute current more uniformly through the C4 bumps has also been shown to improve the C4 EM performance significantly, while lowering the overall stresses in the chip. Effects of final passivation thickness and via diameter on the white bump stresses will also be discussed. Supporting white-bump, C4 EM and electrical/mechanical modeling data showing the benefits of the design and integration changes will also be discussed in detail in the paper.

Differential thermal expansion mismatch between Cu and Si along with high aspect ratios required for TSV pose unique challenges to the integration and reliability of Cu TSV. A TSV structure that successfully mitigates these concerns has been integrated into CMOS with high K/metal gates. Data from test structures demonstrate no ‘Cu pumping’ or other deleterious effects to neighboring devices or interconnects. Functional 3D prototypes utilizing stacked embedded DRAMs were demonstrated showing no impact from TSV processing.

Money is not the result of material processes. Its roles in the economy assume a social and moral ethos. In turn, the ethos is dependent upon custom and custom as law. Money does not remember its origins in these prior agreements, and often ignores the moral import of choices affecting its quantity and cost. Money, too, is not subordinate to society, or limited by societal boundaries. Rather, by a reversal, the structures of the social and moral order are themselves shaped by money. Money’s dominance, and therefore its freedom, appears complete. At the same time, however, the network of financial exchange and currency evaluation require formal agreements which assume the global unity and solidarity of a moral order.

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

This chapter contains sections titled: Introduction Considerations on NBTI Stress Configurations Appropriate NBTI Stress Bias Dependence Nature of the NBTI Damage Impact of the NBTI Damage to Key pMOSFET Transistor Parameters Physical Mechanisms Contributing to the NBTI Damage Key Experimental Observations on the NBTI Damage N it Generation by Reaction-Diffusion (R-D) Processes Hole Trapping Modeling NBTI Dependence on CMOS Processes NBTI Dependence on Area Scaling Overview of Key NBTI Features References ]]>

This chapter contains sections titled: Introduction Physics of Degradation and Breakdown Physical Models for Oxide Degradation and Breakdown Experimental Results of Oxide Breakdown Post-Breakdown Phenomena References ]]>

Evaporated metallizations composed of aluminum alloys and titanium underlayers were patterned, passivated with plasma enhanced chemical vapor deposited SiNx and aged for 1000 h at 150 °C in order to observe stress‐induced void formation. Metal films were analyzed using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectrometry. The addition of copper to aluminum results in fewer voids than in comparable noncopper metallizations. For Al–Cu films, fewer voids were observed in 1.5 μm lines compared to 5 μm lines, apparently due to the presence of greater stress gradients in the wide line case. Silicon appears to promote void formation by rapid grain boundary diffusion to precipitates. Oxygen incorporation in aluminum produces small grained films, thereby generating many void nucleation sites. High oxygen concentrations produce films with a few long, channel‐like voids and many small voids. Titanium underlayers decrease the percent of metal volume voided for Al and AlS...

In this study, a novel method is explored for improving the electromigration lifetime of Cu wires, using Ta implantation into Cu. For high implant doses (2E15 cm−2), the electromigration lifetime is improved by over 5X using this method. An increase in lifetime is achieved, even for an average surface concentration of Ta on the order of 0.1 atm%. We propose that the improvement in electromigration lifetime is due to the reduction of defects at the SiN/Cu interface due to the presence of Ta. The line-to-line leakage at high voltages (> 5V) increases with the Ta implant, with higher leakage at higher Ta concentrations, so the Ta dose must be limited to avoid excessive leakage.

In this study, a novel method is explored for improving the electromigration lifetime of Cu wires, using a blanket Ta implantation into both the oxide and Cu on the surface of a wafer. For the highest implant dose, the electromigration lifetime is improved by over 5X using this method, with a minimal increase in wire resistance. An increase in lifetime is achieved, even for an average surface concentration of Ta on the order of 0.1 atm%. The line-to-line leakage at high voltages (> 5 V) increases with the Ta implant, with higher leakage at higher Ta concentrations. The lifetime for time dependent dielectric breakdown (TDDB) is significantly degraded for high Ta doses, but not for lower Ta doses, suggesting that there may be a window for improving electromigration lifetime while maintaining high dielectric reliability.

Reliability monitoring is an important part of process control in high volume production. For the back end of line (BEOL), a wafer-level electromigration (WL-EM) test is usually the method of choice to get a good indication of process variation (Schuster, 2001). In this work we present practical normalization procedures to ensure an appropriate wafer to wafer comparison which is independent of variation in cross-sectional area as well as of the initial resistance spread. The measurements have been performed on a commercially available 300mm multi-side probe station, using custom-made software to implement the current ramp and resistance measurement. The test conditions were achieved through Joule heating; the test structures used were 800mum long single lines (no vias) in metal 1 to metal 3, varying in width from 0.14mum to 10mum. After several normalization steps described in this paper we found a strong activation energy dependence on line width. This dependence was linked to issues in temperature investigation using a constant TCR value. Additionally we found a simple way to estimate the current density exponent by optimizing the Arrhenius relation. Overall a comprehensive guideline for constant current WL-EM is presented

During the development and qualification of a 300mm low-k/Cu Back End of Line (BEOL) technology, the long-term reliability of such interconnects including low-k time-dependent dielectric breakdown (TDDB), Cu Electromigration (EM), Cu stress migration (SM), and Cu/low-k thermal behavior are rapidly becoming one of the most critical challenges. In this paper, a comprehensive reliability evaluation for 65nm Cu/low-k interconnects is reported and various reliability issues associated with process integration and material optimization during initial development stage are discussed. Finally, we demonstrate that with careful process and materials optimization, a superior interconnect reliability performance at the 65nm technology node can be achieved for 300mm fabrication. The projected reliability lifetimes of TDDB, EM, and SM meet the most stringent reliability targets and criteria.

In the course of Cu/low-k technology development and qualification, low-k time-dependent dielectric breakdown (TDDB) is rapidly becoming one of the most important reliability issues. In order to accurately predict low-k TDDB reliability, it is crucial to clarify the electric field dependence and temperature dependence of time-to-breakdown. In this study, bias-temperature stresses of CVD low-k SiCOH dielectric at the 65nm technology node were conducted over a wide range of fields and temperatures. Based on the extensive long-term test results (longer than one year), it was found that the "square-root of E" (radicE) dependence seems to be the best choice for modeling field dependent TDDB data. It was also determined that the TDDB activation energy is dependent on electric field, and that the field acceleration parameter for the radicE model decreases with increasing temperature. The physical mechanism behind radicE and the role of Cu diffusion during bias-temperature-stress are discussed, and an electron-fluence-driven, Cu-catalyzed SiCOH breakdown model is introduced. Finally, it is emphasized that great care must be taken in evaluating low-k dielectric TDDB when different stress fields and temperatures are used for chip operational lifetime projections

Broad failure time distributions were observed for line depletion electromigration in Cu interconnects for various structures without sufficient liner contact and via redundancy. The root cause for this behavior was identified as the sensitivity of failure times to the void size, shape and location. Application of the traditional 2-parameter lognormal distribution model to corresponding stress data often results in very pessimistic EM lifetime projections. A 3-parameter lognormal distribution was found not only to fit the experimental data better, especially for the early portion of the failure time distributions, but also to generate more accurate lifetime projections for void-size-limited EM. Given the nature of EM wear-out, deeper consideration indicates that a 3-parameter lognormal distribution has a sounder physical basis than a 2-parameter lognormal distribution. The new parameter introduced in the model, the minimum failure time (X0 ), scales with via size over several technology generations, further validating the minimum void size explanation

Damascene processing creates special features for copper interconnect electromigration (EM). Though the fast Cu diffusion path is along the interface between Cu and the top cap layer, the early EM fails are often associated with vias, either by voiding in the via (via depletion), or by voiding underneath the via (line depletion). While most of the early EM fails for via depletion are related to the liner quality in vias, for line depletion EM the contact configuration between the via and the underlying line is critical to the failure characteristics. The contact between the via and the line liner below can effectively prevent or minimize open-circuit type EM failures. Redundant vias can significantly improve the EM performance in both the median failure time (t/sub 50/) and the distribution shape (sigma, /spl sigma/), depending on the arrangement of these vias relative to the line below. This paper presents an EM study of Cu interconnects with various via/line contact configurations. Results from single via and multiple via contacts, with and without redundancy to the underlying lines, are discussed.

The combination of low k dielectric material application and aggressive scaling in advanced interconnects creates new challenges for thermal and electromigration solutions. The complexity and difficulty are discussed for modeling and evaluating thermal and EM interactions in circuit designs. A few examples are given to show quantitatively the impact of different dielectric materials on maximum allowed current density and scaling in Cu lines.

Accurate specification of design groundrules for interconnect systems requires knowledge of the thermal behavior of the systems. A key parameter that characterizes the thermal behavior is the thermal conductivity of the inter-level dielectric (ILD). In practical VLSI applications, the metal interconnects are fully embedded in a stacked, composite ILD media, which presents difficult challenges for the accurate determination of thermal conductivity. In this paper, we propose the concept of an "effective thermal conductivity" to model such complicated, composite media, and introduce a simple methodology to accurately measure effective and bulk thermal conductivities of various thin dielectric layers in integrated circuits. We present measured effective conductivities of several composite media, including various Cu/low-k dielectric configurations such as Cu/SiCOH, Cu/SiLK/sup /spl reg//, Cu/fluorinated silicate glass (FSG), and a hybrid stack with Cu lines in SiLK/sup /spl reg// and Cu vias in un-doped silicate glass (USG). Measurements were recorded in the temperature range from 30/spl deg/C to 120/spl deg/C using a unique combination of fully embedded Cu lines as heater/thermometers, wafer-level temperature vs. power (TVP) measurements, and the Harmon-Gill (H-G) quasi-analytical heat conduction model. The thermal conductivities of all the films studied here were observed to increase with rising substrate temperature.

TAN resistors are commonly used in RFIC applications and are gaining acceptance in traditional CMOS designs. TAN materials, frequently used in fabrication of Cu interconnects can easily be applied to the fabrication of thin film resistors. Deposition and integration of the films may be well controlled to produce a high precision resistor, and the temperature coefficient of resistance (TCR) characteristics of the film make it ideally suited for application across a large temperature range. While the time zero characteristics of the device are well understood, of equal importance are the device reliability properties. In this paper traditional film characteristics such as resistance distributions and TCR characteristics are presented. A voltage ramp stress is employed to identify the critical current A constant voltage stress at high temperature is utilized for reliability evaluation. Based on the stress results, a reliability degradation model is derived to express the relationship between stress condition, resistance change, and lifetime. The results demonstrate that the TAN thin film resistor is reliable over traditional IC operating ranges. While TAN resistors are robust, application conditions of the resistor typically result in significant resistive joule heating. The joule heating effects on the resistor are included in the resistor degradation model. The effects of the joule heating on reliability for neighboring structures must also be considered. The effective result is that the maximum allowed use current of the resistor might be dictated by the resistive joule heating and not necessarily the resistor reliability itself. The effect of the joule heating on neighboring structures is a subject itself and will not be covered in this paper.

Specific details of fabrication process and geometry of Cu interconnects result in different electromigration (EM) fail modes. This paper discusses EM characteristics of line depletion mode stress, i.e. for the case of electrons flowing into a Cu line through a Cu diffusion barrier to cause voiding in the line. For electrons flowing from a W via, for example to a Cu line above, redundancy exists due to the overlap of line bottom liner over the top of the via. When electrons flow from a via above down to a Cu line, the redundancy characteristics can be very different for different via/line layouts and result in different EM fail distributions. The solid contact between via and the liner of the line below can result in tight fail distributions, while weak contact or lack of contact between the via and the liner of the line below can cause broad (high sigma), or even multi-mode fail distributions. A few examples and their implications on robust interconnect design are presented. The relation between void size and liner redundancy characteristics is also discussed.

Wafer level electromigration behavior of copper and aluminum using isothermal stress was investigated in this paper. Lifetime, lognormal standard deviation, and activation energy were evaluated as a function of stress temperature as well as line width. Temperature dependence of the embedded 2D thermal behavior was modeled via the initial stress current versus the initial resistance correlations. The mass transport mechanisms in the highly accelerated wafer level electromigration were observed to be the same as those in moderately accelerated conventional package level electromigration for both Cu-based and Al-based systems.

Electromigration is a well-known wearout mechanism for metallic interconnects on integrated circuit chips, and has been studied for decades in Al metallization, and for the last several years in Cu metallization. Chip failure is caused by either catastrophic electrical open or by resistance shifts sufficiently large to cause functional failure. The failure mechanism is the creation of a hole or void in the primary conductive layer of the interconnect, caused by a divergence in atomic diffusion in the direction of electron flow. Electromigration results for a 264 sample electromigration study performed on dual damascene copper interconnects are presented and reviewed. The stress results show multi-modal failure distributions and extensive failure analysis provides possible explanations as to the failure modes. Monte Carlo type simulations are used to investigate the statistical implications of using bi-modal fitting to predict reliability performance.

Previous investigations into thermal characteristics of embedded interconnects produced a wafer level technique for measurement of the thermal conductance, as well as a quasi-analytical model for predicting the results (Harmon, Gill and Sullivan, IRW 1998). In this paper, measurements of the thermal characteristics of embedded interconnects with underlying insulator thicknesses from 1.0 to 0.1 /spl mu/m are presented. These measurements indicate the thermal conductance for thin insulators is significantly less than that predicted by the quasi-analytical model. Through finite element modeling, this discrepancy is shown to be due to localized substrate heating. An "effective conductivity" method is presented to extend the quasi-analytical model to include substrate-heating effects. This same approach is proposed for analysis of composite insulator structures including low K dielectrics. The methodology is assessed by comparing modeled and measured fuse current densities for embedded interconnects of varying width and underlying insulator thickness.

A physical model has been developed that describes the formation of titanium silicide from deposited titanium films on silicon substrates during furnace annealing. The model for TiSi/sub 2/ formation consists of set of diffusion-reaction equations and a set of equations for the mechanical behavior of the materials present. Some of the parameters for the model have been obtained from data in the literature. A one-dimensional computer implementation of the model has been developed that shows the time evolution of the growing layers and their constituents. This is useful for understanding the mechanisms that determine the relative thicknesses of various layers, like TiSi/sub 2/ and TiN, that grow at different temperatures during N/sub 2/ annealing. >