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The length of the transit region of a Gunn diode determines the natural frequency at which it operates in fundamental mode-the shorter the device, the higher the frequency of operation. The long-held view on Gunn diode design is that for a functioning device the minimum length of the transit region is about 1.5 μm, limiting the devices to fundamental mode operation at frequencies of roughly 60 GHz. Study of these devices by more advanced Monte Carlo techniques that simulate the ballistic transport and electron-phonon interactions that govern device behaviour, offers a new lower bound of 0.5 μm, which is already being approached by the experimental evidence that has shown planar and vertical devices exhibiting Gunn operation at 600 nm and 700 nm, respectively. The paper presents results of the first ever THz submicron planar Gunn diode fabricated in In0.53Ga0.47As on an InP substrate, operating at a fundamental frequency above 300 GHz. Experimentally measured rf power of 28 μW was obtained from a 600 nm long × 120 μm wide device. At this new length, operation in fundamental mode at much higher frequencies becomes possible-the Monte Carlo model used predicts power output at frequencies over 300 GHz. [ABSTRACT FROM AUTHOR]

The admittances and subthreshold characteristics of capacitors and MOSFETs on buried and surface In0.53Ga0.47As channel flatband wafers, with a dielectric of Al2O3 deposited on In0.53Ga0.47As, are reported. The admittance characteristics of both wafers indicate the presence of defect states within the oxide, in common with a number of other oxides on In0.53Ga0.47As. The two wafers studied have not been hydrogen annealed, but do show some similar features to FGA treated oxides on n+ substrates. We discuss how the possible presence of residual hydroxyl ions in as-grown Al2O3 may explain these similarities and also account for many of the changes in the properties of FGA treated n+ samples. The issues around the comparison of subthreshold swing (SS) results and the impact of transistor design parameters on the energy portion of the defect state distribution affecting efficient device switching are discussed. The interface state model is applied to low source-drain voltage SS data to extract an effective interface state density (Dit) that includes interface and oxide traps. The logarithmic gate voltage sweep rate dependence of the SS Dit is used to extract an oxide trap density (Dot) and a simple method is used to estimate the Fermi level position within the band gap, Et. The Al2O3 Dit(Et) and Dot(Et) distributions are found to be similar to each other and to the results of our analysis of Gd0.25Ga0.15O0.6/Ga2O3 and HfO2/Al2O3 on In0.53Ga0.47As, adding weight to the suggestion of there being a common defect state distribution and perhaps a common cause of defects states for a number of oxides on In0.53Ga0.47As. [ABSTRACT FROM AUTHOR]

The admittance characteristics of a well understood oxide system of Gd0.25 Ga0.15 O0.60/Ga2 O3 on In0.53 Ga0.47As are studied at low temperature where the majority of the defect states are frozen. The capacitance-voltage (C-V) characteristics are broadened beyond those expected for an ideal sample. The broadening is ascribed to the presence of a non-uniform surface potential. We report a simple method for measuring the surface potential distribution width using the ac signal amplitude dependence of the C-V profile. A distribution of surface potentials can explain the observed behavior, but only if it includes the admittance of the semiconductor. This is in contrast to the usual approximation that the effect of a distribution of surface potentials on the admittance of the semiconductor is ignored. It is found that the charge state of defect states in the oxide and variation in the doping density of the substrate contribute to the broadening. The implications for inclusion of the semiconductor admittance for the interpretation of ideal characteristics and for the analysisof characteristics with interface states are explored. Both the conductance method and the quasi-equilibrium C-V methods are affected to some extent. An alternative method that can more accurately extract information from the admittance characteristics of the MOS samples is proposed. [ABSTRACT FROM AUTHOR]

The admittances and subthreshold characteristics of capacitors and MOSFETs on buried InxGa1-xAs channel wafers with a dielectric stack of Gd0.25Ga0.15O0.6/Ga2O3 deposited on GaAs and In0.53Ga0.47As are reported. Both the GaAs and InGaAs interface samples show admittance characteristics indicative of the presence of defect states within the oxide, in agreement with previously reported data from the same oxides on n+ substrates. The interface state model is applied to the admittance data to extract an apparent interface state density (Dit) that includes interface and oxide states. The Dit profiles are very different and have pronounced effects on the device performance. The device subthreshold swings (SS) at low source-drain voltages are also used to extract an apparent Dit. A simple method is used to estimate the Fermi-level position within the bandgap (Et) at threshold, and the resulting Dit(Et) are found to be in good agreement with the admittance data. The importance of proper interpretation of SS and Dit in general and in GaAs interface devices in particular is emphasized. A model that accounts for the logarithmic sweep rate dependence of the extracted Dit due to the presence of oxide states is reported and used to estimate their density from SS measurements. The implications of the band parameters of an oxide with defect states within it for the comparison of different oxides on the same substrate and the issues around the comparison of results in general are discussed. [ABSTRACT FROM AUTHOR]

The electrical characteristics of n+ GaAs and In0.53Ga0.47As MOS capacitors with a dielectric stack of Ga2O3/Gd0.25Ga0.15O0.6 have been examined in detail and compared to the interface state model. The deviations from the model are assessed and the limitations of different interface state density extraction techniques are highlighted. The results of a model which accounts for many of the electrical characteristics of the InGaAs material by including states within the oxide and at the interface are reported. A hypothesis that may explain the difference between the GaAs and InGaAs characteristics and the similarities between the properties of many different oxides on InGaAs is discussed, leading to suggestions on how the oxide quality may be improved. [ABSTRACT FROM AUTHOR]

Test devices have been fabricated on two specially grown GaAs/AlGaAs wafers with 10 nm thick gate dielectrics composed of either Ga2O3 or a stack of Ga2O3 and Gd0.25Ga0.15O0.6. The wafers have two GaAs transport channels either side of an AlGaAs barrier containing a Si δ-doping layer. Temperature dependent capacitance-voltage (C-V) and current-voltage (I-V) studies have been performed at temperatures between 10 and 300 K. Bias cooling experiments reveal the presence of DX centers in both wafers. Both wafers show a forward bias gate leakage that is by a single activated channel at higher temperatures and by tunneling at lower temperatures. When Gd0.25Ga0.15O0.6 is included in a stack with 1 nm of Ga2O3 at the interface, the gate leakage is greatly reduced due to the larger band gap of the Gd0.25Ga0.15O0.6 layer. The different band gaps of the two oxides result in a difference in the gate voltage at the onset of leakage of ∼3 V. However, the inclusion of Gd0.25Ga0.15O0.6 in the gate insulator introduces many oxide states (≥4.70×1012 cm-2). Transmission electron microscope images of the interface region show that the growth of a Gd0.25Ga0.15O0.6 layer on Ga2O3 disturbs the well ordered Ga2O3/GaAs interface. We therefore conclude that while including Gd0.25Ga0.15O0.6 in a dielectric stack with Ga2O3 is necessary for use in device applications, the inclusion of Gd decreases the quality of the Ga2O3/GaAs interface and near interface region by introducing roughness and a large number of defect states. [ABSTRACT FROM AUTHOR]

We report the first demonstration of InAs FinFETs with fin width \textrm W{\mathrm{fin}} in the range 25–35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height \textrm H{\mathrm{fin}}=20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length \textrm L{{\textrm {g}}}=1~\mu \text{m} , peak transconductance \textrm g{{\textrm {m,{\mathrm{ peak}}}}}=1430~\mu \text{S}/\mu \text{m} is measured at \textrm V{\textrm {d}}=0.5 V demonstrating that electron transport in InAs fins can match planar devices. [ABSTRACT FROM PUBLISHER]

We report the modification and control of threshold voltage in enhancement and depletion mode AlGaN/GaN metal-insulator-semiconductor heterostructure field effect transistors through the use of in-situ fluorine doping of atomic layer deposition Al2O3. Uniform distribution of F ions throughout the oxide thickness are achievable, with a doping level of up to 5.5 × 1019 cm-3 as quantified by secondary ion mass spectrometry. This fluorine doping level reduces capacitive hysteretic effects when exploited in GaN metal-oxide-semiconductor capacitors. The fluorine doping and forming gas anneal also induces an average positive threshold voltage shift of between 0.75 and 1.36V in both enhancement mode and depletion mode GaN-based transistors compared with the undoped gate oxide via a reduction of positive fixed charge in the gate oxide from +4.67 × 1012 cm-2 to -6.60 × 1012 cm-2. The application of this process in GaN based power transistors advances the realisation of normally off, high power, high speed devices. [ABSTRACT FROM AUTHOR]

The potential performance of implant free heterostructure In0.3Ga0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications [ABSTRACT FROM PUBLISHER]

We present the first results of a planar Gunn diode made in \In0.53\Ga0.47\As on an InP substrate, operating at a fundamental frequency up to 164 GHz. For a 120-\mu\m-wide device with a 1.3- \mu\m active channel length, the highest power achieved was approximately -10 dBm at 164 GHz. [ABSTRACT FROM AUTHOR]

A parallel coupled-line planar bandpass filter (BPF) with branch-line shape using coplanar waveguide technology on GaAs substrate is presented. The unit parallel coupled-line BPF utilises a parallel coupled-line resonator with an open-ended stub which has suppression response of spurious band. Four unit parallel coupled-line BPFs are integrated with branch-line shape and open-circuit stubs on input and output ports are also integrated for improvement of rejection performance. The proposed fourth-order filter was fabricated on GaAs substrate with dielectric thickness of 50 µm and gold thickness of 1.2 µm. The fabricated fourth-order BPF shows a 3 dB bandwidth from 177 to 209 GHz frequency range with insertion loss of 6.5 dB, rejection of 38 dB and return loss better than 12 dB. It has a high resolution fractional bandwidth of 17% [ABSTRACT FROM AUTHOR]

A broadband low-loss, ultra-low-power consumption transmit/receive switch using high-performance 50 nm gate-length metamorphic high electron mobility transistors (MHEMTs) is presented. The single pole double throw (SPDT) monolithic switch utilises a drain contact electrode sharing concept using a two-finger MHEMT. An optimal gate width of the MHEMT was chosen for low-loss, high-isolation performance and circuit compactness. The switch shows a broadband operation from DC to 35 GHz with insertion loss less than 1.9 dB, isolation better than 27 dB, and P1 dB better than 12 dBm with DC power consumption of less than 6 µW. [ABSTRACT FROM AUTHOR]

The first demonstration of implant-free, flatband-mode In0.75Ga0.25As channel n-MOSFETs is reported. These 1 µm gate length MOSFETs, fabricated on a structure with average mobility of 7720 cm2/Vs and sheet carrier concentration of 3.3×1012 cm-2, utilise a Pt gate, a high-κ dielectric (κ≃20), and a δ-doped InAlAs/InGaAs/InAlAs heterostructure. The devices have a typical maximum drive current (Id,sat) of 933 µA/µm, extrinsic transconductance (gm) of 737 µS/µm, gate leakage (Ig) of 40 pA, and on-resistance (Ron) of 555 Ω · µm. The gm and Ron figures of merit are the best reported to date for any III-V MOSFET. [ABSTRACT FROM AUTHOR]

Data is reported from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 µA/µm (Vg=Vd=1.5 V), extrinsic transconductance (gm) of 426 µS/µm, gate leakage ( jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω µm. The gm and Ron metrics are the best values reported to date for III–V MOSFETs, and indicate their potential for scaling to deca-nanometre dimensions. [ABSTRACT FROM AUTHOR]

GaAs-based transistors with the highest ƒT and lowest noise figure reported to date are presented in this letter. A 50-nm T-gate In0.52Al0.48As/In0.53Ga0.47As Metamorphic high-electron mobility transistors (mHEMTs) on a GaAs substrate show ƒT of 440 GHz, fmax of 400 GHz, a minimum noise figure of 0.7 dB and an associated gain of 13 dB at 26 GHz, the latter at a drain current of 185 mA/mm and gm of 950 mS/mm. In addition, a noise figure of below 1.2 dB with 10.5 dB or higher associated gain at 26 GHz was demonstrated for drain currents in the range 40 to 470 mA/mm at a drain bias of 0.8 V. These devices are ideal for low noise and medium power applications at millimeter-wave frequencies. [ABSTRACT FROM AUTHOR]

The 300-K admittance characteristics of n+ In0.53Ga0.47As MOS capacitors with a dielectric stack of Gd0.25Ga0.15O0.6/Ga2O3 in as-grown condition are examined in detail and compared to an oxide trap model that we previously introduced. The model explains many of the observed features not contained in the interface state model. By fitting the model to experimental data, we extract a distribution of defect states in space and energy within the oxide and at the oxide/semiconductor interface separately. Oxide states are the dominant defects over a wide range of energy. The defect state densities are not subject to the usual resolution limits of conventional analyses. Using this approach, it is possible to characterize relatively rapidly a wide range of energies at a single temperature without the need for reaching the low or high limits of frequency. The implications for the conventional interface state density (Dit) extraction techniques are explored. It is shown how oxide states can affect the extraction of sample parameters, particularly the insulator capacitance, and can result in a range of extracted Dit values. We believe these contribute to the wide range of Dit reported in the literature from similar admittance characteristics of a number of oxides on In0.53Ga0.47As. [ABSTRACT FROM AUTHOR]

The impact of the stress in room temperature inductively coupled plasma chemical vapour deposited (ICP-CVD) SiNx surface passivation layers on off-state drain (IDS-off) and gate leakage currents (IGS) in AlGaN/GaN high electron mobility transistors (HEMTs) is reported. IDS-off and IGS in 2 μm gate length devices were reduced by up to four orders of magnitude to ~10 pA/mm using a compressively stressed bilayer SiNx passivation scheme. In addition, Ion/Ioff of ~1011 and subthreshold slope of 68 mV/dec were obtained using this strain engineered surface passivation approach. [ABSTRACT FROM AUTHOR]